Compare commits
9 Commits
Author | SHA1 | Date | |
---|---|---|---|
27b32bd462 | |||
d755d1382e | |||
f35be86a71 | |||
e473216eba | |||
e4f6fd2d36 | |||
d05f1de3b1 | |||
efd7ebbe36 | |||
77fa66a6d9 | |||
639c0e9bb9 |
4
Makefile
4
Makefile
@ -1,6 +1,6 @@
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||||
PRG = blmc
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OBJ = blmc.o eeprom.o i2c-slave.o main.o
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MCU_TARGET = atmega8
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MCU_TARGET = atmega88
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OPTIMIZE = -Os
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DEFS =
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@ -61,4 +61,4 @@ ebin: $(PRG)_eeprom.bin
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install: text
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# uisp -dprog=avr910 -dserial=/dev/ttyS0 -dspeed=115200 -dpart=M8 --erase --upload if=$(PRG).hex
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avrdude -p m8 -c butterfly -b 115200 -P /dev/ttyUSB1 -u -e -V -U flash:w:$(PRG).hex
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avrdude -p m88 -c butterfly -b 115200 -u -e -V -U flash:w:$(PRG).hex
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9
README
9
README
@ -1,8 +1,11 @@
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blmc v1
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blmc v2
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=======
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An AVR mega8 based brushless motor controller.
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- SW/HW and i2c protocol are *NOT* compatible with H+I blctrl!
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An AVR mega88/168 based brushless motor controller.
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- must run with TWIBOOT as bootloader to get own i2c address
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- spinup parameters in EEPROM
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- extended i2c protocol
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TODO:
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- remove C1/C3/C6 and do "timed" commutation
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- replace C11 with smaller value / remove it
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|
120
blmc.c
120
blmc.c
@ -31,67 +31,86 @@ static uint8_t next_sense;
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void trigger_adc(uint8_t channel)
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{
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/* Disable Analog Comperator */
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ACSR &= ~(1<<ACIE);
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/* Disable Analog Comperator Interrupt */
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TIMSK1 &= ~(1<<ICIE1);
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/* set channel (Internal reference, 2.56V) */
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ADMUX = (1<<REFS1) | (1<<REFS0) | channel;
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/* set channel (external reference, 5V) */
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ADMUX = (0<<REFS1) | (0<<REFS0) | channel;
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/* turn on ADC with interrupts, start conversion with 1/32 of F_CPU */
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ADCSRA = (1<<ADEN) | (1<<ADSC) | (1<<ADIE) | (1<<ADIF)| (1<<ADPS2) | (1<<ADPS0);
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/*
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* turn on ADC with interrupts
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* start conversion with 1/32 of F_CPU
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* 1/250kHz * 25 => 100us conversion time
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*/
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ADCSRA = (1<<ADEN) | (1<<ADSC) | (1<<ADIE) | (1<<ADIF)| (1<<ADPS2) | (0<<ADPS0);
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}
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void next_phase(void)
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static void next_phase(void)
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{
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static uint8_t phase;
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static uint8_t phase_adc;
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/* Disable Analog Comperator */
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ACSR &= ~(1<<ACIE);
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TCNT1 = 0x00;
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TCNT2 = 0x00;
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/* Disable Analog Comperator Interrupt */
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TIMSK1 &= ~(1<<ICIE1);
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switch (phase) {
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case 0: PORTD = (PORTD & ~PHASE_L_MASK) | PHASE_B_L;
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TCCR1A = (TCCR1A & ~(1<<COM1B1)) | (1<<COM1A1);
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TCCR2 &= ~(1<<COM21);
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ACSR = (1<<ACIS1);
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case 0: /* A: PWM, B: LOW, C: SENSE => disable EN_C, disable PWM_B, enable EN_B */
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PORTD &= ~PHASE_C_EN;
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TCCR0A &= ~PHASE_B_OC;
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PORTD |= PHASE_B_EN;
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/* C: falling edge */
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TCCR1B &= ~(1<<ICES1);
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next_sense = SENSE_C;
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break;
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case 1: PORTD = (PORTD & ~PHASE_L_MASK) | PHASE_B_L;
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TCCR1A &= ~((1<<COM1A1) | (1<<COM1B1));
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TCCR2 |= (1<<COM21);
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ACSR = (1<<ACIS1) | (1<<ACIS0);
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case 1: /* A: SENSE, B: LOW, C: PWM => disable EN_A, enable PWM_C, enable EN_C */
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PORTB &= ~PHASE_A_EN;
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TCCR2A |= PHASE_C_OC;
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PORTD |= PHASE_C_EN;
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/* A: rising edge */
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TCCR1B |= (1<<ICES1);
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next_sense = SENSE_A;
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break;
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case 2: PORTD = (PORTD & ~PHASE_L_MASK) | PHASE_A_L;
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TCCR1A &= ~((1<<COM1A1) | (1<<COM1B1));
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TCCR2 |= (1<<COM21);
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ACSR = (1<<ACIS1);
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case 2: /* A: LOW, B: SENSE, C: PWM => disable EN_B, disable PWM_A, enable EN_A */
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PORTD &= ~PHASE_B_EN;
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TCCR2A &= ~PHASE_A_OC;
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PORTB |= PHASE_A_EN;
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/* B: falling edge */
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TCCR1B &= ~(1<<ICES1);
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next_sense = SENSE_B;
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break;
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case 3: PORTD = (PORTD & ~PHASE_L_MASK) | PHASE_A_L;
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TCCR1A = (TCCR1A & ~(1<<COM1A1)) | (1<<COM1B1);
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TCCR2 &= ~(1<<COM21);
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ACSR = (1<<ACIS1) | (1<<ACIS0);
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case 3: /* A: LOW, B: PWM, C: SENSE => disable EN_C, enable PWM_B, enable EN_B */
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PORTD &= ~PHASE_C_EN;
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TCCR0A |= PHASE_B_OC;
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PORTD |= PHASE_B_EN;
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/* C: rising edge */
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TCCR1B |= (1<<ICES1);
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next_sense = SENSE_C;
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break;
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case 4: PORTD = (PORTD & ~PHASE_L_MASK) | PHASE_C_L;
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TCCR1A = (TCCR1A & ~(1<<COM1A1)) | (1<<COM1B1);
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TCCR2 &= ~(1<<COM21);
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ACSR = (1<<ACIS1);
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case 4: /* A: SENSE, B: PWM, C: LOW => disable EN_A, disable PWM_C, enable EN_C */
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PORTB &= ~PHASE_A_EN;
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TCCR2A &= ~PHASE_C_OC;
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PORTD |= PHASE_C_EN;
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/* A: falling edge */
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TCCR1B &= ~(1<<ICES1);
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next_sense = SENSE_A;
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break;
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case 5: PORTD = (PORTD & ~PHASE_L_MASK) | PHASE_C_L;
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TCCR1A = (TCCR1A & ~(1<<COM1B1)) | (1<<COM1A1);
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TCCR2 &= ~(1<<COM21);
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ACSR = (1<<ACIS1) | (1<<ACIS0);
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case 5: /* A: PWM, B: SENSE, C: LOW => disable EN_B, enable PWM_A, enable EN_A */
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PORTD &= ~PHASE_B_EN;
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TCCR2A |= PHASE_A_OC;
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PORTB |= PHASE_A_EN;
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/* B: rising edge */
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TCCR1B |= (1<<ICES1);
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next_sense = SENSE_B;
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break;
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}
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@ -114,8 +133,10 @@ void next_phase(void)
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ADMUX = next_sense;
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/* enable Analog Comparator with Interrupts */
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if (blmc.flags & FLAG_COM_NORMAL)
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ACSR |= (1<<ACIE) | (1<<ACI);
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if (blmc.flags & FLAG_COM_NORMAL) {
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TIFR1 |= (1<<ICF1);
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TIMSK1 |= (1<<ICIE1);
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}
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}
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phase++;
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@ -207,12 +228,21 @@ void setpwm(uint8_t pwm)
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if (pwm > params.pwm_max)
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pwm = params.pwm_max;
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OCR1A = pwm;
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OCR1B = pwm;
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OCR2 = pwm;
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OCR0B = pwm;
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OCR2A = pwm;
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OCR2B = pwm;
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/* disable PWM signales, enable all drivers -> brake */
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if (pwm == 0) {
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TCCR0A &= ~PHASE_B_OC;
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TCCR2A &= ~(PHASE_A_OC | PHASE_C_OC);
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PORTB |= PHASE_A_EN;
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PORTD |= (PHASE_B_EN | PHASE_C_EN);
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}
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}
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ISR(ANA_COMP_vect)
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ISR(TIMER1_CAPT_vect)
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{
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next_phase();
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}
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@ -232,8 +262,10 @@ ISR(ADC_vect)
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ADCSRA = 0x00;
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/* enable Analog Comparator with Interrupts */
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if (blmc.flags & FLAG_COM_NORMAL)
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ACSR |= (1<<ACIE) | (1<<ACI);
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if (blmc.flags & FLAG_COM_NORMAL) {
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TIFR1 |= (1<<ICF1);
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TIMSK1 |= (1<<ICIE1);
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}
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if (channel == SENSE_CURRENT) {
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current_tmp += value;
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2
blmc.h
2
blmc.h
@ -1,6 +1,8 @@
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#ifndef _BLMC_H_
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#define _BLMC_H_
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#include <avr/io.h>
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#define FLAG_RUN_MASK 0x00F
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#define FLAG_PWM_SPINUP 0x001
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#define FLAG_PWM_NORMAL 0x002
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Before Width: | Height: | Size: 40 KiB |
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Before Width: | Height: | Size: 16 KiB |
BIN
eagle/blmc-v2-bot.png
Normal file
BIN
eagle/blmc-v2-bot.png
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After Width: | Height: | Size: 19 KiB |
BIN
eagle/blmc-v2-sch.png
Normal file
BIN
eagle/blmc-v2-sch.png
Normal file
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After Width: | Height: | Size: 45 KiB |
BIN
eagle/blmc-v2-top.png
Normal file
BIN
eagle/blmc-v2-top.png
Normal file
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After Width: | Height: | Size: 19 KiB |
BIN
eagle/blmc.brd
Normal file
BIN
eagle/blmc.brd
Normal file
Binary file not shown.
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Binary file not shown.
10
eeprom.c
10
eeprom.c
@ -16,11 +16,12 @@
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#include <avr/pgmspace.h>
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#include <avr/eeprom.h>
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#include <util/crc16.h>
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#include "eeprom.h"
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static const struct ee_param defaults = DEFAULT_PARAMETERS;
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static struct ee_param defaults PROGMEM = DEFAULT_PARAMETERS;
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struct ee_param params;
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struct ee_param params_in_eeprom EEMEM = DEFAULT_PARAMETERS;
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@ -48,12 +49,7 @@ uint8_t read_parameters(void)
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crc = _crc_ccitt_update(crc, *tmp++);
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if (crc != 0x0000) {
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i = sizeof(struct ee_param);
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uint8_t *src = (uint8_t *)&defaults;
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uint8_t *dst = (uint8_t *)¶ms;
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while (i--)
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*dst++ = *src++;
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memcpy_P(¶ms, &defaults, sizeof(struct ee_param));
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write_parameters();
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return 1;
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}
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|
9
eeprom.h
9
eeprom.h
@ -22,16 +22,17 @@ struct ee_param {
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};
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#define DEFAULT_PARAMETERS { \
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.spinup_ticks = 1000, \
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.spinup_tick = 25, \
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.spinup_step = 24, \
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.spinup_ticks = 2000, \
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.spinup_tick = 24, \
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.spinup_step = 4, \
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.spinup_wait = 10, \
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.spinup_pwm = 0x0f, \
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.spinup_pwm = 25, \
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.pwm_min = 0x08, \
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.pwm_max = 0xff, \
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.current_limit = 120, \
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.current_max = 0x3ff, \
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.voltage_min = 0x000, \
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.crc16 = 0xDB76, \
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};
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uint8_t read_parameters(void);
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|
51
i2c-slave.c
51
i2c-slave.c
@ -61,20 +61,19 @@ extern struct ee_param params;
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const static uint8_t info[16] = "blmc m8-v1.2 ";
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const static uint8_t info[16] = "blctrl m88-v2.0";
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ISR(TWI_vect)
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{
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static uint8_t cmd;
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static uint8_t bcnt;
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uint8_t data;
|
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uint8_t ack = (1<<TWEA);
|
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|
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switch (TWSR & 0xF8) {
|
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/* SLA + W received, ACK returned -> receive Data and ACK */
|
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case 0x60:
|
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bcnt = 0;
|
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TWCR |= (1<<TWINT) | (1<<TWEA);
|
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TWCR = (1<<TWEN) | (1<<TWIE) | (1<<TWINT) | (1<<TWEA);
|
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break;
|
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|
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/* prev. SLA + W, data received, ACK returned -> receive Data and ACK */
|
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@ -103,9 +102,6 @@ ISR(TWI_vect)
|
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case CMD_SWITCH_APPLICATION:
|
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if (data == BOOTTYPE_BOOTLOADER) {
|
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wdt_enable(WDTO_15MS);
|
||||
|
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} else {
|
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ack = (0<<TWEA);
|
||||
}
|
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break;
|
||||
|
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@ -113,14 +109,10 @@ ISR(TWI_vect)
|
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bcnt++;
|
||||
if (data == MEMTYPE_PARAMETERS) {
|
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cmd = CMD_WRITE_PARAMETERS;
|
||||
|
||||
} else {
|
||||
ack = (0<<TWEA);
|
||||
}
|
||||
break;
|
||||
|
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default:
|
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ack = (0<<TWEA);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
@ -136,21 +128,16 @@ ISR(TWI_vect)
|
||||
((uint8_t *)¶ms)[bcnt++ -4] = data;
|
||||
if (bcnt == sizeof(params)) {
|
||||
write_parameters();
|
||||
ack = (0<<TWEA);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
ack = (0<<TWEA);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
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if (ack == 0x00)
|
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bcnt = 0;
|
||||
|
||||
TWCR |= (1<<TWINT) | ack;
|
||||
TWCR = (1<<TWEN) | (1<<TWIE) | (1<<TWINT) | (1<<TWEA);
|
||||
break;
|
||||
|
||||
/* SLA+R received, ACK returned -> send data */
|
||||
@ -161,16 +148,32 @@ ISR(TWI_vect)
|
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switch (cmd) {
|
||||
case CMD_WAIT:
|
||||
switch (bcnt++) {
|
||||
case 0:
|
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data = blmc.current & 0xFF;
|
||||
case 0: data = blmc.pwm - blmc.pwm_limit;
|
||||
break;
|
||||
|
||||
case 1:
|
||||
data = 0xFF - blmc.pwm_limit;
|
||||
case 1: data = blmc.pwm;
|
||||
break;
|
||||
|
||||
case 2: data = (blmc.rpm & 0xFF);
|
||||
break;
|
||||
|
||||
case 3: data = (blmc.rpm >> 8);
|
||||
break;
|
||||
|
||||
case 4: data = (blmc.current & 0xFF);
|
||||
break;
|
||||
|
||||
case 5: data = (blmc.current >> 8);
|
||||
break;
|
||||
|
||||
case 6: data = (blmc.voltage & 0xFF);
|
||||
break;
|
||||
|
||||
case 7: data = (blmc.voltage >> 8);
|
||||
break;
|
||||
|
||||
default:
|
||||
data = 0xFF;
|
||||
data = 0x00;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
@ -192,19 +195,19 @@ ISR(TWI_vect)
|
||||
}
|
||||
|
||||
TWDR = data;
|
||||
TWCR |= (1<<TWINT) | (1<<TWEA);
|
||||
TWCR = (1<<TWEN) | (1<<TWIE) | (1<<TWINT) | (1<<TWEA);
|
||||
break;
|
||||
|
||||
/* STOP or repeated START */
|
||||
case 0xA0:
|
||||
/* Data transmitted, NACK returned */
|
||||
case 0xC0:
|
||||
TWCR |= (1<<TWINT) | (1<<TWEA);
|
||||
TWCR = (1<<TWEN) | (1<<TWIE) | (1<<TWINT) | (1<<TWEA);
|
||||
break;
|
||||
|
||||
/* failsave -> reset Hardware */
|
||||
default:
|
||||
TWCR |= (1<<TWINT) | (1<<TWSTO) | (1<<TWEA);
|
||||
TWCR = (1<<TWEN) | (1<<TWIE) | (1<<TWINT) | (1<<TWSTO) | (1<<TWEA);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
60
main.c
60
main.c
@ -46,13 +46,13 @@ extern struct blmc_ blmc;
|
||||
|
||||
static uint8_t led[2];
|
||||
|
||||
ISR(TIMER0_OVF_vect)
|
||||
ISR(TIMER1_COMPB_vect)
|
||||
{
|
||||
static uint8_t timer0_cnt = 0;
|
||||
static uint8_t rpm_cnt = 0;
|
||||
static uint8_t adc_chan = SENSE_CURRENT;
|
||||
|
||||
/* Come back in 20ms */
|
||||
TCNT0 = 0xFF - 156;
|
||||
OCR1B = TCNT1 + 20000;
|
||||
|
||||
/* commutations during last 20ms */
|
||||
uint16_t diff = blmc.rpm_tmp - blmc.rpm_tmp_old;
|
||||
@ -64,7 +64,7 @@ ISR(TIMER0_OVF_vect)
|
||||
blmc.flags &= ~(FLAG_RUN_MASK);
|
||||
blmc.flags |= FLAG_PWM_SPINUP | FLAG_COM_SPINUP;
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* no i2c cmd in the last 20ms */
|
||||
if (!(blmc.flags & FLAG_I2C_ACTIVE)) {
|
||||
/* already in i2c timeout, turn off motor */
|
||||
@ -76,7 +76,7 @@ ISR(TIMER0_OVF_vect)
|
||||
} else {
|
||||
blmc.flags &= ~FLAG_I2C_TIMEOUT;
|
||||
}
|
||||
|
||||
#endif
|
||||
blmc.flags &= ~FLAG_I2C_ACTIVE;
|
||||
}
|
||||
|
||||
@ -84,9 +84,9 @@ ISR(TIMER0_OVF_vect)
|
||||
setpwm(blmc.pwm);
|
||||
|
||||
/* calc rpm every second */
|
||||
timer0_cnt++;
|
||||
if (timer0_cnt == 50) {
|
||||
timer0_cnt = 0;
|
||||
rpm_cnt++;
|
||||
if (rpm_cnt == 50) {
|
||||
rpm_cnt = 0;
|
||||
|
||||
blmc.rpm = blmc.rpm_tmp;
|
||||
blmc.rpm_tmp = 0;
|
||||
@ -100,7 +100,6 @@ ISR(TIMER0_OVF_vect)
|
||||
else
|
||||
adc_chan = SENSE_CURRENT;
|
||||
}
|
||||
|
||||
/* led blink timer */
|
||||
static uint8_t led_timer = 0;
|
||||
led_timer = (led_timer +1) & 0x1F;
|
||||
@ -126,29 +125,49 @@ ISR(TIMER0_OVF_vect)
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* For newer devices (mega88) the watchdog timer remains active even after a
|
||||
* system reset. So disable it as soon as possible.
|
||||
* automagically called on startup
|
||||
*/
|
||||
void get_mcusr(void) __attribute__((naked, section(".init3")));
|
||||
void get_mcusr(void)
|
||||
{
|
||||
MCUSR = 0;
|
||||
WDTCSR = (1<<WDCE) | (0<<WDE);
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
DDRB = PHASE_H_MASK | LED_RT | LED_GN;
|
||||
DDRD = PHASE_L_MASK;
|
||||
DDRB = PHASE_A_EN | PHASE_A_PWM | LED_RT | LED_GN;
|
||||
DDRD = PHASE_B_EN | PHASE_B_PWM | PHASE_C_EN | PHASE_C_PWM;
|
||||
|
||||
PORTB = 0x00;
|
||||
PORTD = 0x00;
|
||||
|
||||
/* timer0: running with F_CPU/1024 */
|
||||
TCCR0 = (1<<CS02) | (1<<CS00);
|
||||
/* timer0: running with F_CPU, 8bit Phase Correct PWM (16kHz) */
|
||||
TCCR0A = (1<<WGM00);
|
||||
TCCR0B = (1<<CS00);
|
||||
|
||||
/* timer1: running with F_CPU, 8bit Phase Correct PWM (16kHz) */
|
||||
TCCR1B = (1<<CS10);
|
||||
TCCR1A = (1<<WGM10);
|
||||
/* timer1: running with F_CPU/8 */
|
||||
TCCR1B = (1<<CS11) | (1<<ICNC1);
|
||||
|
||||
/* timer2: running with F_CPU, 8bit Phase Correct PWM (16kHz) */
|
||||
TCCR2 = (1<<WGM20) | (1<<CS20);
|
||||
TCCR2A = (1<<WGM20);
|
||||
TCCR2B = (1<<CS20);
|
||||
|
||||
/* enable Timer0 OVF Interrupt */
|
||||
TIMSK = (1<<TOIE0);
|
||||
/* sync PWM timers */
|
||||
GTCCR = (1<<TSM) | (1<<PSRASY) | (1<<PSRSYNC);
|
||||
TCNT0 = 0x00;
|
||||
TCNT2 = 0x00;
|
||||
GTCCR = (0<<TSM);
|
||||
|
||||
/* enable Timer1 OVF Interrupt */
|
||||
TIMSK1 = (1<<OCIE1B);
|
||||
|
||||
/* Enable Analog Comparator Multiplexer */
|
||||
SFIOR |= (1<<ACME);
|
||||
ADCSRB |= (1<<ACME);
|
||||
ACSR |= (1<<ACIC);
|
||||
|
||||
/* I2C Init: keep Address from bootloader, Auto ACKs with Interrupts */
|
||||
TWCR = (1<<TWEA) | (1<<TWEN) | (1<<TWIE);
|
||||
@ -210,5 +229,6 @@ int main(void)
|
||||
|
||||
sleep_mode();
|
||||
};
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
26
main.h
26
main.h
@ -9,21 +9,23 @@
|
||||
#define LED_RT (1<<PORTB4)
|
||||
#define LED_GN (1<<PORTB5)
|
||||
|
||||
#define PHASE_A_H (1<<PORTB1)
|
||||
#define PHASE_B_H (1<<PORTB2)
|
||||
#define PHASE_C_H (1<<PORTB3)
|
||||
#define PHASE_H_MASK (PHASE_A_H | PHASE_B_H | PHASE_C_H)
|
||||
#define PHASE_A_EN (1<<PORTB2)
|
||||
#define PHASE_A_PWM (1<<PORTB3)
|
||||
#define PHASE_A_OC (1<<COM2A1)
|
||||
|
||||
#define PHASE_A_L (1<<PORTD4)
|
||||
#define PHASE_B_L (1<<PORTD3)
|
||||
#define PHASE_C_L (1<<PORTD2)
|
||||
#define PHASE_L_MASK (PHASE_A_L | PHASE_B_L | PHASE_C_L)
|
||||
#define PHASE_B_EN (1<<PORTD7)
|
||||
#define PHASE_B_PWM (1<<PORTD5)
|
||||
#define PHASE_B_OC (1<<COM0B1)
|
||||
|
||||
#define PHASE_C_EN (1<<PORTD4)
|
||||
#define PHASE_C_PWM (1<<PORTD3)
|
||||
#define PHASE_C_OC (1<<COM2B1)
|
||||
|
||||
#define SENSE_A 0
|
||||
#define SENSE_B 1
|
||||
#define SENSE_C 2
|
||||
#define SENSE_B 2
|
||||
#define SENSE_C 1
|
||||
|
||||
#define SENSE_VOLTAGE 3
|
||||
#define SENSE_CURRENT 6
|
||||
#define SENSE_VOLTAGE 7
|
||||
#define SENSE_CURRENT 3
|
||||
|
||||
#endif
|
||||
|
Loading…
Reference in New Issue
Block a user