fix ADC ref, cleanup, brake added
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efd7ebbe36
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d05f1de3b1
72
blmc.c
72
blmc.c
@ -34,11 +34,15 @@ void trigger_adc(uint8_t channel)
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/* Disable Analog Comperator */
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/* Disable Analog Comperator */
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ACSR &= ~(1<<ACIE);
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ACSR &= ~(1<<ACIE);
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/* set channel (Internal reference, 2.56V) */
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/* set channel (external reference, 5V) */
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ADMUX = (1<<REFS1) | (1<<REFS0) | channel;
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ADMUX = (0<<REFS1) | (0<<REFS0) | channel;
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/* turn on ADC with interrupts, start conversion with 1/32 of F_CPU */
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/*
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ADCSRA = (1<<ADEN) | (1<<ADSC) | (1<<ADIE) | (1<<ADIF)| (1<<ADPS2) | (1<<ADPS0);
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* turn on ADC with interrupts
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* start conversion with 1/16 of F_CPU
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* 1/500kHz * 25 => 50us conversion time
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*/
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ADCSRA = (1<<ADEN) | (1<<ADSC) | (1<<ADIE) | (1<<ADIF)| (1<<ADPS2) | (0<<ADPS0);
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}
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}
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void next_phase(void)
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void next_phase(void)
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@ -53,62 +57,62 @@ void next_phase(void)
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TCNT2 = 0x00;
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TCNT2 = 0x00;
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switch (phase) {
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switch (phase) {
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case 0: /* A: PWM, B: LOW, C: SENSE */
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case 0: /* A: PWM, B: LOW, C: SENSE => disable EN_C, disable PWM_B, enable EN_B */
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PORTB |= PHASE_A_EN;
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PORTD &= ~PHASE_C_EN;
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PORTD = (PORTD & ~PHASE_C_EN) | PHASE_B_EN;
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TCCR0A &= ~PHASE_B_OC;
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TCCR0A &= ~PHASE_B_OC;
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TCCR2A = (TCCR2A & ~PHASE_C_OC) | PHASE_A_OC;
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PORTD |= PHASE_B_EN;
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/* C: falling edge */
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ACSR = (1<<ACIS1);
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ACSR = (1<<ACIS1);
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next_sense = SENSE_C;
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next_sense = SENSE_C;
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break;
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break;
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case 1: /* A: SENSE, B: LOW, C: PWM */
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case 1: /* A: SENSE, B: LOW, C: PWM => disable EN_A, enable PWM_C, enable EN_C */
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PORTB &= ~PHASE_A_EN;
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PORTB &= ~PHASE_A_EN;
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PORTD |= PHASE_B_EN | PHASE_C_EN;
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TCCR2A |= PHASE_C_OC;
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TCCR0A &= ~PHASE_B_OC;
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PORTD |= PHASE_C_EN;
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TCCR2A = (TCCR2A & ~PHASE_A_OC) | PHASE_C_OC;
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/* A: rising edge */
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ACSR = (1<<ACIS1) | (1<<ACIS0);
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ACSR = (1<<ACIS1) | (1<<ACIS0);
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next_sense = SENSE_A;
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next_sense = SENSE_A;
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break;
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break;
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case 2: /* A: LOW, B: SENSE, C: PWM */
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case 2: /* A: LOW, B: SENSE, C: PWM => disable EN_B, disable PWM_A, enable EN_A */
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PORTD &= ~PHASE_B_EN;
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TCCR2A &= ~PHASE_A_OC;
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PORTB |= PHASE_A_EN;
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PORTB |= PHASE_A_EN;
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PORTD = (PORTD & ~PHASE_B_EN) | PHASE_C_EN;
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TCCR0A &= ~PHASE_B_OC;
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TCCR2A = (TCCR2A & ~PHASE_A_OC) | PHASE_C_OC;
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/* B: falling edge */
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ACSR = (1<<ACIS1);
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ACSR = (1<<ACIS1);
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next_sense = SENSE_B;
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next_sense = SENSE_B;
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break;
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break;
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case 3: /* A: LOW, B: PWM, C: SENSE */
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case 3: /* A: LOW, B: PWM, C: SENSE => disable EN_C, enable PWM_B, enable EN_B */
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PORTB |= PHASE_A_EN;
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PORTD &= ~PHASE_C_EN;
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PORTD = (PORTD & ~PHASE_C_EN) | PHASE_B_EN;
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TCCR0A |= PHASE_B_OC;
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TCCR0A |= PHASE_B_OC;
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TCCR2A &= ~(PHASE_A_OC | PHASE_C_OC);
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PORTD |= PHASE_B_EN;
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/* C: rising edge */
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ACSR = (1<<ACIS1) | (1<<ACIS0);
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ACSR = (1<<ACIS1) | (1<<ACIS0);
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next_sense = SENSE_C;
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next_sense = SENSE_C;
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break;
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break;
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case 4: /* A: SENSE, B: PWM, C: LOW */
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case 4: /* A: SENSE, B: PWM, C: LOW => disable EN_A, disable PWM_C, enable EN_C */
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PORTB &= ~PHASE_A_EN;
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PORTB &= ~PHASE_A_EN;
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PORTD = (PORTD & ~PHASE_B_EN) | PHASE_C_EN;
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TCCR2A &= ~PHASE_C_OC;
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TCCR0A |= PHASE_B_OC;
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PORTD |= PHASE_C_EN;
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TCCR2A &= ~(PHASE_A_OC | PHASE_C_OC);
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/* A: falling edge */
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ACSR = (1<<ACIS1);
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ACSR = (1<<ACIS1);
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next_sense = SENSE_A;
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next_sense = SENSE_A;
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break;
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break;
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case 5: /* A: PWM, B: SENSE, C: LOW */
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case 5: /* A: PWM, B: SENSE, C: LOW => disable EN_B, enable PWM_A, enable EN_A */
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PORTD &= ~PHASE_B_EN;
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TCCR2A |= PHASE_A_OC;
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PORTB |= PHASE_A_EN;
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PORTB |= PHASE_A_EN;
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PORTD = (PORTD & ~PHASE_B_EN) | PHASE_C_EN;
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TCCR0A &= ~PHASE_B_OC;
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TCCR2A = (TCCR2A & ~PHASE_C_OC) | PHASE_A_OC;
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/* B: rising edge */
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ACSR = (1<<ACIS1) | (1<<ACIS0);
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ACSR = (1<<ACIS1) | (1<<ACIS0);
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next_sense = SENSE_B;
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next_sense = SENSE_B;
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break;
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break;
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@ -228,6 +232,18 @@ void setpwm(uint8_t pwm)
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OCR0B = pwm;
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OCR0B = pwm;
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OCR2A = pwm;
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OCR2A = pwm;
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OCR2B = pwm;
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OCR2B = pwm;
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/* disable all drivers */
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if (pwm == 0) {
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PORTB &= ~PHASE_A_EN;
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PORTD &= ~(PHASE_B_EN | PHASE_C_EN);
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TCCR0A &= ~PHASE_B_OC;
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TCCR2A &= ~(PHASE_A_OC | PHASE_C_OC);
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PORTB |= PHASE_A_EN;
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PORTD |= (PHASE_B_EN | PHASE_C_EN);
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}
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}
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}
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ISR(ANALOG_COMP_vect)
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ISR(ANALOG_COMP_vect)
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