AVR based brushless motor controller
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/***************************************************************************
* Copyright (C) 09/2007 by Olaf Rempel *
* razzor@kopf-tisch.de *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; version 2 of the License, *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/wdt.h>
#include "main.h"
#include "blmc.h"
#include "eeprom.h"
extern struct blmc_ blmc;
extern struct ee_param params;
/* SLA+R */
#define CMD_WAIT 0x00
#define CMD_READ_VERSION 0x01
#define CMD_READ_MEMORY 0x02
/* internal mappings */
#define CMD_READ_CHIPINFO (0x10 | CMD_READ_MEMORY)
#define CMD_READ_FLASH (0x20 | CMD_READ_MEMORY)
#define CMD_READ_EEPROM (0x30 | CMD_READ_MEMORY)
#define CMD_READ_PARAMETERS (0x40 | CMD_READ_MEMORY) /* only in APP */
/* SLA+W */
#define CMD_SWITCH_APPLICATION CMD_READ_VERSION
#define CMD_WRITE_MEMORY CMD_READ_MEMORY
/* internal mappings */
#define CMD_BOOT_BOOTLOADER (0x10 | CMD_SWITCH_APPLICATION) /* only in APP */
#define CMD_BOOT_APPLICATION (0x20 | CMD_SWITCH_APPLICATION)
#define CMD_WRITE_CHIPINFO (0x10 | CMD_WRITE_MEMORY) /* invalid */
#define CMD_WRITE_FLASH (0x20 | CMD_WRITE_MEMORY)
#define CMD_WRITE_EEPROM (0x30 | CMD_WRITE_MEMORY)
#define CMD_WRITE_PARAMETERS (0x40 | CMD_WRITE_MEMORY) /* only in APP */
/* CMD_SWITCH_APPLICATION parameter */
#define BOOTTYPE_BOOTLOADER 0x00 /* only in APP */
#define BOOTTYPE_APPLICATION 0x80
/* CMD_{READ|WRITE}_* parameter */
#define MEMTYPE_CHIPINFO 0x00
#define MEMTYPE_FLASH 0x01
#define MEMTYPE_EEPROM 0x02
#define MEMTYPE_PARAMETERS 0x03 /* only in APP */
const static uint8_t info[16] = "blmc m8-v1.2 ";
ISR(TWI_vect)
{
static uint8_t cmd;
static uint8_t bcnt;
uint8_t data;
uint8_t ack = (1<<TWEA);
switch (TWSR & 0xF8) {
/* SLA + W received, ACK returned -> receive Data and ACK */
case 0x60:
bcnt = 0;
TWCR |= (1<<TWINT) | (1<<TWEA);
break;
/* prev. SLA + W, data received, ACK returned -> receive Data and ACK */
case 0x80:
data = TWDR;
switch (bcnt) {
case 0:
switch (data) {
case CMD_SWITCH_APPLICATION:
case CMD_WRITE_MEMORY:
cmd = data;
bcnt++;
break;
default:
blmc.flags |= FLAG_I2C_ACTIVE;
setpwm(data);
cmd = CMD_WAIT;
bcnt = 0;
break;
}
break;
case 1:
switch (cmd) {
case CMD_SWITCH_APPLICATION:
if (data == BOOTTYPE_BOOTLOADER) {
wdt_enable(WDTO_15MS);
} else {
ack = (0<<TWEA);
}
break;
case CMD_WRITE_MEMORY:
bcnt++;
if (data == MEMTYPE_PARAMETERS) {
cmd = CMD_WRITE_PARAMETERS;
} else {
ack = (0<<TWEA);
}
break;
default:
ack = (0<<TWEA);
break;
}
break;
case 2: /* ignore address bytes */
case 3:
bcnt++;
break;
default:
switch (cmd) {
case CMD_WRITE_PARAMETERS:
((uint8_t *)&params)[bcnt++ -4] = data;
if (bcnt == sizeof(params)) {
write_parameters();
ack = (0<<TWEA);
}
break;
default:
ack = (0<<TWEA);
break;
}
break;
}
if (ack == 0x00)
bcnt = 0;
TWCR |= (1<<TWINT) | ack;
break;
/* SLA+R received, ACK returned -> send data */
case 0xA8:
bcnt = 0;
/* prev. SLA+R, data sent, ACK returned -> send data */
case 0xB8:
switch (cmd) {
case CMD_WAIT:
switch (bcnt++) {
case 0:
data = blmc.current & 0xFF;
break;
case 1:
data = 0xFF - blmc.pwm_limit;
break;
default:
data = 0xFF;
break;
}
break;
case CMD_READ_VERSION:
data = info[bcnt++];
bcnt %= sizeof(info);
break;
case CMD_READ_PARAMETERS:
data = ((uint8_t *)&params)[bcnt++];
if (bcnt > sizeof(params))
bcnt = 0;
break;
default:
data = 0xFF;
break;
}
TWDR = data;
TWCR |= (1<<TWINT) | (1<<TWEA);
break;
/* STOP or repeated START */
case 0xA0:
/* Data transmitted, NACK returned */
case 0xC0:
TWCR |= (1<<TWINT) | (1<<TWEA);
break;
/* failsave -> reset Hardware */
default:
TWCR |= (1<<TWINT) | (1<<TWSTO) | (1<<TWEA);
break;
}
}