369 lines
9.9 KiB
C
369 lines
9.9 KiB
C
/***************************************************************************
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* Copyright (C) 04/2013 by Olaf Rempel *
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* razzor@kopf-tisch.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; version 2 of the License, *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#include <avr/io.h>
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#include <avr/interrupt.h>
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#define F_CPU 11059200
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#include <util/delay.h>
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/*
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* attiny2313
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* lfuse: 0xff (ext. crystal, slow rising power, max startup time)
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* hfuse: 0xdb (2.7V BOD)
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* efuse: 0xff (self Prog enabled)
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*
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* PB0 -> NC
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* PB1 -> reset-out
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* PB2 -> /WR SRAM
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* PB3 -> SRCK (shift register clock)
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* PB4 -> SER (shift register input)
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* PB5 -> CCK (counter clock)
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* PB6 -> RCK (counter and shift register store clock)
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* PB7 -> /OE (output enable counter, shift register, reset-out, A16)
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* PD0 <- RXD
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* PD1 -> TXD
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* PD2 <- /PowerFail
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* PD3 -> A16
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* PD4 -> /LED_GN
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* PD5 -> /LED_RT
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* PD6 -> /OE (output enable RAM and address buffer, counter clear)
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*/
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#define RESET_OUT PORTB1
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#define nRAM_WR PORTB2
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#define SREG_CLK PORTB3
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#define SREG_DAT PORTB4
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#define CNT_CLK PORTB5
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#define REG_STORE PORTB6
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#define nEMU_EN PORTB7
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#define RXD PORTD0
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#define TXD PORTD1
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#define nPOWERFAIL PORTD2
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#define EMU_A16 PORTD3
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#define nLED_GN PORTD4
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#define nLED_RT PORTD5
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#define nTARGET_EN PORTD6
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#define BAUDRATE 115200
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#define UART_CALC_BAUDRATE(baudRate) (((uint32_t)F_CPU) / (((uint32_t)baudRate)*16) -1)
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struct _globdata {
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uint8_t address_mask;
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uint8_t reset_polarity;
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};
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static struct _globdata gdata = { 0 };
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/* *************************************************************************
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* send one byte to UART
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* ************************************************************************* */
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static void ser_send(uint8_t data)
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{
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loop_until_bit_is_set(UCSRA, UDRIE);
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UDR = data;
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} /* ser_send */
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/* *************************************************************************
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* receive one byte from UART
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* ************************************************************************* */
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static uint8_t ser_recv(void)
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{
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loop_until_bit_is_set(UCSRA, RXC);
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return UDR;
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} /* ser_recv */
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/* *************************************************************************
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* shift one byte out to register (LSB first)
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* ************************************************************************* */
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static void shift_data(uint8_t data)
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{
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uint8_t mask;
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for (mask = 0x01; mask != 0; mask <<= 1) {
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if (data & mask) {
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PORTB |= (1<<SREG_DAT);
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} else {
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PORTB &= ~(1<<SREG_DAT);
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}
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/* positive edge clocks in data */
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PORTB |= (1<<SREG_CLK);
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PORTB &= ~(1<<SREG_CLK);
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}
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} /* shift_data */
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/* *************************************************************************
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* store pulse for register and counter
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* ************************************************************************* */
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static void store_pulse(void)
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{
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/* positive edge transfers data to output buffer */
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PORTB |= (1<<REG_STORE);
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PORTB &= ~(1<<REG_STORE);
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} /* store_pulse */
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/* *************************************************************************
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* write pulse for SRAM and increment counter
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* ************************************************************************* */
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static void write_inc_pulse(void)
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{
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/* positive edge clocks in data */
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PORTB &= ~(1<<nRAM_WR);
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PORTB |= (1<<nRAM_WR);
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/* positive edge increments counter */
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PORTB |= (1<<CNT_CLK);
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PORTB &= ~(1<<CNT_CLK);
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} /* write_inc_pulse */
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/* *************************************************************************
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* switch access to RAM between emulator and target
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* ************************************************************************* */
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static void do_reset(uint8_t enable)
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{
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if (enable) {
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/* switch RAM access to EMU */
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PORTD |= (1<<nTARGET_EN);
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PORTD &= ~(1<<nLED_RT);
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PORTB &= ~(1<<nEMU_EN);
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} else {
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/* set eprom address line mask */
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shift_data(gdata.address_mask);
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shift_data(0x00);
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store_pulse();
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/* switch RAM access to TARGET */
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PORTB |= (1<<nEMU_EN);
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PORTD &= ~(1<<nTARGET_EN);
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PORTD |= (1<<nLED_RT);
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}
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/* set RESET_OUT */
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if (enable ^ gdata.reset_polarity) {
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PORTB &= ~(1<<RESET_OUT);
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} else {
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PORTB |= (1<<RESET_OUT);
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}
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} /* do_reset */
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/* *************************************************************************
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* configures number of addresslines and loads data from UART into RAM
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* ************************************************************************* */
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static void do_load(uint8_t type, uint32_t length)
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{
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uint32_t size;
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switch (type) {
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case 0x02: /* 2716 - 2kB */
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size = 0x0800;
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gdata.address_mask = 0x00;
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break;
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case 0x04: /* 2732 - 4kB */
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size = 0x1000;
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gdata.address_mask = 0x80;
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break;
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case 0x08: /* 2764 - 8kB */
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size = 0x2000;
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gdata.address_mask = 0xC0;
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break;
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case 0x10: /* 27128 - 16kB */
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size = 0x4000;
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gdata.address_mask = 0xE0;
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break;
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case 0x20: /* 27256 - 32kB */
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size = 0x8000;
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gdata.address_mask = 0xF0;
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break;
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case 0x40: /* 27512 - 64kB */
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size = 0x10000;
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gdata.address_mask = 0xF8;
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break;
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default:
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case 0x80: /* 27010 - 128kB */
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size = 0x20000;
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gdata.address_mask = 0xFC;
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break;
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}
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do_reset(1);
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uint32_t i;
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uint8_t data;
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for (i = 0; i < size; i++) {
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if (i > 0xFFFF) {
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PORTD |= (1<<EMU_A16);
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} else {
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PORTD &= ~(1<<EMU_A16);
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}
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data = (i < length) ? ser_recv() : 0xFF;
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shift_data(data);
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store_pulse();
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write_inc_pulse();
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}
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do_reset(0);
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} /* do_load */
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/* *************************************************************************
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* clears whole RAM (writes 0xFF)
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* ************************************************************************* */
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static void do_clear(void)
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{
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do_reset(1);
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shift_data(0xFF);
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uint16_t i = 0xFFFF;
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PORTD &= ~(1<<EMU_A16);
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do {
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store_pulse();
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write_inc_pulse();
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} while (i--);
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PORTD |= (1<<EMU_A16);
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do {
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store_pulse();
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write_inc_pulse();
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} while (i--);
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do_reset(0);
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} /* do_clear */
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#if 0
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/* Powerfail / Wakeup */
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ISR(INT0_vect)
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{
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if (1) {
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/*
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* Power Fail:
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* - enable RESET_OUT
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* - disable nTARGET_EN
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* - enable rising edge INT0 (nPOWERFAIL)
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* - disable pullups
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* - put MCU in standby
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*/
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do_reset(1);
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/* disable green LED */
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PORTD |= (1<<nLED_GN);
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} else {
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/*
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* Power Restore:
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* - enable pullups
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* - enable falling edge INT0 (nPOWERFAIL)
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* - enable nTARGET_EN again
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* - disable RESET_OUT
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*/
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/* enable green LED */
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PORTD &= ~(1<<nLED_GN);
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do_reset(0);
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}
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}
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#endif
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int main(void) __attribute__ ((noreturn));
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int main(void)
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{
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DDRB = 0xFF;
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PORTB = (1<<nRAM_WR) | (1<<nEMU_EN);
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DDRD = ~((1<<RXD) | (1<<nPOWERFAIL));
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PORTD = (1<<RXD) | (1<<nPOWERFAIL) | (1<<nLED_GN) | (1<<nLED_RT) | (1<<nTARGET_EN);
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/* enable UART 115200,8n1 */
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UBRRH = (UART_CALC_BAUDRATE(BAUDRATE)>>8) & 0xFF;
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UBRRL = (UART_CALC_BAUDRATE(BAUDRATE) & 0xFF);
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UCSRC = (1<<UCSZ1) | (1<<UCSZ0);
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UCSRB = (1<<RXEN) | (1<<TXEN);
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#if 0
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/* powerfail: detect falling edge on INT0 */
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MCUCR = (1<<ISC01);
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GIMSK = (1<<INT0);
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sei();
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#endif
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/* enable LED and reset Counter */
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PORTD &= ~((1<<nLED_GN) | (1<<nTARGET_EN));
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/* init RAM */
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gdata.address_mask = 0x3F;
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do_clear();
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while (1) {
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uint8_t cmd = ser_recv();
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switch (cmd) {
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case 'p': /* low active reset */
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gdata.reset_polarity = 0;
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ser_send('\n');
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break;
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case 'P': /* high active reset */
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gdata.reset_polarity = 1;
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ser_send('\n');
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break;
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case 'r': /* reset pulse */
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do_reset(1);
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_delay_ms(10);
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do_reset(0);
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ser_send('\n');
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break;
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case 'l': /* load eprom content */
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{
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uint8_t type = ser_recv();
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uint32_t length = (uint32_t)ser_recv() << 16;
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length |= ser_recv() << 8;
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length |= ser_recv();
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do_load(type, length);
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}
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break;
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default:
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ser_send('?');
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break;
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}
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}
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}
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