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/**** RFM 12 library for Atmel AVR Microcontrollers *******
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*
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* This software is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published
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* by the Free Software Foundation; either version 2 of the License,
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* or (at your option) any later version.
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*
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* This software is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this software; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA.
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*
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* @author Peter Fuhrmann, Hans-Gert Dahmen, Soeren Heisrath
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*/
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/* Configuration setting command
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Bit el enables the internal data register.
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Bit ef enables the FIFO mode. If ef=0 then DATA (pin 6) and DCLK (pin 7) are used for data and data clock output.
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x3 x2 x1 x0 Crystal Load Capacitance [pF]
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0 0 0 0 8.5
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0 0 0 1 9.0
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0 0 1 0 9.5
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0 0 1 1 10.0
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....
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1 1 1 0 15.5
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1 1 1 1 16.0
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*/
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# define RFM12_CMD_CFG 0x8000
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# define RFM12_CFG_EL 0x80
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# define RFM12_CFG_EF 0x40
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# define RFM12_CFG_BAND_MASK 0x30
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# define RFM12_BAND_315 0x00
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# define RFM12_BAND_433 0x10
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# define RFM12_BAND_868 0x20
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# define RFM12_BAND_915 0x30
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# define RFM12_CFG_XTAL_MASK 0x0F
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# define RFM12_XTAL_8_5PF 0x00
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# define RFM12_XTAL_9_0PF 0x01
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# define RFM12_XTAL_9_5PF 0x02
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# define RFM12_XTAL_10_0PF 0x03
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# define RFM12_XTAL_10_5PF 0x04
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# define RFM12_XTAL_11_0PF 0x05
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# define RFM12_XTAL_11_5PF 0x06
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# define RFM12_XTAL_12_0PF 0x07
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# define RFM12_XTAL_12_5PF 0x08
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# define RFM12_XTAL_13_0PF 0x09
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# define RFM12_XTAL_13_5PF 0x0A
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# define RFM12_XTAL_14_0PF 0x0B
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# define RFM12_XTAL_14_5PF 0x0C
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# define RFM12_XTAL_15_0PF 0x0D
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# define RFM12_XTAL_15_5PF 0x0E
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# define RFM12_XTAL_16_0PF 0x0F
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/*
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2. Power Management Command
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Bit Function of the control bit Related blocks
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er Enables the whole receiver chain RF front end, baseband, synthesizer, oscillator
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ebb The receiver baseband circuit can be separately switched on Baseband
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et Switches on the PLL, the power amplifier, and starts the
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transmission (If TX register is enabled) Power amplifier, synthesizer, oscillator
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es Turns on the synthesizer Synthesizer
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ex Turns on the crystal oscillator Crystal oscillator
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eb Enables the low battery detector Low battery detector
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ew Enables the wake-up timer Wake-up timer
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dc Disables the clock output (pin 8) Clock output buffer
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*/
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#define RFM12_CMD_PWRMGT 0x8200
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#define RFM12_PWRMGT_ER 0x80
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#define RFM12_PWRMGT_EBB 0x40
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#define RFM12_PWRMGT_ET 0x20
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#define RFM12_PWRMGT_ES 0x10
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#define RFM12_PWRMGT_EX 0x08
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#define RFM12_PWRMGT_EB 0x04
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#define RFM12_PWRMGT_EW 0x02
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#define RFM12_PWRMGT_DC 0x01
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/*
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3. Frequency Setting Command
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
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1 0 1 0 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 A680h
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The 12-bit parameter F (bits f11 to f0) should be in the range
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of 96 and 3903. When F value sent is out of range, the
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previous value is kept. The synthesizer center frequency f0 can
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be calculated as:
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f0 = 10 * C1 * (C2 + F/4000) [MHz]
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The constants C1 and C2 are determined by
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the selected band as:
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Band [MHz] C1 C2
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433 1 43
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868 2 43
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915 3 30
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Frequency in 433 Band can be from 430.24MHz to 439.7575MHz in 2.5kHz increments.
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*/
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#define RFM12_CMD_FREQUENCY 0xA000
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#define RFM12_FREQUENCY_MASK 0x0FFF
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#define RFM12_FREQUENCY_CALC_433(f) (((f)-430000000UL)/2500UL)
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#define RFM12_FREQUENCY_CALC_868(f) (((f)-860000000UL)/5000UL)
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#define RFM12_FREQUENCY_CALC_915(f) (((f)-900000000UL)/7500UL)
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/*
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4. Data Rate Command
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
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1 1 0 0 0 1 1 0 cs r6 r5 r4 r3 r2 r1 r0 C623h
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The actual bit rate in transmit mode and the expected bit rate of the received data stream in receive mode is determined by the 7-bit
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parameter R (bits r6 to r0) and bit cs.
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BR = 10000 / 29 / (R+1) / (1+cs*7) [kbps]
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In the receiver set R according to the next function:
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R = (10000 / 29 / (1+cs*7) / BR) – 1, where BR is the expected bit rate in kbps.
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Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with small error.
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Data rate accuracy requirements:
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Clock recovery in slow mode: ΔBR/BR < 1/(29*Nbit) Clock recovery in fast mode: ΔBR/BR < 3/(29*Nbit)
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BR is the bit rate set in the receiver and ΔBR is the bit rate difference between the transmitter and the receiver. Nbit is the maximum
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number of consecutive ones or zeros in the data stream. It is recommended for long data packets to include enough 1/0 and 0/1
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transitions, and to be careful to use the same division ratio in the receiver and in the transmitter.
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*/
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#define RFM12_CMD_DATARATE 0xC600
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#define RFM12_DATARATE_CS 0x80
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//calculate setting for datarates >= 2700 Baud
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#define RFM12_DATARATE_CALC_HIGH(d) ((uint8_t)((10000000.0/29.0/d)-0.5))
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//calculate setting for datarates < 2700 Baud
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#define RFM12_DATARATE_CALC_LOW(d) (RFM12_DATARATE_CS|(uint8_t)((10000000.0/29.0/8.0/d)-0.5))
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#define RFM12_DATARATE_MASK 0x00ff
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/*
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5. Receiver Control Command
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
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1 0 0 1 0 p16 d1 d0 i2 i1 i0 g1 g0 r2 r1 r0 9080h
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Bit 10 (p16): pin16 function select
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p16 Function of pin 16
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0 Interrupt input
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1 VDI output
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Bits 9-8 (d1 to d0): VDI (valid data indicator) signal response time setting:
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d1 d0 Response
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0 0 Fast
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0 1 Medium
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1 0 Slow
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1 1 Always on
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Bits 7-5 (i2 to i0): Receiver baseband bandwidth (BW) select:
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i2 i1 i0 BW [kHz]
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0 0 0 reserved
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0 0 1 400
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0 1 0 340
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0 1 1 270
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1 0 0 200
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1 0 1 134
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1 1 0 67
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1 1 1 reserved
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Bits 4-3 (g1 to g0): LNA gain select:
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g1 g0 relative to maximum [dB]
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0 0 0
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0 1 -6
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1 0 -14
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1 1 -20
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Bits 2-0 (r2 to r0): RSSI detector threshold:
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r2 r1 r0 RSSIsetth [dBm]
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0 0 0 -103
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0 0 1 -97
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0 1 0 -91
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0 1 1 -85
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1 0 0 -79
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1 0 1 -73
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1 1 0 Reserved
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1 1 1 Reserved
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The RSSI threshold depends on the LNA gain, the real RSSI threshold can be calculated:
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RSSIth=RSSIsetth+GLNA
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*/
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#define RFM12_CMD_RXCTRL 0x9000
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#define RFM12_RXCTRL_P16_VDI 0x400
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#define RFM12_RXCTRL_VDI_FAST 0x000
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#define RFM12_RXCTRL_VDI_MEDIUM 0x100
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#define RFM12_RXCTRL_VDI_SLOW 0x200
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#define RFM12_RXCTRL_VDI_ALWAYS_ON 0x300
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#define RFM12_RXCTRL_BW_MASK 0xE0
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#define RFM12_RXCTRL_BW_400 0x20
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#define RFM12_RXCTRL_BW_340 0x40
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#define RFM12_RXCTRL_BW_270 0x60
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#define RFM12_RXCTRL_BW_200 0x80
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#define RFM12_RXCTRL_BW_134 0xA0
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#define RFM12_RXCTRL_BW_67 0xC0
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#define RFM12_RXCTRL_LNA_MASK 0x18
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#define RFM12_RXCTRL_LNA_0 0x00
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#define RFM12_RXCTRL_LNA_6 0x08
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#define RFM12_RXCTRL_LNA_14 0x10
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#define RFM12_RXCTRL_LNA_20 0x18
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#define RFM12_RXCTRL_RSSI_103 0x00
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#define RFM12_RXCTRL_RSSI_97 0x01
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#define RFM12_RXCTRL_RSSI_91 0x02
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#define RFM12_RXCTRL_RSSI_85 0x03
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#define RFM12_RXCTRL_RSSI_79 0x04
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#define RFM12_RXCTRL_RSSI_73 0x05
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#define RFM12_RXCTRL_RSSI_67 0x06
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#define RFM12_RXCTRL_RSSI_61 0x07
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#define RFM12_RXCTRL_RSSI_MASK 0x07
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/*
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6. Data Filter Command
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
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1 1 0 0 0 0 1 0 al ml 1 s 1 f2 f1 f0 C22Ch
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Bit 7 (al): Clock recovery (CR) auto lock control, if set.
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CR will start in fast mode, then after locking it will automatically switch to slow mode.
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Bit 6 (ml): Clock recovery lock control
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1: fast mode, fast attack and fast release (4 to 8 bit preamble (1010...) is recommended)
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0: slow mode, slow attack and slow release (12 to 16 bit preamble is recommended)
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Using the slow mode requires more accurate bit timing (see Data Rate Command).
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Bits 4 (s): Select the type of the data filter:
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s Filter Type
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0 Digital filter
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1 Analog RC filter
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Digital: This is a digital realization of an analog RC filter followed by a comparator with hysteresis. The time constant is
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automatically adjusted to the bit rate defined by the Data Rate Command.
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Note: Bit rate can not exceed 115 kpbs in this mode.
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Analog RC filter: The demodulator output is fed to pin 7 over a 10 kOhm resistor. The filter cut-off frequency is set by the
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external capacitor connected to this pin and VSS.
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Bits 2-0 (f2 to f0): DQD threshold parameter.
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Note: To let the DQD report "good signal quality" the threshold parameter should be 4 in cases where the bitrate is close to the
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deviation. At higher deviation/bitrate settings, a higher threshold parameter can report "good signal quality" as well.
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*/
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#define RFM12_CMD_DATAFILTER 0xC228
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#define RFM12_DATAFILTER_AL 0x80
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#define RFM12_DATAFILTER_ML 0x40
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#define RFM12_DATAFILTER_S 0x10
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/*
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7. FIFO and Reset Mode Command
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
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1 1 0 0 1 0 1 0 f3 f2 f1 f0 sp al ff dr CA80h
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Bits 7-4 (f3 to f0): FIFO IT level. The FIFO generates IT when the number of received data bits reaches this level.
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Bit 3 (sp): Select the length of the synchron pattern:
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sp Byte1 Byte0 (POR) Synchron Pattern (Byte1+Byte0)
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0 2Dh D4h 2DD4h
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1 Not used D4h D4h
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Note: Byte0 can be programmed by the Synchron Pattern Command.
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Bit 2 (al): Set the input of the FIFO fill start condition:
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al
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0 Synchron pattern
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1 Always fill
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Bit 1 (ff): FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared.
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Bit 0 (dr): Disables the highly sensitive RESET mode.
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*/
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#define RFM12_CMD_FIFORESET 0xCA00
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#define RFM12_FIFORESET_SP 0x08
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#define RFM12_FIFORESET_AL 0x04
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#define RFM12_FIFORESET_FF 0x02
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#define RFM12_FIFORESET_DR 0x01
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/*
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8. Synchron Pattern Command
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
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1 1 0 0 1 1 1 0 b7 b6 b5 b4 b3 b2 b1 b0 CED4h
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The Byte0 used for synchron pattern detection can be reprogrammed by B <b7:b0>.
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*/
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#define RFM12_CMD_SYNCPATTERN 0xCE00
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/*
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9. Receiver FIFO Read Command
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
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1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 B000h
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With this command, the controller can read 8 bits from the receiver FIFO. Bit 6 (ef) must be set in Configuration Setting Command.
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Note:: During FIFO access fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency. When the duty-cycle of the
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clock signal is not 50 % the shorter period of the clock pulse width should be at least 2/fref .
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*/
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#define RFM12_CMD_READ 0xB000
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/*
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10. AFC Command
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
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1 1 0 0 0 1 0 0 a1 a0 rl1 rl0 st fi oe en C4F7h
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Bit 7-6 (a1 to a0): Automatic operation mode selector:
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a1 a0
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0 0 Auto mode off (Strobe is controlled by microcontroller)
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0 1 Runs only once after each power-up
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1 0 Keep the foffset only during receiving (VDI=high)
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1 1 Keep the foffset value independently from the state of the VDI signal
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Bit 5-4 (rl1 to rl0): Range limit. Limits the value of the frequency offset register to the next values:
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rl1 rl0 Max deviation
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0 0 No restriction (+63 fres to -64 fres)
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0 1 +15 fres to -16 fres
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1 0 +7 fres to -8 fres
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1 1 +3 fres to -4 fres
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fres:
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433 MHz bands: 2.5 kHz
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868 MHz band: 5 kHz
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915 MHz band: 7.5 kHz
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Bit 3 (st): Strobe edge, when st goes to high, the actual latest calculated frequency error is stored into the offset register of the AFC
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block.
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Bit 2 (fi): Switches the circuit to high accuracy (fine) mode. In this case, the processing time is about twice as long, but the measurement
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uncertainty is about half.
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Bit 1 (oe): Enables the frequency offset register. It allows the addition of the offset register to the frequency control word of the PLL.
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Bit 0 (en): Enables the calculation of the offset frequency by the AFC circuit.
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In automatic operation mode (no strobe signal is needed from the microcontroller to update the output offset register) the AFC circuit
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is automatically enabled when the VDI indicates potential incoming signal during the whole measurement cycle and the circuit
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measures the same result in two subsequent cycles.
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There are three operation modes, examples from the possible application:
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1, (a1=0, a0=1) The circuit measures the frequency offset only once after power up. This way, extended TX-RX maximum distance
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can be achieved.
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Possible application:
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In the final application, when the user inserts the battery, the circuit measures and compensates for the frequency offset caused by
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the crystal tolerances. This method allows for the use of a cheaper quartz in the application and provides protection against tracking
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an interferer.
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2a, (a1=1, a0=0) The circuit automatically measures the frequency offset during an initial effective low data rate pattern –easier to
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receive- (i.e.: 00110011) of the package and changes the receiving frequency accordingly. The further part of the package can be
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received by the corrected frequency settings.
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2b, (a1=1, a0=0) The transmitter must transmit the first part of the packet with a step higher deviation and later there is a possibility
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of reducing it.
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In both cases (2a and 2b), when the VDI indicates poor receiving conditions (VDI goes low), the output register is automatically
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cleared. Use these settings when receiving signals from different transmitters transmitting in the same nominal frequencies.
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3, (a1=1, a0=1) It’s the same as 2a and 2b modes, but suggested to use when a receiver operates with only one transmitter. After a
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complete measuring cycle, the measured value is kept independently of the state of the VDI signal.
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*/
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#define RFM12_CMD_AFC 0xC400
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#define RFM12_AFC_AUTO_OFF 0x00
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#define RFM12_AFC_AUTO_ONCE 0x40
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#define RFM12_AFC_AUTO_VDI 0x80
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#define RFM12_AFC_AUTO_KEEP 0xC0
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#define RFM12_AFC_LIMIT_OFF 0x00 /* 64 */
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#define RFM12_AFC_LIMIT_16 0x10
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#define RFM12_AFC_LIMIT_8 0x20
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#define RFM12_AFC_LIMIT_4 0x30
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#define RFM12_AFC_ST 0x08
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#define RFM12_AFC_FI 0x04
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#define RFM12_AFC_OE 0x02
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#define RFM12_AFC_EN 0x01
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/*
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11. TX Configuration Control Command
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
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1 0 0 1 1 0 0 mp m3 m2 m1 m0 0 p2 p1 p0 9800h
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Bits 8-4 (mp, m3 to m0): FSK modulation parameters:
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The resulting output frequency can be calculated as:
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fout = f0 + (-1)SIGN * (M + 1) * (15 kHz)
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where:
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f0 is the channel center frequency (see the
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Frequency Setting Command)
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M is the four bit binary number <m3 : m0>
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SIGN = (mp) XOR FSK
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Bits 2-0 (p2 to p0): Output power:
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p2 p1 p0 Relative Output Power [dB]
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0 0 0 0
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0 0 1 -2.5
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0 1 0 -5
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0 1 1 -7.5
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1 0 0 -10
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1 0 1 -12.5
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1 1 0 -15
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1 1 1 -17.5
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*/
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#define RFM12_CMD_TXCONF 0x9800
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#define RFM12_TXCONF_MP 0x100
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#define RFM12_TXCONF_POWER_0 0x00
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#define RFM12_TXCONF_POWER_3 0x01
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#define RFM12_TXCONF_POWER_6 0x02
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#define RFM12_TXCONF_POWER_9 0x03
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#define RFM12_TXCONF_POWER_12 0x04
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#define RFM12_TXCONF_POWER_15 0x05
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#define RFM12_TXCONF_POWER_18 0x06
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#define RFM12_TXCONF_POWER_21 0x07
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#define RFM12_TXCONF_FSK_MASK 0xf0
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#define RFM12_TXCONF_FS_CALC(f) (((f/15000UL)-1)<<4)
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#define RFM12_TXCONF_MASK 0x01F7
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#define RFM12_TXCONF_POWER_MASK 0x07
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/*
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12. PLL Setting Command
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
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1 1 0 0 1 1 0 0 0 ob1 ob0 0 ddy ddit 1 bw0 CC67h
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Note: POR default setting of the register carefully selected to cover almost all typical applications.
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Bit 6-5 (ob1-ob0): Microcontroller output clock buffer rise and fall time control.
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ob1 ob0 Selected uC CLK frequency
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0 0 5 or 10 MHz (recommended)
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0 1 3.3 MHz
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1 X 2.5 MHz or less
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(Typ conditions: Top = 27 oC; Vdd = Voc = 2.7 V, Crystal ESR = 30 Ohm)
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Bit 3 (ddy): Switches on the delay in the phase detector when this bit is set.
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Bit 2 (ddit): When set, disables the dithering in the PLL loop.
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Bit 0 (bw0): PLL bandwidth can be set for optimal TX RF performance.
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bw0 Max bit rate [kbps] Phase noise at 1MHz offset [dBc/Hz]
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0 86.2 -107
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1 256 -102
|
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|
Note: Needed for optimization of the RF
|
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|
performance. Optimal settings can vary
|
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|
according to the external load capacitance.
|
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|
*/
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#define RFM12_CMD_PLL 0xCC02
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#define RFM12_PLL_DDY 0x08
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#define RFM12_PLL_DDIT 0x04
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#define RFM12_PLL_BW0 0x01
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|
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|
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|
/*
|
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13. Transmitter Register Write Command
|
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
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1 0 1 1 1 0 0 0 t7 t6 t5 t4 t3 t2 t1 t0 B8AAh
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With this command, the controller can write 8 bits (t7 to t0) to the transmitter data register. Bit 7 (el) must be set in Configuration
|
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Setting Command.
|
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|
*/
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#define RFM12_CMD_TX 0xB800
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|
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|
/*
|
|
|
14. Wake-Up Timer Command
|
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
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1 1 1 r4 r3 r2 r1 r0 m7 m6 m5 m4 m3 m2 m1 m0 E196h
|
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|
The wake-up time period can be calculated by (m7 to m0) and (r4 to r0):
|
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|
Twake-up = 1.03 * M * 2R + 0.5 [ms]
|
|
|
Note:
|
|
|
• For continual operation the ew bit should be cleared and set at the end of every cycle.
|
|
|
• For future compatibility, use R in a range of 0 and 29.
|
|
|
*/
|
|
|
#define RFM12_CMD_WAKEUP 0xE000
|
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|
|
|
|
|
|
|
/*
|
|
|
15. Low Duty-Cycle Command
|
|
|
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
|
|
|
1 1 0 0 1 0 0 0 d6 d5 d4 d3 d2 d1 d0 en C80Eh
|
|
|
With this command, Low Duty-Cycle operation can be set in order to decrease the average power consumption in receiver mode.
|
|
|
The time cycle is determined by the Wake-Up Timer Command.
|
|
|
The Duty-Cycle can be calculated by using (d6 to d0) and M. (M is parameter in a Wake-Up Timer Command.)
|
|
|
Duty-Cycle= (D * 2 +1) / M *100%
|
|
|
The on-cycle is automatically extended while DQD indicates good received signal condition (FSK transmission is detected in the
|
|
|
frequency range determined by Frequency Setting Command plus and minus the baseband filter bandwidth determined by the
|
|
|
Receiver Control Command).
|
|
|
*/
|
|
|
#define RFM12_CMD_DUTYCYCLE 0xC800
|
|
|
#define RFM12_DUTYCYCLE_ENABLE 0x01
|
|
|
|
|
|
/*
|
|
|
16. Low Battery Detector and Microcontroller Clock Divider Command
|
|
|
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
|
|
|
1 1 0 0 0 0 0 0 d2 d1 d0 0 v3 v2 v1 v0 C000h
|
|
|
The 4 bit parameter (v3 to v0) represents the value V, which defines the threshold voltage Vlb of the detector:
|
|
|
Vlb= 2.25 + V * 0.1 [V]
|
|
|
Clock divider configuration:
|
|
|
Clock Output
|
|
|
Frequency [MHz]
|
|
|
0 0 0 1
|
|
|
0 0 1 1.25
|
|
|
0 1 0 1.66
|
|
|
0 1 1 2
|
|
|
1 0 0 2.5
|
|
|
1 0 1 3.33
|
|
|
1 1 0 5
|
|
|
1 1 1 10
|
|
|
d2 d1 d0
|
|
|
The low battery detector and the clock output can be enabled or disabled by bits eb and dc, respectively, using the Power
|
|
|
Management Command.
|
|
|
*/
|
|
|
#define RFM12_CMD_LBDMCD 0xC000
|
|
|
|
|
|
#define RFM12_LBD_VOLTAGE_2V2 0
|
|
|
#define RFM12_LBD_VOLTAGE_2V3 1
|
|
|
#define RFM12_LBD_VOLTAGE_2V4 2
|
|
|
#define RFM12_LBD_VOLTAGE_2V5 3
|
|
|
#define RFM12_LBD_VOLTAGE_2V6 4
|
|
|
#define RFM12_LBD_VOLTAGE_2V7 5
|
|
|
#define RFM12_LBD_VOLTAGE_2V8 6
|
|
|
#define RFM12_LBD_VOLTAGE_2V9 7
|
|
|
#define RFM12_LBD_VOLTAGE_3V0 8
|
|
|
#define RFM12_LBD_VOLTAGE_3V1 9
|
|
|
#define RFM12_LBD_VOLTAGE_3V2 10
|
|
|
#define RFM12_LBD_VOLTAGE_3V3 11
|
|
|
#define RFM12_LBD_VOLTAGE_3V4 12
|
|
|
#define RFM12_LBD_VOLTAGE_3V5 13
|
|
|
#define RFM12_LBD_VOLTAGE_3V6 14
|
|
|
#define RFM12_LBD_VOLTAGE_3V7 15
|
|
|
|
|
|
#define RFM12_CLOCK_OUT_FREQUENCY_1_00_MHz (0<<5)
|
|
|
#define RFM12_CLOCK_OUT_FREQUENCY_1_25_MHz (1<<5)
|
|
|
#define RFM12_CLOCK_OUT_FREQUENCY_1_66_MHz (2<<5)
|
|
|
#define RFM12_CLOCK_OUT_FREQUENCY_2_00_MHz (3<<5)
|
|
|
#define RFM12_CLOCK_OUT_FREQUENCY_2_50_MHz (4<<5)
|
|
|
#define RFM12_CLOCK_OUT_FREQUENCY_3_33_MHz (5<<5)
|
|
|
#define RFM12_CLOCK_OUT_FREQUENCY_5_00_MHz (6<<5)
|
|
|
#define RFM12_CLOCK_OUT_FREQUENCY_10_00_MHz (7<<5)
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
17. Status Read Command
|
|
|
The read command starts with a zero, whereas all other control commands start with a one. If a read command is identified, the
|
|
|
status bits will be clocked out on the SDO pin as follows:
|
|
|
|
|
|
bitnumber
|
|
|
15 RGIT TX register is ready to receive the next byte (Can be cleared by Transmitter Register Write Command)
|
|
|
FFIT The number of data bits in the RX FIFO has reached the pre-programmed limit (Can be cleared by any of the
|
|
|
FIFO read methods)
|
|
|
14 POR Power-on reset (Cleared after Status Read Command)
|
|
|
13 RGUR TX register under run, register over write (Cleared after Status Read Command)
|
|
|
FFOV RX FIFO overflow (Cleared after Status Read Command)
|
|
|
12 WKUP Wake-up timer overflow (Cleared after Status Read Command)
|
|
|
11 EXT Logic level on interrupt pin (pin 16) changed to low (Cleared after Status Read Command)
|
|
|
10 LBD Low battery detect, the power supply voltage is below the pre-programmed limit
|
|
|
9 FFEM FIFO is empty
|
|
|
8 ATS Antenna tuning circuit detected strong enough RF signal
|
|
|
RSSI The strength of the incoming signal is above the pre-programmed limit
|
|
|
7 DQD Data quality detector output
|
|
|
6 CRL Clock recovery locked
|
|
|
5 ATGL Toggling in each AFC cycle
|
|
|
4 OFFS(6) MSB of the measured frequency offset (sign of the offset value)
|
|
|
3 OFFS(3) -OFFS(0) Offset value to be added to the value of the frequency control parameter (Four LSB bits)
|
|
|
2
|
|
|
1
|
|
|
0
|
|
|
*/
|
|
|
|
|
|
#define RFM12_CMD_STATUS 0x0000
|
|
|
#define RFM12_STATUS_RGIT 0x8000
|
|
|
#define RFM12_STATUS_FFIT 0x8000
|
|
|
#define RFM12_STATUS_POR 0x4000
|
|
|
#define RFM12_STATUS_RGUR 0x2000
|
|
|
#define RFM12_STATUS_FFOV 0x2000
|
|
|
#define RFM12_STATUS_WKUP 0x1000
|
|
|
#define RFM12_STATUS_EXT 0x0800
|
|
|
#define RFM12_STATUS_LBD 0x0400
|
|
|
#define RFM12_STATUS_FFEM 0x0200
|
|
|
#define RFM12_STATUS_ATS 0x0100
|
|
|
#define RFM12_STATUS_RSSI 0x0100
|
|
|
#define RFM12_STATUS_DQD 0x0080
|
|
|
#define RFM12_STATUS_CRL 0x0040
|
|
|
#define RFM12_STATUS_ATGL 0x0020
|
|
|
|
|
|
|
|
|
/* undocumented software reset command for the rf12
|
|
|
*/
|
|
|
#define RFM12_RESET 0xffff
|
