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  1. /**** RFM 12 library for Atmel AVR Microcontrollers *******
  2. *
  3. * This software is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License as published
  5. * by the Free Software Foundation; either version 2 of the License,
  6. * or (at your option) any later version.
  7. *
  8. * This software is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. * General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this software; if not, write to the Free Software
  15. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  16. * USA.
  17. *
  18. * @author Peter Fuhrmann, Hans-Gert Dahmen, Soeren Heisrath
  19. */
  20. /* Configuration setting command
  21. Bit el enables the internal data register.
  22. Bit ef enables the FIFO mode. If ef=0 then DATA (pin 6) and DCLK (pin 7) are used for data and data clock output.
  23. x3 x2 x1 x0 Crystal Load Capacitance [pF]
  24. 0 0 0 0 8.5
  25. 0 0 0 1 9.0
  26. 0 0 1 0 9.5
  27. 0 0 1 1 10.0
  28. ....
  29. 1 1 1 0 15.5
  30. 1 1 1 1 16.0
  31. */
  32. # define RFM12_CMD_CFG 0x8000
  33. # define RFM12_CFG_EL 0x80
  34. # define RFM12_CFG_EF 0x40
  35. # define RFM12_CFG_BAND_MASK 0x30
  36. # define RFM12_BAND_315 0x00
  37. # define RFM12_BAND_433 0x10
  38. # define RFM12_BAND_868 0x20
  39. # define RFM12_BAND_915 0x30
  40. # define RFM12_CFG_XTAL_MASK 0x0F
  41. # define RFM12_XTAL_8_5PF 0x00
  42. # define RFM12_XTAL_9_0PF 0x01
  43. # define RFM12_XTAL_9_5PF 0x02
  44. # define RFM12_XTAL_10_0PF 0x03
  45. # define RFM12_XTAL_10_5PF 0x04
  46. # define RFM12_XTAL_11_0PF 0x05
  47. # define RFM12_XTAL_11_5PF 0x06
  48. # define RFM12_XTAL_12_0PF 0x07
  49. # define RFM12_XTAL_12_5PF 0x08
  50. # define RFM12_XTAL_13_0PF 0x09
  51. # define RFM12_XTAL_13_5PF 0x0A
  52. # define RFM12_XTAL_14_0PF 0x0B
  53. # define RFM12_XTAL_14_5PF 0x0C
  54. # define RFM12_XTAL_15_0PF 0x0D
  55. # define RFM12_XTAL_15_5PF 0x0E
  56. # define RFM12_XTAL_16_0PF 0x0F
  57. /*
  58. 2. Power Management Command
  59. Bit Function of the control bit Related blocks
  60. er Enables the whole receiver chain RF front end, baseband, synthesizer, oscillator
  61. ebb The receiver baseband circuit can be separately switched on Baseband
  62. et Switches on the PLL, the power amplifier, and starts the
  63. transmission (If TX register is enabled) Power amplifier, synthesizer, oscillator
  64. es Turns on the synthesizer Synthesizer
  65. ex Turns on the crystal oscillator Crystal oscillator
  66. eb Enables the low battery detector Low battery detector
  67. ew Enables the wake-up timer Wake-up timer
  68. dc Disables the clock output (pin 8) Clock output buffer
  69. */
  70. #define RFM12_CMD_PWRMGT 0x8200
  71. #define RFM12_PWRMGT_ER 0x80
  72. #define RFM12_PWRMGT_EBB 0x40
  73. #define RFM12_PWRMGT_ET 0x20
  74. #define RFM12_PWRMGT_ES 0x10
  75. #define RFM12_PWRMGT_EX 0x08
  76. #define RFM12_PWRMGT_EB 0x04
  77. #define RFM12_PWRMGT_EW 0x02
  78. #define RFM12_PWRMGT_DC 0x01
  79. /*
  80. 3. Frequency Setting Command
  81. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
  82. 1 0 1 0 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 A680h
  83. The 12-bit parameter F (bits f11 to f0) should be in the range
  84. of 96 and 3903. When F value sent is out of range, the
  85. previous value is kept. The synthesizer center frequency f0 can
  86. be calculated as:
  87. f0 = 10 * C1 * (C2 + F/4000) [MHz]
  88. The constants C1 and C2 are determined by
  89. the selected band as:
  90. Band [MHz] C1 C2
  91. 433 1 43
  92. 868 2 43
  93. 915 3 30
  94. Frequency in 433 Band can be from 430.24MHz to 439.7575MHz in 2.5kHz increments.
  95. */
  96. #define RFM12_CMD_FREQUENCY 0xA000
  97. #define RFM12_FREQUENCY_MASK 0x0FFF
  98. #define RFM12_FREQUENCY_CALC_433(f) (((f)-430000000UL)/2500UL)
  99. #define RFM12_FREQUENCY_CALC_868(f) (((f)-860000000UL)/5000UL)
  100. #define RFM12_FREQUENCY_CALC_915(f) (((f)-900000000UL)/7500UL)
  101. /*
  102. 4. Data Rate Command
  103. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
  104. 1 1 0 0 0 1 1 0 cs r6 r5 r4 r3 r2 r1 r0 C623h
  105. The actual bit rate in transmit mode and the expected bit rate of the received data stream in receive mode is determined by the 7-bit
  106. parameter R (bits r6 to r0) and bit cs.
  107. BR = 10000 / 29 / (R+1) / (1+cs*7) [kbps]
  108. In the receiver set R according to the next function:
  109. R = (10000 / 29 / (1+cs*7) / BR) – 1, where BR is the expected bit rate in kbps.
  110. Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with small error.
  111. Data rate accuracy requirements:
  112. Clock recovery in slow mode: ΔBR/BR < 1/(29*Nbit) Clock recovery in fast mode: ΔBR/BR < 3/(29*Nbit)
  113. BR is the bit rate set in the receiver and ΔBR is the bit rate difference between the transmitter and the receiver. Nbit is the maximum
  114. number of consecutive ones or zeros in the data stream. It is recommended for long data packets to include enough 1/0 and 0/1
  115. transitions, and to be careful to use the same division ratio in the receiver and in the transmitter.
  116. */
  117. #define RFM12_CMD_DATARATE 0xC600
  118. #define RFM12_DATARATE_CS 0x80
  119. //calculate setting for datarates >= 2700 Baud
  120. #define RFM12_DATARATE_CALC_HIGH(d) ((uint8_t)((10000000.0/29.0/d)-0.5))
  121. //calculate setting for datarates < 2700 Baud
  122. #define RFM12_DATARATE_CALC_LOW(d) (RFM12_DATARATE_CS|(uint8_t)((10000000.0/29.0/8.0/d)-0.5))
  123. #define RFM12_DATARATE_MASK 0x00ff
  124. /*
  125. 5. Receiver Control Command
  126. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
  127. 1 0 0 1 0 p16 d1 d0 i2 i1 i0 g1 g0 r2 r1 r0 9080h
  128. Bit 10 (p16): pin16 function select
  129. p16 Function of pin 16
  130. 0 Interrupt input
  131. 1 VDI output
  132. Bits 9-8 (d1 to d0): VDI (valid data indicator) signal response time setting:
  133. d1 d0 Response
  134. 0 0 Fast
  135. 0 1 Medium
  136. 1 0 Slow
  137. 1 1 Always on
  138. Bits 7-5 (i2 to i0): Receiver baseband bandwidth (BW) select:
  139. i2 i1 i0 BW [kHz]
  140. 0 0 0 reserved
  141. 0 0 1 400
  142. 0 1 0 340
  143. 0 1 1 270
  144. 1 0 0 200
  145. 1 0 1 134
  146. 1 1 0 67
  147. 1 1 1 reserved
  148. Bits 4-3 (g1 to g0): LNA gain select:
  149. g1 g0 relative to maximum [dB]
  150. 0 0 0
  151. 0 1 -6
  152. 1 0 -14
  153. 1 1 -20
  154. Bits 2-0 (r2 to r0): RSSI detector threshold:
  155. r2 r1 r0 RSSIsetth [dBm]
  156. 0 0 0 -103
  157. 0 0 1 -97
  158. 0 1 0 -91
  159. 0 1 1 -85
  160. 1 0 0 -79
  161. 1 0 1 -73
  162. 1 1 0 Reserved
  163. 1 1 1 Reserved
  164. The RSSI threshold depends on the LNA gain, the real RSSI threshold can be calculated:
  165. RSSIth=RSSIsetth+GLNA
  166. */
  167. #define RFM12_CMD_RXCTRL 0x9000
  168. #define RFM12_RXCTRL_P16_VDI 0x400
  169. #define RFM12_RXCTRL_VDI_FAST 0x000
  170. #define RFM12_RXCTRL_VDI_MEDIUM 0x100
  171. #define RFM12_RXCTRL_VDI_SLOW 0x200
  172. #define RFM12_RXCTRL_VDI_ALWAYS_ON 0x300
  173. #define RFM12_RXCTRL_BW_MASK 0xE0
  174. #define RFM12_RXCTRL_BW_400 0x20
  175. #define RFM12_RXCTRL_BW_340 0x40
  176. #define RFM12_RXCTRL_BW_270 0x60
  177. #define RFM12_RXCTRL_BW_200 0x80
  178. #define RFM12_RXCTRL_BW_134 0xA0
  179. #define RFM12_RXCTRL_BW_67 0xC0
  180. #define RFM12_RXCTRL_LNA_MASK 0x18
  181. #define RFM12_RXCTRL_LNA_0 0x00
  182. #define RFM12_RXCTRL_LNA_6 0x08
  183. #define RFM12_RXCTRL_LNA_14 0x10
  184. #define RFM12_RXCTRL_LNA_20 0x18
  185. #define RFM12_RXCTRL_RSSI_103 0x00
  186. #define RFM12_RXCTRL_RSSI_97 0x01
  187. #define RFM12_RXCTRL_RSSI_91 0x02
  188. #define RFM12_RXCTRL_RSSI_85 0x03
  189. #define RFM12_RXCTRL_RSSI_79 0x04
  190. #define RFM12_RXCTRL_RSSI_73 0x05
  191. #define RFM12_RXCTRL_RSSI_67 0x06
  192. #define RFM12_RXCTRL_RSSI_61 0x07
  193. #define RFM12_RXCTRL_RSSI_MASK 0x07
  194. /*
  195. 6. Data Filter Command
  196. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
  197. 1 1 0 0 0 0 1 0 al ml 1 s 1 f2 f1 f0 C22Ch
  198. Bit 7 (al): Clock recovery (CR) auto lock control, if set.
  199. CR will start in fast mode, then after locking it will automatically switch to slow mode.
  200. Bit 6 (ml): Clock recovery lock control
  201. 1: fast mode, fast attack and fast release (4 to 8 bit preamble (1010...) is recommended)
  202. 0: slow mode, slow attack and slow release (12 to 16 bit preamble is recommended)
  203. Using the slow mode requires more accurate bit timing (see Data Rate Command).
  204. Bits 4 (s): Select the type of the data filter:
  205. s Filter Type
  206. 0 Digital filter
  207. 1 Analog RC filter
  208. Digital: This is a digital realization of an analog RC filter followed by a comparator with hysteresis. The time constant is
  209. automatically adjusted to the bit rate defined by the Data Rate Command.
  210. Note: Bit rate can not exceed 115 kpbs in this mode.
  211. Analog RC filter: The demodulator output is fed to pin 7 over a 10 kOhm resistor. The filter cut-off frequency is set by the
  212. external capacitor connected to this pin and VSS.
  213. Bits 2-0 (f2 to f0): DQD threshold parameter.
  214. Note: To let the DQD report "good signal quality" the threshold parameter should be 4 in cases where the bitrate is close to the
  215. deviation. At higher deviation/bitrate settings, a higher threshold parameter can report "good signal quality" as well.
  216. */
  217. #define RFM12_CMD_DATAFILTER 0xC228
  218. #define RFM12_DATAFILTER_AL 0x80
  219. #define RFM12_DATAFILTER_ML 0x40
  220. #define RFM12_DATAFILTER_S 0x10
  221. /*
  222. 7. FIFO and Reset Mode Command
  223. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
  224. 1 1 0 0 1 0 1 0 f3 f2 f1 f0 sp al ff dr CA80h
  225. Bits 7-4 (f3 to f0): FIFO IT level. The FIFO generates IT when the number of received data bits reaches this level.
  226. Bit 3 (sp): Select the length of the synchron pattern:
  227. sp Byte1 Byte0 (POR) Synchron Pattern (Byte1+Byte0)
  228. 0 2Dh D4h 2DD4h
  229. 1 Not used D4h D4h
  230. Note: Byte0 can be programmed by the Synchron Pattern Command.
  231. Bit 2 (al): Set the input of the FIFO fill start condition:
  232. al
  233. 0 Synchron pattern
  234. 1 Always fill
  235. Bit 1 (ff): FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared.
  236. Bit 0 (dr): Disables the highly sensitive RESET mode.
  237. */
  238. #define RFM12_CMD_FIFORESET 0xCA00
  239. #define RFM12_FIFORESET_SP 0x08
  240. #define RFM12_FIFORESET_AL 0x04
  241. #define RFM12_FIFORESET_FF 0x02
  242. #define RFM12_FIFORESET_DR 0x01
  243. /*
  244. 8. Synchron Pattern Command
  245. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
  246. 1 1 0 0 1 1 1 0 b7 b6 b5 b4 b3 b2 b1 b0 CED4h
  247. The Byte0 used for synchron pattern detection can be reprogrammed by B <b7:b0>.
  248. */
  249. #define RFM12_CMD_SYNCPATTERN 0xCE00
  250. /*
  251. 9. Receiver FIFO Read Command
  252. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
  253. 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 B000h
  254. With this command, the controller can read 8 bits from the receiver FIFO. Bit 6 (ef) must be set in Configuration Setting Command.
  255. Note:: During FIFO access fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency. When the duty-cycle of the
  256. clock signal is not 50 % the shorter period of the clock pulse width should be at least 2/fref .
  257. */
  258. #define RFM12_CMD_READ 0xB000
  259. /*
  260. 10. AFC Command
  261. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
  262. 1 1 0 0 0 1 0 0 a1 a0 rl1 rl0 st fi oe en C4F7h
  263. Bit 7-6 (a1 to a0): Automatic operation mode selector:
  264. a1 a0
  265. 0 0 Auto mode off (Strobe is controlled by microcontroller)
  266. 0 1 Runs only once after each power-up
  267. 1 0 Keep the foffset only during receiving (VDI=high)
  268. 1 1 Keep the foffset value independently from the state of the VDI signal
  269. Bit 5-4 (rl1 to rl0): Range limit. Limits the value of the frequency offset register to the next values:
  270. rl1 rl0 Max deviation
  271. 0 0 No restriction (+63 fres to -64 fres)
  272. 0 1 +15 fres to -16 fres
  273. 1 0 +7 fres to -8 fres
  274. 1 1 +3 fres to -4 fres
  275. fres:
  276. 433 MHz bands: 2.5 kHz
  277. 868 MHz band: 5 kHz
  278. 915 MHz band: 7.5 kHz
  279. Bit 3 (st): Strobe edge, when st goes to high, the actual latest calculated frequency error is stored into the offset register of the AFC
  280. block.
  281. Bit 2 (fi): Switches the circuit to high accuracy (fine) mode. In this case, the processing time is about twice as long, but the measurement
  282. uncertainty is about half.
  283. Bit 1 (oe): Enables the frequency offset register. It allows the addition of the offset register to the frequency control word of the PLL.
  284. Bit 0 (en): Enables the calculation of the offset frequency by the AFC circuit.
  285. In automatic operation mode (no strobe signal is needed from the microcontroller to update the output offset register) the AFC circuit
  286. is automatically enabled when the VDI indicates potential incoming signal during the whole measurement cycle and the circuit
  287. measures the same result in two subsequent cycles.
  288. There are three operation modes, examples from the possible application:
  289. 1, (a1=0, a0=1) The circuit measures the frequency offset only once after power up. This way, extended TX-RX maximum distance
  290. can be achieved.
  291. Possible application:
  292. In the final application, when the user inserts the battery, the circuit measures and compensates for the frequency offset caused by
  293. the crystal tolerances. This method allows for the use of a cheaper quartz in the application and provides protection against tracking
  294. an interferer.
  295. 2a, (a1=1, a0=0) The circuit automatically measures the frequency offset during an initial effective low data rate pattern –easier to
  296. receive- (i.e.: 00110011) of the package and changes the receiving frequency accordingly. The further part of the package can be
  297. received by the corrected frequency settings.
  298. 2b, (a1=1, a0=0) The transmitter must transmit the first part of the packet with a step higher deviation and later there is a possibility
  299. of reducing it.
  300. In both cases (2a and 2b), when the VDI indicates poor receiving conditions (VDI goes low), the output register is automatically
  301. cleared. Use these settings when receiving signals from different transmitters transmitting in the same nominal frequencies.
  302. 3, (a1=1, a0=1) It’s the same as 2a and 2b modes, but suggested to use when a receiver operates with only one transmitter. After a
  303. complete measuring cycle, the measured value is kept independently of the state of the VDI signal.
  304. */
  305. #define RFM12_CMD_AFC 0xC400
  306. #define RFM12_AFC_AUTO_OFF 0x00
  307. #define RFM12_AFC_AUTO_ONCE 0x40
  308. #define RFM12_AFC_AUTO_VDI 0x80
  309. #define RFM12_AFC_AUTO_KEEP 0xC0
  310. #define RFM12_AFC_LIMIT_OFF 0x00 /* 64 */
  311. #define RFM12_AFC_LIMIT_16 0x10
  312. #define RFM12_AFC_LIMIT_8 0x20
  313. #define RFM12_AFC_LIMIT_4 0x30
  314. #define RFM12_AFC_ST 0x08
  315. #define RFM12_AFC_FI 0x04
  316. #define RFM12_AFC_OE 0x02
  317. #define RFM12_AFC_EN 0x01
  318. /*
  319. 11. TX Configuration Control Command
  320. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
  321. 1 0 0 1 1 0 0 mp m3 m2 m1 m0 0 p2 p1 p0 9800h
  322. Bits 8-4 (mp, m3 to m0): FSK modulation parameters:
  323. The resulting output frequency can be calculated as:
  324. fout = f0 + (-1)SIGN * (M + 1) * (15 kHz)
  325. where:
  326. f0 is the channel center frequency (see the
  327. Frequency Setting Command)
  328. M is the four bit binary number <m3 : m0>
  329. SIGN = (mp) XOR FSK
  330. Bits 2-0 (p2 to p0): Output power:
  331. p2 p1 p0 Relative Output Power [dB]
  332. 0 0 0 0
  333. 0 0 1 -2.5
  334. 0 1 0 -5
  335. 0 1 1 -7.5
  336. 1 0 0 -10
  337. 1 0 1 -12.5
  338. 1 1 0 -15
  339. 1 1 1 -17.5
  340. */
  341. #define RFM12_CMD_TXCONF 0x9800
  342. #define RFM12_TXCONF_MP 0x100
  343. #define RFM12_TXCONF_POWER_0 0x00
  344. #define RFM12_TXCONF_POWER_3 0x01
  345. #define RFM12_TXCONF_POWER_6 0x02
  346. #define RFM12_TXCONF_POWER_9 0x03
  347. #define RFM12_TXCONF_POWER_12 0x04
  348. #define RFM12_TXCONF_POWER_15 0x05
  349. #define RFM12_TXCONF_POWER_18 0x06
  350. #define RFM12_TXCONF_POWER_21 0x07
  351. #define RFM12_TXCONF_FSK_MASK 0xf0
  352. #define RFM12_TXCONF_FS_CALC(f) (((f/15000UL)-1)<<4)
  353. #define RFM12_TXCONF_MASK 0x01F7
  354. #define RFM12_TXCONF_POWER_MASK 0x07
  355. /*
  356. 12. PLL Setting Command
  357. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
  358. 1 1 0 0 1 1 0 0 0 ob1 ob0 0 ddy ddit 1 bw0 CC67h
  359. Note: POR default setting of the register carefully selected to cover almost all typical applications.
  360. Bit 6-5 (ob1-ob0): Microcontroller output clock buffer rise and fall time control.
  361. ob1 ob0 Selected uC CLK frequency
  362. 0 0 5 or 10 MHz (recommended)
  363. 0 1 3.3 MHz
  364. 1 X 2.5 MHz or less
  365. (Typ conditions: Top = 27 oC; Vdd = Voc = 2.7 V, Crystal ESR = 30 Ohm)
  366. Bit 3 (ddy): Switches on the delay in the phase detector when this bit is set.
  367. Bit 2 (ddit): When set, disables the dithering in the PLL loop.
  368. Bit 0 (bw0): PLL bandwidth can be set for optimal TX RF performance.
  369. bw0 Max bit rate [kbps] Phase noise at 1MHz offset [dBc/Hz]
  370. 0 86.2 -107
  371. 1 256 -102
  372. Note: Needed for optimization of the RF
  373. performance. Optimal settings can vary
  374. according to the external load capacitance.
  375. */
  376. #define RFM12_CMD_PLL 0xCC02
  377. #define RFM12_PLL_DDY 0x08
  378. #define RFM12_PLL_DDIT 0x04
  379. #define RFM12_PLL_BW0 0x01
  380. /*
  381. 13. Transmitter Register Write Command
  382. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
  383. 1 0 1 1 1 0 0 0 t7 t6 t5 t4 t3 t2 t1 t0 B8AAh
  384. With this command, the controller can write 8 bits (t7 to t0) to the transmitter data register. Bit 7 (el) must be set in Configuration
  385. Setting Command.
  386. */
  387. #define RFM12_CMD_TX 0xB800
  388. /*
  389. 14. Wake-Up Timer Command
  390. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
  391. 1 1 1 r4 r3 r2 r1 r0 m7 m6 m5 m4 m3 m2 m1 m0 E196h
  392. The wake-up time period can be calculated by (m7 to m0) and (r4 to r0):
  393. Twake-up = 1.03 * M * 2R + 0.5 [ms]
  394. Note:
  395. • For continual operation the ew bit should be cleared and set at the end of every cycle.
  396. • For future compatibility, use R in a range of 0 and 29.
  397. */
  398. #define RFM12_CMD_WAKEUP 0xE000
  399. /*
  400. 15. Low Duty-Cycle Command
  401. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
  402. 1 1 0 0 1 0 0 0 d6 d5 d4 d3 d2 d1 d0 en C80Eh
  403. With this command, Low Duty-Cycle operation can be set in order to decrease the average power consumption in receiver mode.
  404. The time cycle is determined by the Wake-Up Timer Command.
  405. The Duty-Cycle can be calculated by using (d6 to d0) and M. (M is parameter in a Wake-Up Timer Command.)
  406. Duty-Cycle= (D * 2 +1) / M *100%
  407. The on-cycle is automatically extended while DQD indicates good received signal condition (FSK transmission is detected in the
  408. frequency range determined by Frequency Setting Command plus and minus the baseband filter bandwidth determined by the
  409. Receiver Control Command).
  410. */
  411. #define RFM12_CMD_DUTYCYCLE 0xC800
  412. #define RFM12_DUTYCYCLE_ENABLE 0x01
  413. /*
  414. 16. Low Battery Detector and Microcontroller Clock Divider Command
  415. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
  416. 1 1 0 0 0 0 0 0 d2 d1 d0 0 v3 v2 v1 v0 C000h
  417. The 4 bit parameter (v3 to v0) represents the value V, which defines the threshold voltage Vlb of the detector:
  418. Vlb= 2.25 + V * 0.1 [V]
  419. Clock divider configuration:
  420. Clock Output
  421. Frequency [MHz]
  422. 0 0 0 1
  423. 0 0 1 1.25
  424. 0 1 0 1.66
  425. 0 1 1 2
  426. 1 0 0 2.5
  427. 1 0 1 3.33
  428. 1 1 0 5
  429. 1 1 1 10
  430. d2 d1 d0
  431. The low battery detector and the clock output can be enabled or disabled by bits eb and dc, respectively, using the Power
  432. Management Command.
  433. */
  434. #define RFM12_CMD_LBDMCD 0xC000
  435. #define RFM12_LBD_VOLTAGE_2V2 0
  436. #define RFM12_LBD_VOLTAGE_2V3 1
  437. #define RFM12_LBD_VOLTAGE_2V4 2
  438. #define RFM12_LBD_VOLTAGE_2V5 3
  439. #define RFM12_LBD_VOLTAGE_2V6 4
  440. #define RFM12_LBD_VOLTAGE_2V7 5
  441. #define RFM12_LBD_VOLTAGE_2V8 6
  442. #define RFM12_LBD_VOLTAGE_2V9 7
  443. #define RFM12_LBD_VOLTAGE_3V0 8
  444. #define RFM12_LBD_VOLTAGE_3V1 9
  445. #define RFM12_LBD_VOLTAGE_3V2 10
  446. #define RFM12_LBD_VOLTAGE_3V3 11
  447. #define RFM12_LBD_VOLTAGE_3V4 12
  448. #define RFM12_LBD_VOLTAGE_3V5 13
  449. #define RFM12_LBD_VOLTAGE_3V6 14
  450. #define RFM12_LBD_VOLTAGE_3V7 15
  451. #define RFM12_CLOCK_OUT_FREQUENCY_1_00_MHz (0<<5)
  452. #define RFM12_CLOCK_OUT_FREQUENCY_1_25_MHz (1<<5)
  453. #define RFM12_CLOCK_OUT_FREQUENCY_1_66_MHz (2<<5)
  454. #define RFM12_CLOCK_OUT_FREQUENCY_2_00_MHz (3<<5)
  455. #define RFM12_CLOCK_OUT_FREQUENCY_2_50_MHz (4<<5)
  456. #define RFM12_CLOCK_OUT_FREQUENCY_3_33_MHz (5<<5)
  457. #define RFM12_CLOCK_OUT_FREQUENCY_5_00_MHz (6<<5)
  458. #define RFM12_CLOCK_OUT_FREQUENCY_10_00_MHz (7<<5)
  459. /*
  460. 17. Status Read Command
  461. The read command starts with a zero, whereas all other control commands start with a one. If a read command is identified, the
  462. status bits will be clocked out on the SDO pin as follows:
  463. bitnumber
  464. 15 RGIT TX register is ready to receive the next byte (Can be cleared by Transmitter Register Write Command)
  465. FFIT The number of data bits in the RX FIFO has reached the pre-programmed limit (Can be cleared by any of the
  466. FIFO read methods)
  467. 14 POR Power-on reset (Cleared after Status Read Command)
  468. 13 RGUR TX register under run, register over write (Cleared after Status Read Command)
  469. FFOV RX FIFO overflow (Cleared after Status Read Command)
  470. 12 WKUP Wake-up timer overflow (Cleared after Status Read Command)
  471. 11 EXT Logic level on interrupt pin (pin 16) changed to low (Cleared after Status Read Command)
  472. 10 LBD Low battery detect, the power supply voltage is below the pre-programmed limit
  473. 9 FFEM FIFO is empty
  474. 8 ATS Antenna tuning circuit detected strong enough RF signal
  475. RSSI The strength of the incoming signal is above the pre-programmed limit
  476. 7 DQD Data quality detector output
  477. 6 CRL Clock recovery locked
  478. 5 ATGL Toggling in each AFC cycle
  479. 4 OFFS(6) MSB of the measured frequency offset (sign of the offset value)
  480. 3 OFFS(3) -OFFS(0) Offset value to be added to the value of the frequency control parameter (Four LSB bits)
  481. 2
  482. 1
  483. 0
  484. */
  485. #define RFM12_CMD_STATUS 0x0000
  486. #define RFM12_STATUS_RGIT 0x8000
  487. #define RFM12_STATUS_FFIT 0x8000
  488. #define RFM12_STATUS_POR 0x4000
  489. #define RFM12_STATUS_RGUR 0x2000
  490. #define RFM12_STATUS_FFOV 0x2000
  491. #define RFM12_STATUS_WKUP 0x1000
  492. #define RFM12_STATUS_EXT 0x0800
  493. #define RFM12_STATUS_LBD 0x0400
  494. #define RFM12_STATUS_FFEM 0x0200
  495. #define RFM12_STATUS_ATS 0x0100
  496. #define RFM12_STATUS_RSSI 0x0100
  497. #define RFM12_STATUS_DQD 0x0080
  498. #define RFM12_STATUS_CRL 0x0040
  499. #define RFM12_STATUS_ATGL 0x0020
  500. /* undocumented software reset command for the rf12
  501. */
  502. #define RFM12_RESET 0xffff