store SPI speed in eeprom
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9205611c5a
commit
a6a64dbf33
126
ispprog.c
126
ispprog.c
@ -19,9 +19,11 @@
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#include <avr/io.h>
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#include <avr/eeprom.h>
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#include <avr/pgmspace.h>
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#include <avr/interrupt.h>
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#include <string.h>
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#include <util/crc16.h>
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof(*x))
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@ -99,9 +101,6 @@ static struct _device devices[] PROGMEM = {
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{ { 0x1E, 0x97, 0x02 }, 0x43, 0x7F, POLL_FF }, /* mega128 */
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};
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/* sorted devcodes from devices[], terminated with 0x00 */
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static uint8_t devcodes[] PROGMEM = { 0x13, 0x20, 0x38, 0x41, 0x43, 0x45, 0x5E, 0x72, 0x74, 0x76, 0x00 };
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#define EV_NONE 0
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#define EV_STATE_ENTER 1
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#define EV_BUTTON_PRESSED 2
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@ -115,6 +114,7 @@ static uint8_t devcodes[] PROGMEM = { 0x13, 0x20, 0x38, 0x41, 0x43, 0x45, 0x5E,
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#define STATE_SPEED2 4
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#define STATE_SPEED3 5
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#define STATE_SPEED4 6
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#define STATE_NVRAM_STORE 7 /* start nvram_write (internal state) */
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#define LED_OFF 0x00
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#define LED_SLOW 0x20
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@ -165,6 +165,76 @@ static uint8_t devcodes[] PROGMEM = { 0x13, 0x20, 0x38, 0x41, 0x43, 0x45, 0x5E,
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#define CMD_WRITE_FUSE_E_1 0xAC /* not used */
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#define CMD_WRITE_FUSE_E_2 0xA4 /* not used */
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struct _nvdata {
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uint8_t nvram_size; /* first */
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uint8_t spi_mode;
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uint16_t nvram_crc; /* last */
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};
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static uint8_t nvram_write_pos;
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static struct _nvdata nvram_data;
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static struct _nvdata nvram_eeprom EEMEM;
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static struct _nvdata nvram_defaults PROGMEM = { .spi_mode = SPI_MODE4 };
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/* create crc and store nvram data to eeprom */
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static void nvram_start_write(void)
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{
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uint8_t i;
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uint16_t crc = 0x0000;
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uint8_t *tmp = (uint8_t *)&nvram_data;
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nvram_data.nvram_size = sizeof(struct _nvdata);
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for (i = 0; i < sizeof(struct _nvdata) -2; i++) {
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crc = _crc_ccitt_update(crc, *tmp++);
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}
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nvram_data.nvram_crc = crc;
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nvram_write_pos = 0;
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EEARL = nvram_write_pos;
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EEARH = 0x00;
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EEDR = ((uint8_t *)&nvram_data)[nvram_write_pos++];
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EECR |= (1<<EEMWE);
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EECR |= (1<<EEWE);
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EECR |= (1<<EERIE);
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}
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/* store nvram data to eeprom */
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ISR(EE_RDY_vect) {
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if (nvram_write_pos < sizeof(struct _nvdata)) {
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EEARL = nvram_write_pos;
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EEARH = 0x00;
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EEDR = ((uint8_t *)&nvram_data)[nvram_write_pos++];
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EECR |= (1<<EEMWE);
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EECR |= (1<<EEWE);
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EECR |= (1<<EERIE);
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} else {
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EECR &= ~(1<<EERIE);
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}
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}
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/* read nvram from eeprom and check crc */
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static void nvram_read(void)
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{
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uint8_t i;
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uint16_t crc = 0x0000;
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uint8_t *tmp = (uint8_t *)&nvram_data;
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eeprom_read_block(&nvram_data, &nvram_eeprom, sizeof(struct _nvdata));
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for (i = 0; i < sizeof(struct _nvdata); i++) {
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crc = _crc_ccitt_update(crc, *tmp++);
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}
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/* if nvram content is invalid, overwrite with defaults */
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if ((nvram_data.nvram_size != sizeof(struct _nvdata)) || (crc != 0x0000)) {
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memcpy_P(&nvram_data, &nvram_defaults, sizeof(struct _nvdata));
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nvram_start_write();
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}
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}
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static volatile uint8_t led_mode;
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static uint8_t last_cmd;
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@ -271,6 +341,7 @@ static void mem_pagewrite(uint16_t addr)
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poll();
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}
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static void cmdloop(void) __attribute__ ((noreturn));
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static void cmdloop(void)
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{
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static uint8_t page_buf[256];
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@ -301,14 +372,14 @@ static void cmdloop(void)
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memset(&device, 0x00, sizeof(struct _device));
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if (sync == CMD_PROG_ENABLE_2) {
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uint8_t i, sig[3];
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uint8_t i;
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for (i = 0; i < 3; i++) {
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sig[i] = mem_read(CMD_READ_SIG_1, (CMD_READ_SIG_2 << 8) | i);
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device.sig[i] = mem_read(CMD_READ_SIG_1, (CMD_READ_SIG_2 << 8) | i);
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}
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for (i = 0; i < ARRAY_SIZE(devices); i++) {
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if (memcmp_P(sig, devices[i].sig, sizeof(sig)) == 0) {
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if (memcmp_P(device.sig, devices[i].sig, sizeof(device.sig)) == 0) {
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memcpy_P(&device, &devices[i], sizeof(struct _device));
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break;
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}
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@ -463,10 +534,24 @@ static void cmdloop(void)
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/* Return supported device codes */
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case 't': {
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uint8_t limit = 0x00;
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while (1) {
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uint8_t i;
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for (i = 0; i < ARRAY_SIZE(devcodes); i++) {
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ser_send(pgm_read_byte(&devcodes[i]));
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uint8_t search = 0xFF;
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for (i = 0; i < ARRAY_SIZE(devices); i++) {
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uint8_t devcode = pgm_read_byte(&devices[i].devcode);
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if ((devcode > limit) && (devcode < search)) {
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search = devcode;
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}
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}
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if (search == 0xFF)
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break;
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ser_send(search);
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limit = search;
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}
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ser_send(0x00);
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break;
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}
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@ -644,7 +729,7 @@ static void cmdloop(void)
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}
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}
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static uint16_t statemachine(uint8_t event)
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static uint16_t button_statemachine(uint8_t event)
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{
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static uint8_t oldstate;
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uint8_t state = oldstate;
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@ -721,7 +806,7 @@ static uint16_t statemachine(uint8_t event)
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state = STATE_SPEED2;
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} else if (event == EV_TIMEOUT) {
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state = STATE_IDLE;
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state = STATE_NVRAM_STORE;
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SPCR = SPI_MODE1;
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}
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break;
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@ -735,7 +820,7 @@ static uint16_t statemachine(uint8_t event)
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state = STATE_SPEED3;
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} else if (event == EV_TIMEOUT) {
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state = STATE_IDLE;
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state = STATE_NVRAM_STORE;
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SPCR = SPI_MODE2;
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}
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break;
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@ -749,7 +834,7 @@ static uint16_t statemachine(uint8_t event)
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state = STATE_SPEED4;
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} else if (event == EV_TIMEOUT) {
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state = STATE_IDLE;
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state = STATE_NVRAM_STORE;
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SPCR = SPI_MODE3;
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}
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break;
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@ -763,7 +848,7 @@ static uint16_t statemachine(uint8_t event)
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state = STATE_SPEED1;
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} else if (event == EV_TIMEOUT) {
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state = STATE_IDLE;
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state = STATE_NVRAM_STORE;
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SPCR = SPI_MODE4;
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}
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break;
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@ -773,6 +858,12 @@ static uint16_t statemachine(uint8_t event)
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break;
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}
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if (state == STATE_NVRAM_STORE) {
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state = STATE_IDLE;
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nvram_data.spi_mode = SPCR;
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nvram_start_write();
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}
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if (event == EV_STATE_ENTER) {
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oldstate = state;
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}
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@ -813,7 +904,7 @@ ISR(TIMER0_OVF_vect)
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}
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if (event != EV_NONE) {
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uint16_t new_timer = statemachine(event);
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uint16_t new_timer = button_statemachine(event);
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if (new_timer == 0xFFFF) {
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timer = 0;
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@ -832,6 +923,7 @@ ISR(TIMER0_OVF_vect)
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}
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}
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int main(void) __attribute__ ((noreturn));
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int main(void)
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{
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/* ISP_RESET and ISP_LED are outputs, pullup SlaveSelect */
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@ -846,8 +938,11 @@ int main(void)
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UCSRB = (1<<TXEN) | (1<<RXEN);
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UCSRC = (1<<URSEL) | (1<<UCSZ1) | (1<<UCSZ0);
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/* read stored parameters */
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nvram_read();
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/* enable SPI master mode */
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SPCR = SPI_MODE4;
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SPCR = nvram_data.spi_mode;
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/* timer0, FCPU/1024, overflow interrupt */
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TCCR0 = (1<<CS02) | (1<<CS00);
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@ -856,5 +951,4 @@ int main(void)
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sei();
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cmdloop();
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return 0;
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}
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