120 lines
4.5 KiB
C
120 lines
4.5 KiB
C
#ifndef TARGET_H_
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#define TARGET_H_
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/* *********************************************************************** */
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#if defined(CONFIG_ispprog)
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/*
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* using ATmega16 @7.3728MHz:
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* Fuse H: 0xDA (512 words bootloader, jtag disabled)
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* Fuse L: 0xFF (ext. Crystal)
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*/
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#define F_CPU 7372800ULL
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#define BAUDRATE 115200
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#define ISP_RESET PORTB1 /* to target */
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#define ISP_LED PORTB3 /* low active */
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#define ISP_MOSI PORTB5 /* to target */
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#define ISP_MISO PORTB6 /* to target */
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#define ISP_SCK PORTB7 /* to target */
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#define RESET_IN PORTD3 /* high active */
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#define RESET_INACTIVE(){ PORTB |= (1<<ISP_RESET); }
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#define RESET_ACTIVE() { PORTB &= ~(1<<ISP_RESET); }
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#define ISP_INACTIVE() { /* ISP_SCK and ISP_MOSI are inputs */ \
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DDRB &= ~((1<<ISP_SCK) | (1<<ISP_MOSI)); \
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};
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#define ISP_ACTIVE() { /* ISP_SCK and ISP_MOSI are outputs */ \
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DDRB |= ((1<<ISP_SCK) | (1<<ISP_MOSI)); \
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};
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#define ISP_LED_ON() { PORTB &= ~(1<<ISP_LED); };
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#define ISP_LED_OFF() { PORTB |= (1<<ISP_LED); };
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#define ISP_CHECK() (PIND & (1<<RESET_IN))
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#define USE_DISPLAY 0
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#define TIMER_DIVISOR 1024
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#define TIMER_INIT() { /* timer0, FCPU/1024, overflow interrupt */ \
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TCCR0 = (1<<CS02) | (1<<CS00); \
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TIMSK = (1<<TOIE0); \
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}
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#define GPIO_INIT() { /* ISP_RESET and ISP_LED are outputs, pullup SlaveSelect */ \
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PORTB = (1<<ISP_RESET) | (1<<ISP_LED) | (1<<PORTB4); \
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DDRB = (1<<ISP_RESET) | (1<<ISP_LED); \
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};
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/* *********************************************************************** */
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#elif defined(CONFIG_ispprog2)
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/*
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* using ATmega328P @8MHz:
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* Fuse E: 0xFA (2.7V BOD)
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* Fuse H: 0xDC (512 words bootloader)
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* Fuse L: 0xE2 (internal osc)
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*/
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#define F_CPU 8000000ULL
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#define BAUDRATE 115200
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/* trim internal oscillator to get "good" baudrate */
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#define OSCCAL_VALUE 0x80
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#define ISP_RESET PORTB2 /* to target */
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#define ISP_LED PORTB0 /* high active */
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#define ISP_MOSI PORTB3 /* to target */
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#define ISP_MISO PORTB4 /* to target */
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#define ISP_SCK PORTB5 /* to target */
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#define RESET_IN PORTB1 /* low active */
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#define RESET_INACTIVE(){ PORTB |= (1<<ISP_RESET); }
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#define RESET_ACTIVE() { PORTB &= ~(1<<ISP_RESET); }
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#define ISP_INACTIVE() { /* ISP_SCK and ISP_MOSI are inputs */ \
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DDRB &= ~((1<<ISP_SCK) | (1<<ISP_MOSI)); \
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};
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#define ISP_ACTIVE() { /* ISP_SCK and ISP_MOSI and ISP_RESET are outputs */ \
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DDRB |= ((1<<ISP_SCK) | (1<<ISP_MOSI)); \
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};
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#define ISP_LED_ON() { PORTB |= (1<<ISP_LED); };
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#define ISP_LED_OFF() { PORTB &= ~(1<<ISP_LED); };
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#define ISP_CHECK() !(PINB & (1<<RESET_IN))
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/* DL1414 display */
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#define USE_DISPLAY 1
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#define DISP_WR PORTC2 /* low active */
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#define DISP_A0 PORTC0
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#define DISP_A1 PORTC1
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#define DISP_D0 PORTC3
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#define DISP_D1 PORTD2
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#define DISP_D2 PORTD3
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#define DISP_D3 PORTD4
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#define DISP_D4 PORTD5
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#define DISP_D5 PORTD6
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#define DISP_D6 PORTD7
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#define TIMER_DIVISOR 1024
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#define TIMER_INIT() { /* timer0, FCPU/1024, overflow interrupt */ \
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TCCR0B = (1<<CS02) | (1<<CS00); \
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TIMSK0 = (1<<TOIE0); \
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}
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#define GPIO_INIT() { /* ISP_RESET and ISP_LED are outputs, pullup RESET_IN and SlaveSelect */ \
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PORTB = (1<<ISP_RESET) | (1<<RESET_IN) | (1<<PORTB2); \
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DDRB = (1<<ISP_RESET) | (1<<ISP_LED); \
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\
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/* all DISP_* pins are outputs, DISP_WR is high */ \
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DDRC = (1<<DISP_WR) | (1<<DISP_A0) | (1<<DISP_A1) | (1<<DISP_D0); \
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PORTC = (1<<DISP_WR); \
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DDRD = 0xFC; \
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};
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/* *********************************************************************** */
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#else
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#error "unknown CONFIG"
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#endif
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/* *********************************************************************** */
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#endif /* TARGET_H_ */ |