cleanup .s files
This commit is contained in:
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1047706197
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2b2dba7316
485
at91_init0.s
485
at91_init0.s
@ -1,244 +1,241 @@
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/***************************************************************************
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/***************************************************************************
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* Copyright (C) 01/2008 by Olaf Rempel *
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* Copyright (C) 01/2008 by Olaf Rempel *
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* razzor@kopf-tisch.de *
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* razzor@kopf-tisch.de *
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* *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; version 2 of the License *
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* the Free Software Foundation; version 2 of the License *
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* *
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* *
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* This program is distributed in the hope that it will be useful, *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* GNU General Public License for more details. *
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* *
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* *
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* You should have received a copy of the GNU General Public License *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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***************************************************************************/
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.equ AIC_IVR, (256)
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.equ AIC_IVR, (256)
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.equ AIC_FVR, (260)
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.equ AIC_FVR, (260)
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.equ AIC_EOICR, (304)
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.equ AIC_EOICR, (304)
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.equ AT91C_BASE_AIC, (0xFFFFF000)
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.equ AT91C_BASE_AIC, (0xFFFFF000)
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.equ IRQ_Stack_Size, (3 * 8 * 4)
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.equ IRQ_Stack_Size, (3 * 8 * 4)
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.equ FIQ_Stack_Size, (3 * 8 * 4)
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.equ FIQ_Stack_Size, (3 * 8 * 4)
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.equ ABT_Stack_Size, 192
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.equ ABT_Stack_Size, 192
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.equ ARM_MODE_FIQ, 0x11
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.equ ARM_MODE_FIQ, 0x11
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.equ ARM_MODE_IRQ, 0x12
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.equ ARM_MODE_IRQ, 0x12
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.equ ARM_MODE_SVC, 0x13
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.equ ARM_MODE_SVC, 0x13
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.equ ARM_MODE_ABT, 0x17
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.equ ARM_MODE_ABT, 0x17
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.equ I_BIT, 0x80
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.equ I_BIT, 0x80
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.equ F_BIT, 0x40
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.equ F_BIT, 0x40
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.section .text
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.section .text
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.global _start
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.global _start
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.func _start
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.func _start
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_start: ldr pc, [pc, #24] /* 0x00 Reset handler */
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_start: ldr pc, [pc, #24] /* 0x00 Reset handler */
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undefvec: ldr pc, [pc, #24] /* 0x04 Undefined Instruction */
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undefvec: ldr pc, [pc, #24] /* 0x04 Undefined Instruction */
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swivec: ldr pc, [pc, #24] /* 0x08 Software Interrupt */
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swivec: ldr pc, [pc, #24] /* 0x08 Software Interrupt */
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pabtvec: ldr pc, [pc, #24] /* 0x0C Prefetch Abort */
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pabtvec: ldr pc, [pc, #24] /* 0x0C Prefetch Abort */
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dabtvec: ldr pc, [pc, #24] /* 0x10 Data Abort */
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dabtvec: ldr pc, [pc, #24] /* 0x10 Data Abort */
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rsvdvec: ldr pc, [pc, #24] /* 0x14 reserved */
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rsvdvec: ldr pc, [pc, #24] /* 0x14 reserved */
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irqvec: ldr pc, [pc, #24] /* 0x18 IRQ */
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irqvec: ldr pc, [pc, #24] /* 0x18 IRQ */
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fiqvec: ldr pc, [pc, #24] /* 0x1c FIQ */
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fiqvec: ldr pc, [pc, #24] /* 0x1c FIQ */
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/* 0x80000000 will result in Prefetch Abort */
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/* 0x80000000 will result in Prefetch Abort */
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.word InitReset
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.word InitReset
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.word 0x80000000
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.word 0x80000000
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.word 0x80000000
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.word 0x80000000
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.word ABT_Handler_Entry
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.word ABT_Handler_Entry
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.word ABT_Handler_Entry
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.word ABT_Handler_Entry
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.word 0x80000000
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.word 0x80000000
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.word IRQ_Handler_Entry
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.word IRQ_Handler_Entry
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.word FIQ_Handler_Entry
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.word FIQ_Handler_Entry
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.endfunc
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.endfunc
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.global InitReset
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.global InitReset
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.func InitReset
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.func InitReset
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.extern at91_init1
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InitReset:
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InitReset:
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.extern at91_init1
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/* Call Low level init function */
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/* Call Low level init function */
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ldr sp, =__stack_top__
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ldr sp,=__stack_top__
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ldr r0, =at91_init1
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ldr r0,=at91_init1
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mov lr, pc
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mov lr, pc
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bx r0
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bx r0
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mov r0, sp
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mov r0, sp
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/* Setup FIQ Mode Stack */
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/* Setup FIQ Mode Stack */
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msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
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msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
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mov sp, r0
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mov sp, r0
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sub r0, r0, #FIQ_Stack_Size
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sub r0, r0, #FIQ_Stack_Size
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/* store AIC Base in ARM_MODE_FIQ:r8 for faster access */
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/* store AIC Base in ARM_MODE_FIQ:r8 for faster access */
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ldr r8, =AT91C_BASE_AIC
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ldr r8, =AT91C_BASE_AIC
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/* Setup IRQ Mode Stack */
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/* Setup IRQ Mode Stack */
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msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
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msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
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mov sp, r0
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mov sp, r0
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sub r0, r0, #IRQ_Stack_Size
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sub r0, r0, #IRQ_Stack_Size
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/* Setup Abort Mode Stack */
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/* Setup Abort Mode Stack */
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msr CPSR_c, #ARM_MODE_ABT | I_BIT | F_BIT
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msr CPSR_c, #ARM_MODE_ABT | I_BIT | F_BIT
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mov sp, r0
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mov sp, r0
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sub r0, r0, #ABT_Stack_Size
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sub r0, r0, #ABT_Stack_Size
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/* Setup Supervisor Mode Stack (IRQ & NMI enabled) */
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/* Setup Supervisor Mode Stack (IRQ & NMI enabled) */
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msr CPSR_c, #ARM_MODE_SVC
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msr CPSR_c, #ARM_MODE_SVC
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mov sp, r0
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mov sp, r0
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/* Relocate .data section */
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/* Relocate .data section */
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ldr r1, =__text_end__
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ldr r1, =__text_end__
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ldr r2, =__data_start__
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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ldr r3, =__data_end__
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LoopRel: cmp r2, r3
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LoopRel: cmp r2, r3
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ldrlo r0, [r1], #4
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ldrlo r0, [r1], #4
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strlo r0, [r2], #4
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strlo r0, [r2], #4
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blo LoopRel
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blo LoopRel
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/* Clear .bss section */
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/* Clear .bss section */
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mov r0, #0
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mov r0, #0
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ldr r1, =__bss_start__
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ldr r1, =__bss_start__
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ldr r2, =__bss_end__
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ldr r2, =__bss_end__
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LoopZI: cmp r1, r2
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LoopZI: cmp r1, r2
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strlo r0, [r1], #4
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strlo r0, [r1], #4
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BLO LoopZI
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BLO LoopZI
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/* Start main() */
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/* Start main() */
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ldr lr, =exit
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ldr lr,=exit
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ldr r0, =main
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ldr r0,=main
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bx r0
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bx r0
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.endfunc
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.endfunc
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.global exit
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.global exit
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.func exit
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.func exit
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/* exit dummy for newlib */
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/* exit dummy for newlib */
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exit: b .
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exit: b .
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.endfunc
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.endfunc
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.global ABT_Handler_Entry
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.global ABT_Handler_Entry
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.func ABT_Handler_Entry
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.func ABT_Handler_Entry
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ABT_Handler_Entry:
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ABT_Handler_Entry:
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/* disable interrupts (F_BIT not set on entry) */
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/* disable interrupts (F_BIT not set on entry) */
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msr CPSR_c, #ARM_MODE_ABT | I_BIT | F_BIT
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msr CPSR_c, #ARM_MODE_ABT | I_BIT | F_BIT
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/* store all registers */
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/* store all registers */
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stmfd sp!, { r0-r12 }
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stmfd sp!, { r0-r12 }
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/* saved cpsr (from aborted mode) */
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/* saved cpsr (from aborted mode) */
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mrs r0, SPSR
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mrs r0, SPSR
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/* address of abort (pc) */
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/* address of abort (pc) */
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mov r3, lr
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mov r3, lr
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/* enter previous mode and get lr(r14), sp(r13) */
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/* enter previous mode and get lr(r14), sp(r13) */
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/* TODO: interrupts might be enabled? */
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/* TODO: interrupts might be enabled? */
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/* TODO: thumb mode enabled? */
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/* TODO: thumb mode enabled? */
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msr CPSR_c, r0
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msr CPSR_c, r0
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mov r1, sp
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mov r1, sp
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mov r2, lr
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mov r2, lr
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/* return to abort mode */
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/* return to abort mode */
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msr CPSR_c, #ARM_MODE_ABT | I_BIT | F_BIT
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msr CPSR_c, #ARM_MODE_ABT | I_BIT | F_BIT
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/* store remaining registers (r1-r3 == r13-r15) */
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/* store remaining registers (r1-r3 == r13-r15) */
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stmfd sp!, { r1-r3 }
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stmfd sp!, { r1-r3 }
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mov r1, sp
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mov r1, sp
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/* execute C Handler (cpsr, registers) */
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/* execute C Handler (cpsr, registers) */
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ldr r5, =at91_abt_handler
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ldr r5,=at91_abt_handler
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mov lr, pc
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mov lr, pc
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bx r5
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bx r5
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b .
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b .
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.endfunc
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.endfunc
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.global FIQ_Handler_Entry
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.global FIQ_Handler_Entry
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.func FIQ_Handler_Entry
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.func FIQ_Handler_Entry
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FIQ_Handler_Entry:
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FIQ_Handler_Entry:
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/* Save r0 to ARM_MODE_FIQ:r9 */
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/* Save r0 to ARM_MODE_FIQ:r9 */
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mov r9, r0
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mov r9,r0
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/* get FIQ Vector from AIC and thus clear FIQ */
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/* get FIQ Vector from AIC and thus clear FIQ */
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ldr r0, [r8, #AIC_FVR]
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ldr r0 , [r8, #AIC_FVR]
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/* Switch to ARM_MODE_SVC and save registers there */
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/* Switch to ARM_MODE_SVC and save registers there */
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msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT
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msr CPSR_c,#ARM_MODE_SVC | I_BIT | F_BIT
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stmfd sp!, { r1-r3, r12, lr }
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stmfd sp!, { r1-r3, r12, lr}
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/* execute FIQ in SVC_MODE */
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/* execute FIQ in SVC_MODE */
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mov r14, pc
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mov r14, pc
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bx r0
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bx r0
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/* restore registers and switch back to ARM_MODE_FIQ */
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/* restore registers and switch back to ARM_MODE_FIQ */
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ldmia sp!, { r1-r3, r12, lr }
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ldmia sp!, { r1-r3, r12, lr}
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msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
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msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
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/* restore the ARM_MODE_SVC:r0 */
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/* restore the ARM_MODE_SVC:r0 */
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mov r0, r9
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mov r0,r9
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/* restore PC using the LR_fiq directly */
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/* restore PC using the LR_fiq directly */
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subs pc, lr, #4
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subs pc,lr,#4
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.endfunc
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.endfunc
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.global IRQ_Handler_Entry
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.func IRQ_Handler_Entry
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IRQ_Handler_Entry:
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.global IRQ_Handler_Entry
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/* Manage Exception Entry */
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.func IRQ_Handler_Entry
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/* Adjust and save LR_irq in IRQ stack */
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IRQ_Handler_Entry:
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sub lr, lr, #4
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/*- Manage Exception Entry */
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stmfd sp!, { lr }
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/*- Adjust and save LR_irq in IRQ stack */
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sub lr, lr, #4
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/* Save SPSR need to be saved for nested interrupt */
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stmfd sp!, {lr}
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mrs r14, SPSR
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stmfd sp!, { r14 }
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/*- Save SPSR need to be saved for nested interrupt */
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mrs r14, SPSR
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/* Save and r0 in IRQ stack */
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stmfd sp!, {r14}
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stmfd sp!, { r0 }
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/*- Save and r0 in IRQ stack */
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/* Write in the IVR to support Protect Mode */
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stmfd sp!, {r0}
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/* No effect in Normal Mode */
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/* De-assert the NIRQ and clear the source in Protect Mode */
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/*- Write in the IVR to support Protect Mode */
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ldr r14, =AT91C_BASE_AIC
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/*- No effect in Normal Mode */
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ldr r0, [r14, #AIC_IVR]
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/*- De-assert the NIRQ and clear the source in Protect Mode */
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str r14, [r14, #AIC_IVR]
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ldr r14, =AT91C_BASE_AIC
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ldr r0 , [r14, #AIC_IVR]
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/* Enable Interrupt and Switch in Supervisor Mode */
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str r14, [r14, #AIC_IVR]
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msr CPSR_c, #ARM_MODE_SVC
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/*- Enable Interrupt and Switch in Supervisor Mode */
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/* Save scratch/used registers and LR in User Stack */
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msr CPSR_c, #ARM_MODE_SVC
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stmfd sp!, { r1-r3, r12, r14 }
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/*- Save scratch/used registers and LR in User Stack */
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/* Branch to the routine pointed by the AIC_IVR */
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stmfd sp!, { r1-r3, r12, r14}
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mov r14, pc
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bx r0
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/*- Branch to the routine pointed by the AIC_IVR */
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mov r14, pc
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/* Restore scratch/used registers and LR from User Stack */
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bx r0
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ldmia sp!, { r1-r3, r12, r14 }
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/*- Restore scratch/used registers and LR from User Stack*/
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ldmia sp!, { r1-r3, r12, r14}
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/* Disable Interrupt and switch back in IRQ mode */
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msr CPSR_c, #ARM_MODE_IRQ | I_BIT
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/*- Disable Interrupt and switch back in IRQ mode */
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msr CPSR_c, #ARM_MODE_IRQ | I_BIT
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/* Mark the End of Interrupt on the AIC */
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ldr r14, =AT91C_BASE_AIC
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/*- Mark the End of Interrupt on the AIC */
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str r14, [r14, #AIC_EOICR]
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ldr r14, =AT91C_BASE_AIC
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str r14, [r14, #AIC_EOICR]
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/* Restore SPSR_irq and r0 from IRQ stack */
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ldmia sp!, { r0 }
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/*- Restore SPSR_irq and r0 from IRQ stack */
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ldmia sp!, {r0}
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/* Restore SPSR_irq and r0 from IRQ stack */
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ldmia sp!, { r14 }
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/*- Restore SPSR_irq and r0 from IRQ stack */
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msr SPSR_cxsf, r14
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ldmia sp!, {r14}
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msr SPSR_cxsf, r14
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/* Restore adjusted LR_irq from IRQ stack directly in the PC */
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ldmia sp!, { pc }^
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/*- Restore adjusted LR_irq from IRQ stack directly in the PC */
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ldmia sp!, {pc}^
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.endfunc
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.end
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.endfunc
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.end
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