move exception handler into C-files
This commit is contained in:
parent
60cccae208
commit
773cc44a09
138
at91_init0.s
138
at91_init0.s
@ -16,13 +16,10 @@
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* Free Software Foundation, Inc., *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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***************************************************************************/
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.equ AIC_IVR, (256)
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.equ AIC_FVR, (260)
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.equ AIC_EOICR, (304)
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.equ AT91C_BASE_AIC, (0xFFFFF000)
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.equ AT91C_BASE_AIC, (0xFFFFF000)
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.equ IRQ_Stack_Size, (3 * 8 * 4)
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.equ IRQ_Stack_Size, (3 * 8 * 4)
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.equ FIQ_Stack_Size, (3 * 8 * 4)
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.equ FIQ_Stack_Size, (0 * 8 * 4)
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.equ ABT_Stack_Size, 192
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.equ ABT_Stack_Size, 192
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.equ ARM_MODE_FIQ, 0x11
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.equ ARM_MODE_FIQ, 0x11
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@ -46,15 +43,19 @@ rsvdvec: ldr pc, [pc, #24] /* 0x14 reserved */
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irqvec: ldr pc, [pc, #24] /* 0x18 IRQ */
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irqvec: ldr pc, [pc, #24] /* 0x18 IRQ */
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fiqvec: ldr pc, [pc, #24] /* 0x1c FIQ */
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fiqvec: ldr pc, [pc, #24] /* 0x1c FIQ */
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.extern ABT_Handler
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.extern IRQ_Handler
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.extern FIQ_Handler
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/* 0x80000000 will result in Prefetch Abort */
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/* 0x80000000 will result in Prefetch Abort */
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.word InitReset
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.word InitReset
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.word 0x80000000
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.word 0x80000000
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.word 0x80000000
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.word 0x80000000
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.word ABT_Handler_Entry
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.word ABT_Handler
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.word ABT_Handler_Entry
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.word ABT_Handler
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.word 0x80000000
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.word 0x80000000
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.word IRQ_Handler_Entry
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.word IRQ_Handler
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.word FIQ_Handler_Entry
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.word FIQ_Handler
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.endfunc
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.endfunc
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@ -74,7 +75,7 @@ InitReset:
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mov sp, r0
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mov sp, r0
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sub r0, r0, #FIQ_Stack_Size
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sub r0, r0, #FIQ_Stack_Size
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/* store AIC Base in ARM_MODE_FIQ:r8 for faster access */
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/* store AIC Base in r8_fiq for faster access */
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ldr r8, =AT91C_BASE_AIC
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ldr r8, =AT91C_BASE_AIC
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/* Setup IRQ Mode Stack */
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/* Setup IRQ Mode Stack */
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@ -120,122 +121,3 @@ LoopZI: cmp r1, r2
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/* exit dummy for newlib */
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/* exit dummy for newlib */
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exit: b .
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exit: b .
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.endfunc
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.endfunc
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.global ABT_Handler_Entry
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.func ABT_Handler_Entry
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ABT_Handler_Entry:
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/* disable interrupts (F_BIT not set on entry) */
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msr CPSR_c, #ARM_MODE_ABT | I_BIT | F_BIT
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/* store all registers */
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stmfd sp!, { r0-r12 }
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/* saved cpsr (from aborted mode) */
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mrs r0, SPSR
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/* address of abort (pc) */
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mov r3, lr
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/* enter previous mode and get lr(r14), sp(r13) */
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/* TODO: interrupts might be enabled? */
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/* TODO: thumb mode enabled? */
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msr CPSR_c, r0
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mov r1, sp
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mov r2, lr
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/* return to abort mode */
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msr CPSR_c, #ARM_MODE_ABT | I_BIT | F_BIT
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/* store remaining registers (r1-r3 == r13-r15) */
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stmfd sp!, { r1-r3 }
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mov r1, sp
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/* execute C Handler (cpsr, registers) */
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ldr r5, =at91_abt_handler
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mov lr, pc
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bx r5
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b .
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.endfunc
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.global FIQ_Handler_Entry
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.func FIQ_Handler_Entry
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FIQ_Handler_Entry:
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/* Save r0 to ARM_MODE_FIQ:r9 */
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mov r9, r0
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/* get FIQ Vector from AIC and thus clear FIQ */
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ldr r0, [r8, #AIC_FVR]
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/* Switch to ARM_MODE_SVC and save registers there */
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msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT
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stmfd sp!, { r1-r3, r12, lr }
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/* execute FIQ in SVC_MODE */
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mov r14, pc
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bx r0
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/* restore registers and switch back to ARM_MODE_FIQ */
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ldmia sp!, { r1-r3, r12, lr }
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msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
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/* restore the ARM_MODE_SVC:r0 */
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mov r0, r9
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/* restore PC using the LR_fiq directly */
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subs pc, lr, #4
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.endfunc
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.global IRQ_Handler_Entry
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.func IRQ_Handler_Entry
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IRQ_Handler_Entry:
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/* Manage Exception Entry */
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/* Adjust and save LR_irq in IRQ stack */
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sub lr, lr, #4
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stmfd sp!, { lr }
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/* Save SPSR need to be saved for nested interrupt */
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mrs r14, SPSR
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stmfd sp!, { r14 }
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/* Save and r0 in IRQ stack */
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stmfd sp!, { r0 }
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/* Write in the IVR to support Protect Mode */
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/* No effect in Normal Mode */
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/* De-assert the NIRQ and clear the source in Protect Mode */
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ldr r14, =AT91C_BASE_AIC
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ldr r0, [r14, #AIC_IVR]
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str r14, [r14, #AIC_IVR]
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/* Enable Interrupt and Switch in Supervisor Mode */
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msr CPSR_c, #ARM_MODE_SVC
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/* Save scratch/used registers and LR in User Stack */
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stmfd sp!, { r1-r3, r12, r14 }
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/* Branch to the routine pointed by the AIC_IVR */
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mov r14, pc
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bx r0
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/* Restore scratch/used registers and LR from User Stack */
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ldmia sp!, { r1-r3, r12, r14 }
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/* Disable Interrupt and switch back in IRQ mode */
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msr CPSR_c, #ARM_MODE_IRQ | I_BIT
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/* Mark the End of Interrupt on the AIC */
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ldr r14, =AT91C_BASE_AIC
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str r14, [r14, #AIC_EOICR]
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/* Restore SPSR_irq and r0 from IRQ stack */
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ldmia sp!, { r0 }
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/* Restore SPSR_irq and r0 from IRQ stack */
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ldmia sp!, { r14 }
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msr SPSR_cxsf, r14
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/* Restore adjusted LR_irq from IRQ stack directly in the PC */
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ldmia sp!, { pc }^
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.endfunc
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.end
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93
at91_init1.c
93
at91_init1.c
@ -79,3 +79,96 @@ void at91_init1(void)
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}
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}
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aic->AIC_SPU = (uint32_t)empty_isr;
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aic->AIC_SPU = (uint32_t)empty_isr;
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}
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}
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__attribute__((naked)) void IRQ_Handler(void)
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{
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asm volatile (
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".equ ARM_MODE_IRQ, 0x12 \n\t"
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".equ ARM_MODE_SVC, 0x13 \n\t"
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".equ I_BIT, 0x80 \n\t"
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".equ AIC_IVR, (256) \n\t"
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".equ AIC_EOICR, (304) \n\t"
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".equ AT91C_BASE_AIC, (0xFFFFF000) \n\t"
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/* Adjust and save lr_irq on IRQ stack */
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"sub lr, lr, #4 \n\t"
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"stmfd sp!, { lr } \n\t"
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/* Save SPSR (for nested interrupts) */
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"mrs r14, SPSR \n\t"
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"stmfd sp!, { r14 } \n\t"
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/* Save r0 on IRQ stack */
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"stmfd sp!, { r0 } \n\t"
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/* Write in the IVR to support Protect Mode */
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"ldr r14, =AT91C_BASE_AIC \n\t"
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"ldr r0, [r14, #AIC_IVR] \n\t"
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"str r14, [r14, #AIC_IVR] \n\t"
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/* Enable Interrupt and switch to SVC mode */
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"msr CPSR_c, #ARM_MODE_SVC \n\t"
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/* Save scratch/used registers and lr on SVC Stack */
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"stmfd sp!, { r1-r3, r12, r14 } \n\t"
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/* Branch to the routine pointed by the AIC_IVR */
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"mov r14, pc \n\t"
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"bx r0 \n\t"
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/* Restore scratch/used registers and lr from SVC Stack */
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"ldmia sp!, { r1-r3, r12, r14 } \n\t"
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/* Disable Interrupt and switch back to IRQ mode */
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"msr CPSR_c, #ARM_MODE_IRQ | I_BIT \n\t"
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/* Mark the End of Interrupt on the AIC */
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"ldr r14, =AT91C_BASE_AIC \n\t"
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"str r14, [r14, #AIC_EOICR] \n\t"
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/* Restore SPSR_irq and r0 from IRQ stack */
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"ldmia sp!, { r0 } \n\t"
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"ldmia sp!, { r14 } \n\t"
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"msr SPSR_cxsf, r14 \n\t"
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/* Restore adjusted lr_irq from IRQ stack */
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"ldmia sp!, { pc }^ \n\t"
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);
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}
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__attribute__((naked)) void FIQ_Handler(void)
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{
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asm volatile (
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".equ ARM_MODE_FIQ, 0x11 \n\t"
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".equ ARM_MODE_SVC, 0x13 \n\t"
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".equ I_BIT, 0x80 \n\t"
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".equ F_BIT, 0x40 \n\t"
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".equ AIC_FVR, (260) \n\t"
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/* Save r0 to r9_fiq */
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"mov r9, r0 \n\t"
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/* get FIQ Vector from AIC and thus clear FIQ */
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"ldr r0, [r8, #AIC_FVR] \n\t"
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/* Switch to SVC and save registers there */
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"msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT \n\t"
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"stmfd sp!, { r1-r3, r12, lr } \n\t"
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/* execute FIQ in SVC_MODE */
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"mov r14, pc \n\t"
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"bx r0 \n\t"
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/* restore registers and switch back to FIQ */
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"ldmia sp!, { r1-r3, r12, lr } \n\t"
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"msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT \n\t"
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/* restore the r0 from r9_fiq */
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"mov r0, r9 \n\t"
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/* restore PC using the lr_fiq directly */
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"subs pc, lr, #4 \n\t"
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);
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}
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@ -59,8 +59,8 @@ ARM7TDMI 32bit Undefined Address Instruction Fetch Abort
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--- Registerdump (cpsr:0xa0000013 - SVC):
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--- Registerdump (cpsr:0xa0000013 - SVC):
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r0:0x00000002 r1:0x0000000c r2:0x00200038 r3:0x80000000
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r0:0x00000002 r1:0x0000000c r2:0x00200038 r3:0x80000000
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r4:0x0020fffc r5:0x00101788 r6:0x00000180 r7:0x41000000
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r4:0x0020fffc r5:0x00101788 r6:0x00000180 r7:0x41000000
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r8:0x00008400 r9:0x00100004 r10:0x03000294 fp:0x0020fe84
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r8:0x00008400 r9:0x00100004 sl:0x03000294 fp:0x0020fe84
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r12:0x0020fe10 sp:0x0020fe70 lr:0x00102174 pc:0x80000004
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ip:0x0020fe10 sp:0x0020fe70 lr:0x00102174 pc:0x80000004
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--- Stackdump:
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--- Stackdump:
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0x0020fe70: 0x0020fe7c 0x00101648 0x001015a8 0x0020feaf
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0x0020fe70: 0x0020fe7c 0x00101648 0x001015a8 0x0020feaf
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0x0020fe80: 0x0020fec0 0x0020fe90 0x00101780 0x00101620
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0x0020fe80: 0x0020fec0 0x0020fe90 0x00101780 0x00101620
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@ -142,9 +142,9 @@ void at91_abt_handler(uint32_t cpsr, uint32_t *registers)
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dbgu_hexvar(" r7:", registers[10]);
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dbgu_hexvar(" r7:", registers[10]);
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dbgu_hexvar("\n r8:", registers[11]);
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dbgu_hexvar("\n r8:", registers[11]);
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dbgu_hexvar(" r9:", registers[12]);
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dbgu_hexvar(" r9:", registers[12]);
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dbgu_hexvar(" r10:", registers[13]);
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dbgu_hexvar(" sl:", registers[13]);
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dbgu_hexvar(" fp:", registers[14]);
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dbgu_hexvar(" fp:", registers[14]);
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dbgu_hexvar("\nr12:", registers[15]);
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dbgu_hexvar("\n ip:", registers[15]);
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dbgu_hexvar(" sp:", registers[0]);
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dbgu_hexvar(" sp:", registers[0]);
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dbgu_hexvar(" lr:", registers[1]);
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dbgu_hexvar(" lr:", registers[1]);
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dbgu_hexvar(" pc:", registers[2]);
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dbgu_hexvar(" pc:", registers[2]);
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@ -160,3 +160,44 @@ void at91_abt_handler(uint32_t cpsr, uint32_t *registers)
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}
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}
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dbgu_putchar('\n');
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dbgu_putchar('\n');
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}
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}
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__attribute__((naked)) void ABT_Handler(void)
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{
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asm volatile (
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".equ ARM_MODE_ABT, 0x17 \n\t"
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".equ I_BIT, 0x80 \n\t"
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".equ F_BIT, 0x40 \n\t"
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/* disable interrupts (F_BIT not set on entry) */
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"msr CPSR_c, #ARM_MODE_ABT | I_BIT | F_BIT \n\t"
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/* store all registers */
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"stmfd sp!, { r0-r12 } \n\t"
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/* saved cpsr (from aborted mode) */
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"mrs r0, SPSR \n\t"
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/* address of abort (pc) */
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"mov r3, lr \n\t"
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/* enter previous mode and get lr(r14), sp(r13) */
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/* TODO: interrupts might be enabled? */
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/* TODO: thumb mode enabled? */
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"msr CPSR_c, r0 \n\t"
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"mov r1, sp \n\t"
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"mov r2, lr \n\t"
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/* return to abort mode */
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"msr CPSR_c, #ARM_MODE_ABT | I_BIT | F_BIT \n\t"
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/* store remaining registers (r1-r3 == r13-r15) */
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"stmfd sp!, { r1-r3 } \n\t"
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"mov r1, sp \n\t"
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/* execute C Handler (cpsr, registers) */
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"ldr r5, =at91_abt_handler \n\t"
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"mov lr, pc \n\t"
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"bx r5 \n\t"
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"b . \n\t"
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);
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}
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