/*************************************************************************** * sam7fc - stack/bss/data init * * * * Copyright (C) 01/2008 by Olaf Rempel * * razzor@kopf-tisch.de * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; version 2 of the License * * * * This program is distributed in the hope that it will be useful, * * but WITHOUT ANY WARRANTY; without even the implied warranty of * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * * along with this program; if not, write to the * * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ .equ AT91C_BASE_AIC, (0xFFFFF000) .equ IRQ_Stack_Size, (3 * 8 * 4) .equ FIQ_Stack_Size, (0 * 8 * 4) .equ ABT_Stack_Size, 192 .equ ARM_MODE_FIQ, 0x11 .equ ARM_MODE_IRQ, 0x12 .equ ARM_MODE_SVC, 0x13 .equ ARM_MODE_ABT, 0x17 .equ I_BIT, 0x80 .equ F_BIT, 0x40 .section .text .global _start .func _start _start: ldr pc, [pc, #24] /* 0x00 Reset handler */ undefvec: ldr pc, [pc, #24] /* 0x04 Undefined Instruction */ swivec: ldr pc, [pc, #24] /* 0x08 Software Interrupt */ pabtvec: ldr pc, [pc, #24] /* 0x0C Prefetch Abort */ dabtvec: ldr pc, [pc, #24] /* 0x10 Data Abort */ rsvdvec: ldr pc, [pc, #24] /* 0x14 reserved */ irqvec: ldr pc, [pc, #24] /* 0x18 IRQ */ fiqvec: ldr pc, [pc, #24] /* 0x1c FIQ */ .extern ABT_Handler .extern IRQ_Handler .extern FIQ_Handler /* 0x80000000 will result in Prefetch Abort */ .word InitReset .word 0x80000000 .word 0x80000000 .word ABT_Handler .word ABT_Handler .word 0x80000000 .word IRQ_Handler .word FIQ_Handler .endfunc .global InitReset .func InitReset .extern at91_init1 InitReset: /* Call Low level init function */ ldr sp, =__stack_top__ ldr r0, =at91_init1 mov lr, pc bx r0 mov r0, sp /* Setup FIQ Mode Stack */ msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT mov sp, r0 sub r0, r0, #FIQ_Stack_Size /* store AIC Base in r8_fiq for faster access */ ldr r8, =AT91C_BASE_AIC /* Setup IRQ Mode Stack */ msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT mov sp, r0 sub r0, r0, #IRQ_Stack_Size /* Setup Abort Mode Stack */ msr CPSR_c, #ARM_MODE_ABT | I_BIT | F_BIT mov sp, r0 sub r0, r0, #ABT_Stack_Size /* Setup Supervisor Mode Stack (IRQ & NMI enabled) */ msr CPSR_c, #ARM_MODE_SVC mov sp, r0 /* Relocate .data section */ ldr r1, =__text_end__ ldr r2, =__data_start__ ldr r3, =__data_end__ LoopRel: cmp r2, r3 ldrlo r0, [r1], #4 strlo r0, [r2], #4 blo LoopRel /* Clear .bss section */ mov r0, #0 ldr r1, =__bss_start__ ldr r2, =__bss_end__ LoopZI: cmp r1, r2 strlo r0, [r1], #4 BLO LoopZI /* Start main() */ ldr lr, =exit ldr r0, =main bx r0 .endfunc .global exit .func exit /* exit dummy for newlib */ exit: b . .endfunc