205 lines
6.1 KiB
C
205 lines
6.1 KiB
C
/***************************************************************************
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* sam7fc - Abort Handler with Register/Stackdump *
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* *
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* Copyright (C) 01/2008 by Olaf Rempel *
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* razzor@kopf-tisch.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; version 2 of the License *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#include <stdint.h>
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#include "AT91SAM7S256.h"
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#include "board.h"
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static void dbgu_putchar(char c)
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{
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while (!(*AT91C_DBGU_CSR & AT91C_US_TXEMPTY));
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*AT91C_DBGU_THR = c;
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if (c == '\n') {
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while (!(*AT91C_DBGU_CSR & AT91C_US_TXEMPTY));
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*AT91C_DBGU_THR = '\r';
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}
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}
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static void dbgu_puts(const char *p)
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{
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while (*p != '\0')
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dbgu_putchar(*p++);
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}
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static void dbgu_hexvar(const char *name, uint32_t var)
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{
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dbgu_puts(name);
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char buf[11];
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buf[0] = '0';
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buf[1] = 'x';
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uint32_t i;
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for (i = 9; i > 1; i--) {
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buf[i] = (var & 0x0F);
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buf[i] += (buf[i] < 0xa) ? '0' : ('a' - 0x0a);
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var >>= 4;
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}
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buf[10] = '\0';
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dbgu_puts(buf);
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}
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/*
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ARM7TDMI 32bit Undefined Address Instruction Fetch Abort
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(ASR:0x02020a01 AASR:0x80000008)
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--- Registerdump (cpsr:0xa0000013 - SVC):
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r0:0x00000002 r1:0x0000000c r2:0x00200038 r3:0x80000000
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r4:0x0020fffc r5:0x00101788 r6:0x00000180 r7:0x41000000
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r8:0x00008400 r9:0x00100004 sl:0x03000294 fp:0x0020fe84
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ip:0x0020fe10 sp:0x0020fe70 lr:0x00102174 pc:0x80000004
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--- Stackdump:
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0x0020fe70: 0x0020fe7c 0x00101648 0x001015a8 0x0020feaf
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0x0020fe80: 0x0020fec0 0x0020fe90 0x00101780 0x00101620
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0x0020fe90: 0x00000002 0x00000000 0x00000030 0x00000000
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0x0020fea0: 0x001029a8 0x307830b0 0x33383730 0x00303337
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*/
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void at91_abt_handler(uint32_t cpsr, uint32_t *registers)
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{
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/* enable Debug Port with 115200 Baud (+0.16%) */
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AT91S_DBGU *dbgu = AT91C_BASE_DBGU;
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dbgu->DBGU_BRGR = BAUD_TO_DIV(115200);
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dbgu->DBGU_MR = AT91C_US_PAR_NONE | AT91C_US_CHMODE_NORMAL;
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dbgu->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN | AT91C_US_RSTSTA;
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/* switch pins to UART */
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*AT91C_PIOA_PDR = AT91C_PA9_DRXD | AT91C_PA10_DTXD;
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AT91_REG asr = *AT91C_MC_ASR;
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if (asr & AT91C_MC_MST0)
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dbgu_puts("PDC ");
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else if (asr & AT91C_MC_MST1)
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dbgu_puts("ARM7TDMI ");
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switch (asr & AT91C_MC_ABTSZ) {
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case AT91C_MC_ABTSZ_BYTE:
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dbgu_puts("8bit ");
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break;
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case AT91C_MC_ABTSZ_HWORD:
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dbgu_puts("16bit ");
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break;
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case AT91C_MC_ABTSZ_WORD:
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dbgu_puts("32bit ");
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break;
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}
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if (asr & AT91C_MC_UNDADD)
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dbgu_puts("Undefined Address ");
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else if (asr & AT91C_MC_MISADD)
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dbgu_puts("Misaliged Address ");
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switch (asr & AT91C_MC_ABTTYP) {
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case AT91C_MC_ABTTYP_DATAR:
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dbgu_puts("Data Read ");
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break;
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case AT91C_MC_ABTTYP_DATAW:
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dbgu_puts("Data Write ");
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break;
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case AT91C_MC_ABTTYP_FETCH:
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dbgu_puts("Prefetch ");
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break;
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}
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dbgu_hexvar("Abort\n(ASR:", asr);
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dbgu_hexvar(" AASR:", *AT91C_MC_AASR);
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dbgu_puts(")\n");
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dbgu_hexvar("--- Registerdump (cpsr:", cpsr);
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dbgu_puts(" - ");
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switch (cpsr & 0x1F) {
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case 0x10: dbgu_puts("USR"); break;
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case 0x11: dbgu_puts("FIQ"); break;
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case 0x12: dbgu_puts("IRQ"); break;
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case 0x13: dbgu_puts("SVC"); break;
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case 0x17: dbgu_puts("ABT"); break;
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case 0x1B: dbgu_puts("UND"); break;
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case 0x1F: dbgu_puts("SYS"); break;
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}
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dbgu_hexvar("):\n r0:", registers[3]);
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dbgu_hexvar(" r1:", registers[4]);
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dbgu_hexvar(" r2:", registers[5]);
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dbgu_hexvar(" r3:", registers[6]);
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dbgu_hexvar("\n r4:", registers[7]);
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dbgu_hexvar(" r5:", registers[8]);
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dbgu_hexvar(" r6:", registers[9]);
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dbgu_hexvar(" r7:", registers[10]);
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dbgu_hexvar("\n r8:", registers[11]);
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dbgu_hexvar(" r9:", registers[12]);
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dbgu_hexvar(" sl:", registers[13]);
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dbgu_hexvar(" fp:", registers[14]);
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dbgu_hexvar("\n ip:", registers[15]);
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dbgu_hexvar(" sp:", registers[0]);
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dbgu_hexvar(" lr:", registers[1]);
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dbgu_hexvar(" pc:", registers[2]);
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dbgu_puts("\n--- Stackdump:");
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uint32_t *val = (uint32_t *)(registers[0] & ~0x0F);
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for ( ; val < (uint32_t *)(registers[0] & ~0x0F) +16; val++) {
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if (!((uint32_t)val & 0x0F)) {
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dbgu_hexvar("\n", (uint32_t)val);
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dbgu_putchar(':');
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}
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dbgu_hexvar(" ", *val);
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}
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dbgu_putchar('\n');
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}
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__attribute__((naked)) void ABT_Handler(void)
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{
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asm volatile (
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".equ ARM_MODE_ABT, 0x17 \n\t"
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".equ I_BIT, 0x80 \n\t"
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".equ F_BIT, 0x40 \n\t"
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/* disable interrupts (F_BIT not set on entry) */
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"msr CPSR_c, #ARM_MODE_ABT | I_BIT | F_BIT \n\t"
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/* store all registers */
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"stmfd sp!, { r0-r12 } \n\t"
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/* saved cpsr (from aborted mode) */
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"mrs r0, SPSR \n\t"
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/* address of abort (pc) */
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"mov r3, lr \n\t"
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/* enter previous mode and get lr(r14), sp(r13) */
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"orr r1, r0, #I_BIT | F_BIT \n\t"
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"msr CPSR_c, r1 \n\t"
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"mov r1, sp \n\t"
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"mov r2, lr \n\t"
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/* return to abort mode */
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"msr CPSR_c, #ARM_MODE_ABT | I_BIT | F_BIT \n\t"
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/* store remaining registers (r1-r3 == r13-r15) */
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"stmfd sp!, { r1-r3 } \n\t"
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"mov r1, sp \n\t"
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/* execute C Handler (cpsr, *registers) */
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"ldr r5, =at91_abt_handler \n\t"
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"mov lr, pc \n\t"
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"bx r5 \n\t"
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"b . \n\t"
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);
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}
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