100 lines
3.3 KiB
C
100 lines
3.3 KiB
C
/***************************************************************************
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* Copyright (C) 01/2008 by Olaf Rempel *
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* razzor@kopf-tisch.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; version 2 of the License *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#include <stdint.h>
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#include <stdio.h>
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#include "AT91SAM7S256.h"
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#include "board.h"
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#include "at91_pitc.h"
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#include "static_alloc.h"
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static uint16_t adc_result[4];
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static void at91_adc_isr(void)
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{
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AT91S_PDC *pdc = AT91C_BASE_PDC_ADC;
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pdc->PDC_RPR = (uint32_t) &adc_result;
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pdc->PDC_RCR = ARRAY_SIZE(adc_result);
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pdc->PDC_PTCR = AT91C_PDC_RXTEN;
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/* clear interrupts */
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AT91S_ADC *adc = AT91C_BASE_ADC;
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uint32_t status = adc->ADC_SR;
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status = status;
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}
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static uint32_t adc_trigger(struct pitc_timer *timer)
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{
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*AT91C_ADC_CR = AT91C_ADC_START;
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return PITC_RESTART_TIMER;
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}
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void at91_adc_test_init(void)
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{
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/* enable ADC clock */
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*AT91C_PMC_PCER = (1 << AT91C_ID_ADC);
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/* ADC Software reset */
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AT91S_ADC *adc = AT91C_BASE_ADC;
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adc->ADC_CR = AT91C_ADC_SWRST;
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/*
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* ADC config: 10bit, no sleep
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* 4.8MHz (48MHz / ((4 +1) * 2) = 4.8MHz)
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* 96 cycles Startup ((11 +1) * 8 / 4.8MHz = 20us)
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* 3 cycles SH ((2 +1) / 4.8MHz = 625ns)
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* Conversion time per channel @5MHz ~2us
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*/
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adc->ADC_MR = AT91C_ADC_TRGEN_DIS |
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AT91C_ADC_LOWRES_10_BIT |
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AT91C_ADC_SLEEP_NORMAL_MODE |
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(AT91C_ADC_PRESCAL & (4 << 8)) |
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(AT91C_ADC_STARTUP & (11 << 16)) |
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(AT91C_ADC_SHTIM & (2 << 24));
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/* setup PDC */
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AT91S_PDC *pdc = AT91C_BASE_PDC_ADC;
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pdc->PDC_RPR = (uint32_t) &adc_result;
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pdc->PDC_RCR = ARRAY_SIZE(adc_result);
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pdc->PDC_PTCR = AT91C_PDC_RXTEN;
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/* enable 4 channels, PDC Interrupt */
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adc->ADC_CHER = 0xF0;
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adc->ADC_IER = AT91C_ADC_ENDRX;
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/* low priority, level triggered, own vector */
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AT91S_AIC *aic = AT91C_BASE_AIC;
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aic->AIC_SMR[AT91C_ID_ADC] = IRQPRIO_ADC | AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL;
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aic->AIC_SVR[AT91C_ID_ADC] = (uint32_t)at91_adc_isr;
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aic->AIC_IECR = (1<<AT91C_ID_ADC);
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/* schedule trigger */
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struct pitc_timer *adc_timer = alloc_pitc_timer(100, &adc_trigger, NULL);
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pitc_schedule_timer(adc_timer);
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}
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void at91_adc_printresults(void)
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{
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uint8_t i;
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for (i = 0; i < ARRAY_SIZE(adc_result); i++)
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printf("%x:0x%03X ", i, adc_result[i]);
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printf("\n");
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}
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