176 lines
5.3 KiB
C
176 lines
5.3 KiB
C
/***************************************************************************
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* Copyright (C) 01/2008 by Olaf Rempel *
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* razzor@kopf-tisch.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; version 2 of the License *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#include <stdint.h>
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#include "AT91SAM7S256.h"
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#include "board.h"
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static void empty_isr(void) {}
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/*
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* Init critical onchip hardware:
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* - disable Watchdog
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* - enable Oscillator and PLL, switch to 48MHz MCK
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* - set empty Interrupt Handlers
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*/
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void at91_init1(void)
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{
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/* disable watchdog */
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*AT91C_WDTC_WDMR = AT91C_WDTC_WDDIS;
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/* enable user reset */
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*AT91C_RSTC_RMR = (AT91C_RSTC_KEY & 0xA5 << 24) | AT91C_RSTC_URSTEN;
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/* Set Flash Waitstates */
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*AT91C_MC_FMR = (AT91C_MC_FMCN & ((MCK / 666666) << 16)) | AT91C_MC_FWS_1FWS;
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/*
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* Enable main oscillator (MAINCK)
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* startup time: 8*6/32768 -> 1.46ms
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*/
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AT91S_PMC *pmc = AT91C_BASE_PMC;
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pmc->PMC_MOR = (AT91C_CKGR_OSCOUNT & (6<<8)) |
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AT91C_CKGR_MOSCEN;
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while (!(pmc->PMC_SR & AT91C_PMC_MOSCS));
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/*
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* PLLCK = 18.432MHz / 24 * 125 = 96MHz -> div:24, mul:124
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* startup time: 32/32768 -> 976us
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*/
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pmc->PMC_PLLR = (AT91C_CKGR_DIV & 24) |
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(AT91C_CKGR_MUL & (124<<16)) |
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(AT91C_CKGR_PLLCOUNT & (32<<8)) ;
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while (!(pmc->PMC_SR & AT91C_PMC_LOCK));
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/* MCK = PLLCK / 2 = 48MHz */
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pmc->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK |
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AT91C_PMC_PRES_CLK_2;
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while (!(pmc->PMC_SR & AT91C_PMC_MCKRDY));
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/* enable protected mode (let AIC work with debugger) */
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AT91S_AIC *aic = AT91C_BASE_AIC;
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aic->AIC_DCR = AT91C_AIC_DCR_PROT;
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/* Disable & clear all Interrupts */
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aic->AIC_IDCR = ~0;
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aic->AIC_ICCR = ~0;
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/* default Interrupt Handlers just return */
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aic->AIC_FVR = (uint32_t)empty_isr;
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aic->AIC_IVR = (uint32_t)empty_isr;
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uint32_t i;
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for (i = 0; i < 32; i++) {
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aic->AIC_SMR[i] = 0;
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aic->AIC_SVR[i] = (uint32_t)empty_isr;
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}
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aic->AIC_SPU = (uint32_t)empty_isr;
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}
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__attribute__((naked)) void IRQ_Handler(void)
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{
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asm volatile (
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".equ ARM_MODE_IRQ, 0x12 \n\t"
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".equ ARM_MODE_SVC, 0x13 \n\t"
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".equ I_BIT, 0x80 \n\t"
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".equ AIC_IVR, (256) \n\t"
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".equ AIC_EOICR, (304) \n\t"
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".equ AT91C_BASE_AIC, (0xFFFFF000) \n\t"
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/* Adjust and save lr_irq on IRQ stack */
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"sub lr, lr, #4 \n\t"
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"stmfd sp!, { lr } \n\t"
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/* Save SPSR (for nested interrupts) */
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"mrs r14, SPSR \n\t"
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"stmfd sp!, { r14 } \n\t"
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/* Save r0 on IRQ stack */
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"stmfd sp!, { r0 } \n\t"
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/* Write in the IVR to support Protect Mode */
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"ldr r14, =AT91C_BASE_AIC \n\t"
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"ldr r0, [r14, #AIC_IVR] \n\t"
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"str r14, [r14, #AIC_IVR] \n\t"
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/* Enable Interrupt and switch to SVC mode */
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"msr CPSR_c, #ARM_MODE_SVC \n\t"
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/* Save scratch/used registers and lr on SVC Stack */
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"stmfd sp!, { r1-r3, r12, r14 } \n\t"
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/* Branch to the routine pointed by the AIC_IVR */
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"mov r14, pc \n\t"
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"bx r0 \n\t"
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/* Restore scratch/used registers and lr from SVC Stack */
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"ldmia sp!, { r1-r3, r12, r14 } \n\t"
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/* Disable Interrupt and switch back to IRQ mode */
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"msr CPSR_c, #ARM_MODE_IRQ | I_BIT \n\t"
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/* Mark the End of Interrupt on the AIC */
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"ldr r14, =AT91C_BASE_AIC \n\t"
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"str r14, [r14, #AIC_EOICR] \n\t"
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/* Restore SPSR_irq and r0 from IRQ stack */
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"ldmia sp!, { r0 } \n\t"
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"ldmia sp!, { r14 } \n\t"
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"msr SPSR_cxsf, r14 \n\t"
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/* Restore adjusted lr_irq from IRQ stack */
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"ldmia sp!, { pc }^ \n\t"
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);
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}
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__attribute__((naked)) void FIQ_Handler(void)
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{
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asm volatile (
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".equ ARM_MODE_FIQ, 0x11 \n\t"
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".equ ARM_MODE_SVC, 0x13 \n\t"
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".equ I_BIT, 0x80 \n\t"
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".equ F_BIT, 0x40 \n\t"
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".equ AIC_FVR, (260) \n\t"
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/* Save r0 to r9_fiq */
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"mov r9, r0 \n\t"
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/* get FIQ Vector from AIC and thus clear FIQ */
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"ldr r0, [r8, #AIC_FVR] \n\t"
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/* Switch to SVC and save registers there */
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"msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT \n\t"
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"stmfd sp!, { r1-r3, r12, lr } \n\t"
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/* execute FIQ in SVC_MODE */
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"mov r14, pc \n\t"
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"bx r0 \n\t"
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/* restore registers and switch back to FIQ */
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"ldmia sp!, { r1-r3, r12, lr } \n\t"
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"msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT \n\t"
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/* restore the r0 from r9_fiq */
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"mov r0, r9 \n\t"
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/* restore PC using the lr_fiq directly */
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"subs pc, lr, #4 \n\t"
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);
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}
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