Currently clock stretching is used for write/erase timing - the bus is "stopped" (by forcing SCL=low) while the AVR is writing to the flash/eeprom.
Some I2C masters (eg. BCM2835 / Raspberry Pi) do not detect SCL=low forced by the slave und continue to write data to twiboot.
Workaround could be:
- start the actual write cycle only after STOP condition is received
- do not acknowledge ADDR+WRITE while chip is busy writing
- add a new read command to check if chip is buy writing
This will break existing applications since (fast) I2C transaction will now fail during chip write cycle.