Currently clock stretching is used for write/erase timing - the bus is “stopped” (by forcing SCL=low) while the AVR is writing to the flash/eeprom.
Some I2C masters (eg. BCM2835 / Raspberry Pi) do not detect SCL=low forced by the slave und continue to write data to twiboot.
Workaround could be:
This will break existing applications since (fast) I2C transaction will now fail during chip write cycle.
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