Olaf Rempel
f4952aaa63
- patch reset vector while programming flash page0 Let the reset vector always point to the twiboot start. - Use another (must be unused!) ISR vector to store the original reset vector as jump to the application. - Cache the values for the verification read - currently works only for devices < 8kB flash (2 byte vector entries) - using a attiny85 as target This change is heavily based on the optiboot bootloader.
901 lines
26 KiB
C
901 lines
26 KiB
C
/***************************************************************************
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* Copyright (C) 10/2020 by Olaf Rempel *
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* razzor@kopf-tisch.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; version 2 of the License, *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#include <avr/io.h>
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#include <avr/interrupt.h>
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#include <avr/boot.h>
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#include <avr/pgmspace.h>
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#define VERSION_STRING "TWIBOOT v3.1"
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#define EEPROM_SUPPORT 1
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#define LED_SUPPORT 1
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#ifndef USE_CLOCKSTRETCH
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#define USE_CLOCKSTRETCH 0
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#endif
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#ifndef VIRTUAL_BOOT_SECTION
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#define VIRTUAL_BOOT_SECTION 0
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#endif
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#ifndef TWI_ADDRESS
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#define TWI_ADDRESS 0x29
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#endif
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#define F_CPU 8000000ULL
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#define TIMER_DIVISOR 1024
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#define TIMER_IRQFREQ_MS 25
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#define TIMEOUT_MS 1000
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#define TIMER_MSEC2TICKS(x) ((x * F_CPU) / (TIMER_DIVISOR * 1000ULL))
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#define TIMER_MSEC2IRQCNT(x) (x / TIMER_IRQFREQ_MS)
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#if (LED_SUPPORT)
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#define LED_INIT() DDRB = ((1<<PORTB4) | (1<<PORTB5))
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#define LED_RT_ON() PORTB |= (1<<PORTB4)
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#define LED_RT_OFF() PORTB &= ~(1<<PORTB4)
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#define LED_GN_ON() PORTB |= (1<<PORTB5)
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#define LED_GN_OFF() PORTB &= ~(1<<PORTB5)
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#define LED_GN_TOGGLE() PORTB ^= (1<<PORTB5)
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#define LED_OFF() PORTB = 0x00
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#else
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#define LED_INIT()
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#define LED_RT_ON()
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#define LED_RT_OFF()
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#define LED_GN_ON()
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#define LED_GN_OFF()
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#define LED_GN_TOGGLE()
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#define LED_OFF()
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#endif /* LED_SUPPORT */
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#if !defined(TWCR) && defined(USICR)
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#define USI_PIN_INIT() { PORTB |= ((1<<PORTB0) | (1<<PORTB2)); \
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DDRB |= (1<<PORTB2); \
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}
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#define USI_PIN_SDA_INPUT() DDRB &= ~(1<<PORTB0)
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#define USI_PIN_SDA_OUTPUT() DDRB |= (1<<PORTB0)
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#define USI_PIN_SCL() (PINB & (1<<PINB2))
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#if (USE_CLOCKSTRETCH == 0)
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#error "USI peripheral requires enabled USE_CLOCKSTRETCH"
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#endif
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#define USI_STATE_MASK 0x0F
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#define USI_STATE_IDLE 0x00 /* wait for Start Condition */
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#define USI_STATE_SLA 0x01 /* wait for Slave Address */
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#define USI_STATE_SLAW_ACK 0x02 /* ACK Slave Address + Write (Master writes) */
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#define USI_STATE_SLAR_ACK 0x03 /* ACK Slave Address + Read (Master reads) */
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#define USI_STATE_NAK 0x04 /* send NAK */
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#define USI_STATE_DATW 0x05 /* receive Data */
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#define USI_STATE_DATW_ACK 0x06 /* transmit ACK for received Data */
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#define USI_STATE_DATR 0x07 /* transmit Data */
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#define USI_STATE_DATR_ACK 0x08 /* receive ACK for transmitted Data */
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#define USI_WAIT_FOR_ACK 0x10 /* wait for ACK bit (2 SCL clock edges) */
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#define USI_ENABLE_SDA_OUTPUT 0x20 /* SDA is output (slave transmitting) */
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#define USI_ENABLE_SCL_HOLD 0x40 /* Hold SCL low after clock overflow */
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#endif /* !defined(TWCR) && defined(USICR) */
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#if (VIRTUAL_BOOT_SECTION)
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/* unused vector to store application start address */
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#define APPVECT_NUM EE_RDY_vect_num
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/* each vector table entry is a 2byte RJMP opcode */
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#define RSTVECT_ADDR 0x0000
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#define APPVECT_ADDR (APPVECT_NUM * 2)
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#define RSTVECT_PAGE_OFFSET (RSTVECT_ADDR % SPM_PAGESIZE)
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#define APPVECT_PAGE_OFFSET (APPVECT_ADDR % SPM_PAGESIZE)
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/* create RJMP opcode for the vector table */
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#define OPCODE_RJMP(addr) (((addr) & 0x0FFF) | 0xC000)
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#elif (!defined(ASRE) && !defined (RWWSRE))
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#error "Device without bootloader section requires VIRTUAL_BOOT_SECTION"
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#endif
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/* SLA+R */
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#define CMD_WAIT 0x00
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#define CMD_READ_VERSION 0x01
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#define CMD_ACCESS_MEMORY 0x02
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/* internal mappings */
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#define CMD_ACCESS_CHIPINFO (0x10 | CMD_ACCESS_MEMORY)
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#define CMD_ACCESS_FLASH (0x20 | CMD_ACCESS_MEMORY)
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#define CMD_ACCESS_EEPROM (0x30 | CMD_ACCESS_MEMORY)
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#define CMD_WRITE_FLASH_PAGE (0x40 | CMD_ACCESS_MEMORY)
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#define CMD_WRITE_EEPROM_PAGE (0x50 | CMD_ACCESS_MEMORY)
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/* SLA+W */
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#define CMD_SWITCH_APPLICATION CMD_READ_VERSION
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/* internal mappings */
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#define CMD_BOOT_BOOTLOADER (0x10 | CMD_SWITCH_APPLICATION) /* only in APP */
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#define CMD_BOOT_APPLICATION (0x20 | CMD_SWITCH_APPLICATION)
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/* CMD_SWITCH_APPLICATION parameter */
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#define BOOTTYPE_BOOTLOADER 0x00 /* only in APP */
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#define BOOTTYPE_APPLICATION 0x80
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/* CMD_{READ|WRITE}_* parameter */
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#define MEMTYPE_CHIPINFO 0x00
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#define MEMTYPE_FLASH 0x01
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#define MEMTYPE_EEPROM 0x02
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/*
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* LED_GN flashes with 20Hz (while bootloader is running)
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* LED_RT flashes on TWI activity
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*
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* bootloader twi-protocol:
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* - abort boot timeout:
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* SLA+W, 0x00, STO
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*
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* - show bootloader version
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* SLA+W, 0x01, SLA+R, {16 bytes}, STO
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*
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* - start application
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* SLA+W, 0x01, 0x80, STO
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*
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* - read chip info: 3byte signature, 1byte page size, 2byte flash size, 2byte eeprom size
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* SLA+W, 0x02, 0x00, 0x00, 0x00, SLA+R, {8 bytes}, STO
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*
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* - read one (or more) flash bytes
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* SLA+W, 0x02, 0x01, addrh, addrl, SLA+R, {* bytes}, STO
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*
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* - read one (or more) eeprom bytes
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* SLA+W, 0x02, 0x02, addrh, addrl, SLA+R, {* bytes}, STO
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*
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* - write one flash page
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* SLA+W, 0x02, 0x01, addrh, addrl, {* bytes}, STO
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*
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* - write one (or more) eeprom bytes
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* SLA+W, 0x02, 0x02, addrh, addrl, {* bytes}, STO
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*/
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const static uint8_t info[16] = VERSION_STRING;
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const static uint8_t chipinfo[8] = {
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SIGNATURE_0, SIGNATURE_1, SIGNATURE_2,
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SPM_PAGESIZE,
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(BOOTLOADER_START >> 8) & 0xFF,
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BOOTLOADER_START & 0xFF,
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#if (EEPROM_SUPPORT)
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((E2END +1) >> 8 & 0xFF),
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(E2END +1) & 0xFF
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#else
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0x00, 0x00
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#endif
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};
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static uint8_t boot_timeout = TIMER_MSEC2IRQCNT(TIMEOUT_MS);
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static uint8_t cmd = CMD_WAIT;
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/* flash buffer */
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static uint8_t buf[SPM_PAGESIZE];
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static uint16_t addr;
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#if (VIRTUAL_BOOT_SECTION)
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/* reset/application vectors received from host, needed for verify read */
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static uint8_t rstvect_save[2];
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static uint8_t appvect_save[2];
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#endif /* (VIRTUAL_BOOT_SECTION) */
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/* *************************************************************************
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* write_flash_page
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* ************************************************************************* */
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static void write_flash_page(void)
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{
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uint16_t pagestart = addr;
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uint8_t size = SPM_PAGESIZE;
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uint8_t *p = buf;
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#if (VIRTUAL_BOOT_SECTION)
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if (pagestart == (RSTVECT_ADDR & ~(SPM_PAGESIZE -1)))
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{
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/* save original vectors for verify read */
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rstvect_save[0] = buf[RSTVECT_PAGE_OFFSET];
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rstvect_save[1] = buf[RSTVECT_PAGE_OFFSET + 1];
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appvect_save[0] = buf[APPVECT_PAGE_OFFSET];
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appvect_save[1] = buf[APPVECT_PAGE_OFFSET + 1];
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/* replace reset vector with jump to bootloader address */
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uint16_t rst_vector = OPCODE_RJMP(BOOTLOADER_START -1);
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buf[RSTVECT_PAGE_OFFSET] = (rst_vector & 0xFF);
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buf[RSTVECT_PAGE_OFFSET + 1] = (rst_vector >> 8) & 0xFF;
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/* replace application vector with jump to original reset vector */
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uint16_t app_vector = rstvect_save[0] | (rstvect_save[1] << 8);
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app_vector = OPCODE_RJMP(app_vector - APPVECT_NUM);
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buf[APPVECT_PAGE_OFFSET] = (app_vector & 0xFF);
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buf[APPVECT_PAGE_OFFSET + 1] = (app_vector >> 8) & 0xFF;
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}
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#endif /* (VIRTUAL_BOOT_SECTION) */
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if (pagestart < BOOTLOADER_START)
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{
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boot_page_erase(pagestart);
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boot_spm_busy_wait();
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do {
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uint16_t data = *p++;
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data |= *p++ << 8;
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boot_page_fill(addr, data);
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addr += 2;
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size -= 2;
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} while (size);
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boot_page_write(pagestart);
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boot_spm_busy_wait();
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#if defined (ASRE) || defined (RWWSRE)
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/* only required for bootloader section */
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boot_rww_enable();
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#endif
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}
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} /* write_flash_page */
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#if (EEPROM_SUPPORT)
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/* *************************************************************************
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* read_eeprom_byte
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* ************************************************************************* */
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static uint8_t read_eeprom_byte(uint16_t address)
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{
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EEARL = address;
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EEARH = (address >> 8);
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EECR |= (1<<EERE);
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return EEDR;
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} /* read_eeprom_byte */
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/* *************************************************************************
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* write_eeprom_byte
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* ************************************************************************* */
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static void write_eeprom_byte(uint8_t val)
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{
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EEARL = addr;
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EEARH = (addr >> 8);
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EEDR = val;
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addr++;
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#if defined (EEWE)
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EECR |= (1<<EEMWE);
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EECR |= (1<<EEWE);
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#elif defined (EEPE)
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EECR |= (1<<EEMPE);
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EECR |= (1<<EEPE);
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#else
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#error "EEWE/EEPE not defined"
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#endif
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eeprom_busy_wait();
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} /* write_eeprom_byte */
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#if (USE_CLOCKSTRETCH == 0)
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/* *************************************************************************
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* write_eeprom_buffer
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* ************************************************************************* */
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static void write_eeprom_buffer(uint8_t size)
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{
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uint8_t *p = buf;
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while (size--)
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{
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write_eeprom_byte(*p++);
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}
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} /* write_eeprom_buffer */
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#endif /* (USE_CLOCKSTRETCH == 0) */
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#endif /* EEPROM_SUPPORT */
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/* *************************************************************************
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* TWI_data_write
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* ************************************************************************* */
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static uint8_t TWI_data_write(uint8_t bcnt, uint8_t data)
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{
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uint8_t ack = 0x01;
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switch (bcnt)
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{
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case 0:
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switch (data)
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{
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case CMD_SWITCH_APPLICATION:
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case CMD_ACCESS_MEMORY:
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/* no break */
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case CMD_WAIT:
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/* abort countdown */
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boot_timeout = 0;
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cmd = data;
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break;
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default:
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/* boot app now */
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cmd = CMD_BOOT_APPLICATION;
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ack = 0x00;
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break;
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}
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break;
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case 1:
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switch (cmd)
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{
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case CMD_SWITCH_APPLICATION:
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if (data == BOOTTYPE_APPLICATION)
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{
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cmd = CMD_BOOT_APPLICATION;
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}
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ack = 0x00;
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break;
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case CMD_ACCESS_MEMORY:
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if (data == MEMTYPE_CHIPINFO)
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{
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cmd = CMD_ACCESS_CHIPINFO;
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}
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else if (data == MEMTYPE_FLASH)
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{
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cmd = CMD_ACCESS_FLASH;
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}
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#if (EEPROM_SUPPORT)
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else if (data == MEMTYPE_EEPROM)
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{
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cmd = CMD_ACCESS_EEPROM;
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}
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#endif /* (EEPROM_SUPPORT) */
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else
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{
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ack = 0x00;
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}
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break;
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default:
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ack = 0x00;
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break;
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}
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break;
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case 2:
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case 3:
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addr <<= 8;
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addr |= data;
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break;
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default:
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switch (cmd)
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{
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#if (EEPROM_SUPPORT)
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#if (USE_CLOCKSTRETCH)
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case CMD_ACCESS_EEPROM:
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write_eeprom_byte(data);
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break;
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#else
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case CMD_ACCESS_EEPROM:
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cmd = CMD_WRITE_EEPROM_PAGE;
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/* fall through */
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case CMD_WRITE_EEPROM_PAGE:
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#endif /* (USE_CLOCKSTRETCH) */
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#endif /* (EEPROM_SUPPORT) */
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case CMD_ACCESS_FLASH:
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{
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uint8_t pos = bcnt -4;
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buf[pos] = data;
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if (pos >= (sizeof(buf) -2))
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{
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ack = 0x00;
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}
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if ((cmd == CMD_ACCESS_FLASH) &&
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(pos >= (sizeof(buf) -1))
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)
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{
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#if (USE_CLOCKSTRETCH)
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write_flash_page();
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#else
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cmd = CMD_WRITE_FLASH_PAGE;
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#endif
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}
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break;
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}
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default:
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ack = 0x00;
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break;
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}
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break;
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}
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return ack;
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} /* TWI_data_write */
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/* *************************************************************************
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* TWI_data_read
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* ************************************************************************* */
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static uint8_t TWI_data_read(uint8_t bcnt)
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{
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uint8_t data;
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switch (cmd)
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{
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case CMD_READ_VERSION:
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bcnt %= sizeof(info);
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data = info[bcnt];
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break;
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case CMD_ACCESS_CHIPINFO:
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bcnt %= sizeof(chipinfo);
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data = chipinfo[bcnt];
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break;
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case CMD_ACCESS_FLASH:
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switch (addr)
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{
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/* return cached values for verify read */
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#if (VIRTUAL_BOOT_SECTION)
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case RSTVECT_ADDR:
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data = rstvect_save[0];
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break;
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case (RSTVECT_ADDR + 1):
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data = rstvect_save[1];
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break;
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case APPVECT_ADDR:
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data = appvect_save[0];
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break;
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case (APPVECT_ADDR + 1):
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data = appvect_save[1];
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break;
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#endif /* (VIRTUAL_BOOT_SECTION) */
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default:
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data = pgm_read_byte_near(addr);
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break;
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}
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addr++;
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break;
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#if (EEPROM_SUPPORT)
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case CMD_ACCESS_EEPROM:
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data = read_eeprom_byte(addr++);
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break;
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#endif /* (EEPROM_SUPPORT) */
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default:
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data = 0xFF;
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break;
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}
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return data;
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} /* TWI_data_read */
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#if defined (TWCR)
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/* *************************************************************************
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* TWI_vect
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* ************************************************************************* */
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static void TWI_vect(void)
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{
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static uint8_t bcnt;
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uint8_t control = TWCR;
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switch (TWSR & 0xF8)
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{
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/* SLA+W received, ACK returned -> receive data and ACK */
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case 0x60:
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bcnt = 0;
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LED_RT_ON();
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break;
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/* prev. SLA+W, data received, ACK returned -> receive data and ACK */
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case 0x80:
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if (TWI_data_write(bcnt++, TWDR) == 0x00)
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{
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/* the ACK returned by TWI_data_write() is not for the current
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* data in TWDR, but for the next byte received
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*/
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control &= ~(1<<TWEA);
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}
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break;
|
|
|
|
/* SLA+R received, ACK returned -> send data */
|
|
case 0xA8:
|
|
bcnt = 0;
|
|
LED_RT_ON();
|
|
/* fall through */
|
|
|
|
/* prev. SLA+R, data sent, ACK returned -> send data */
|
|
case 0xB8:
|
|
TWDR = TWI_data_read(bcnt++);
|
|
break;
|
|
|
|
/* prev. SLA+W, data received, NACK returned -> IDLE */
|
|
case 0x88:
|
|
TWI_data_write(bcnt++, TWDR);
|
|
/* fall through */
|
|
|
|
/* STOP or repeated START -> IDLE */
|
|
case 0xA0:
|
|
#if (USE_CLOCKSTRETCH == 0)
|
|
if ((cmd == CMD_WRITE_FLASH_PAGE)
|
|
#if (EEPROM_SUPPORT)
|
|
|| (cmd == CMD_WRITE_EEPROM_PAGE)
|
|
#endif
|
|
)
|
|
{
|
|
/* disable ACK for now, re-enable after page write */
|
|
control &= ~(1<<TWEA);
|
|
TWCR = (1<<TWINT) | control;
|
|
|
|
#if (EEPROM_SUPPORT)
|
|
if (cmd == CMD_WRITE_EEPROM_PAGE)
|
|
{
|
|
write_eeprom_buffer(bcnt -4);
|
|
}
|
|
else
|
|
#endif /* (EEPROM_SUPPORT) */
|
|
{
|
|
write_flash_page();
|
|
}
|
|
}
|
|
#endif /* (USE_CLOCKSTRETCH) */
|
|
|
|
bcnt = 0;
|
|
/* fall through */
|
|
|
|
/* prev. SLA+R, data sent, NACK returned -> IDLE */
|
|
case 0xC0:
|
|
LED_RT_OFF();
|
|
control |= (1<<TWEA);
|
|
break;
|
|
|
|
/* illegal state(s) -> reset hardware */
|
|
default:
|
|
control |= (1<<TWSTO);
|
|
break;
|
|
}
|
|
|
|
TWCR = (1<<TWINT) | control;
|
|
} /* TWI_vect */
|
|
#endif /* defined (TWCR) */
|
|
|
|
#if defined (USICR)
|
|
/* *************************************************************************
|
|
* usi_statemachine
|
|
* ************************************************************************* */
|
|
static void usi_statemachine(uint8_t usisr)
|
|
{
|
|
static uint8_t usi_state;
|
|
static uint8_t bcnt;
|
|
|
|
uint8_t data = USIDR;
|
|
uint8_t state = usi_state & USI_STATE_MASK;
|
|
|
|
/* Start Condition detected */
|
|
if (usisr & (1<<USISIF))
|
|
{
|
|
/* wait until SCL goes low */
|
|
while (USI_PIN_SCL());
|
|
|
|
usi_state = USI_STATE_SLA | USI_ENABLE_SCL_HOLD;
|
|
state = USI_STATE_IDLE;
|
|
}
|
|
|
|
/* Stop Condition detected */
|
|
if (usisr & (1<<USIPF))
|
|
{
|
|
LED_RT_OFF();
|
|
usi_state = USI_STATE_IDLE;
|
|
state = USI_STATE_IDLE;
|
|
}
|
|
|
|
if (state == USI_STATE_IDLE)
|
|
{
|
|
/* do nothing */
|
|
}
|
|
/* Slave Address received => prepare ACK/NAK */
|
|
else if (state == USI_STATE_SLA)
|
|
{
|
|
bcnt = 0;
|
|
|
|
/* SLA+W received -> send ACK */
|
|
if (data == ((TWI_ADDRESS<<1) | 0x00))
|
|
{
|
|
LED_RT_ON();
|
|
usi_state = USI_STATE_SLAW_ACK | USI_WAIT_FOR_ACK | USI_ENABLE_SDA_OUTPUT | USI_ENABLE_SCL_HOLD;
|
|
USIDR = 0x00;
|
|
}
|
|
/* SLA+R received -> send ACK */
|
|
else if (data == ((TWI_ADDRESS<<1) | 0x01))
|
|
{
|
|
LED_RT_ON();
|
|
usi_state = USI_STATE_SLAR_ACK | USI_WAIT_FOR_ACK | USI_ENABLE_SDA_OUTPUT | USI_ENABLE_SCL_HOLD;
|
|
USIDR = 0x00;
|
|
}
|
|
/* not addressed -> send NAK */
|
|
else
|
|
{
|
|
usi_state = USI_STATE_NAK | USI_WAIT_FOR_ACK | USI_ENABLE_SDA_OUTPUT | USI_ENABLE_SCL_HOLD;
|
|
USIDR = 0x80;
|
|
}
|
|
}
|
|
/* sent NAK -> go to idle */
|
|
else if (state == USI_STATE_NAK)
|
|
{
|
|
usi_state = USI_STATE_IDLE;
|
|
}
|
|
/* sent ACK after SLA+W -> wait for data */
|
|
/* sent ACK after DAT+W -> wait for more data */
|
|
else if ((state == USI_STATE_SLAW_ACK) ||
|
|
(state == USI_STATE_DATW_ACK)
|
|
)
|
|
{
|
|
usi_state = USI_STATE_DATW | USI_ENABLE_SCL_HOLD;
|
|
}
|
|
/* data received -> send ACK/NAK */
|
|
else if (state == USI_STATE_DATW)
|
|
{
|
|
if (TWI_data_write(bcnt++, data))
|
|
{
|
|
usi_state = USI_STATE_DATW_ACK | USI_WAIT_FOR_ACK | USI_ENABLE_SDA_OUTPUT | USI_ENABLE_SCL_HOLD;
|
|
USIDR = 0x00;
|
|
}
|
|
else
|
|
{
|
|
usi_state = USI_STATE_NAK | USI_WAIT_FOR_ACK | USI_ENABLE_SDA_OUTPUT | USI_ENABLE_SCL_HOLD;
|
|
USIDR = 0x80;
|
|
}
|
|
}
|
|
/* sent ACK after SLA+R -> send data */
|
|
/* received ACK after DAT+R -> send more data */
|
|
else if ((state == USI_STATE_SLAR_ACK) ||
|
|
((state == USI_STATE_DATR_ACK) && !(data & 0x01))
|
|
)
|
|
{
|
|
USIDR = TWI_data_read(bcnt++);
|
|
usi_state = USI_STATE_DATR | USI_ENABLE_SDA_OUTPUT | USI_ENABLE_SCL_HOLD;
|
|
}
|
|
/* sent data after SLA+R -> receive ACK/NAK */
|
|
else if (state == USI_STATE_DATR)
|
|
{
|
|
usi_state = USI_STATE_DATR_ACK | USI_WAIT_FOR_ACK | USI_ENABLE_SCL_HOLD;
|
|
USIDR = 0x80;
|
|
}
|
|
/* received NAK after DAT+R -> go to idle */
|
|
else if ((state == USI_STATE_DATR_ACK) && (data & 0x01))
|
|
{
|
|
usi_state = USI_STATE_IDLE;
|
|
}
|
|
/* default -> go to idle */
|
|
else
|
|
{
|
|
usi_state = USI_STATE_IDLE;
|
|
}
|
|
|
|
/* set SDA direction according to current state */
|
|
if (usi_state & USI_ENABLE_SDA_OUTPUT)
|
|
{
|
|
USI_PIN_SDA_OUTPUT();
|
|
}
|
|
else
|
|
{
|
|
USI_PIN_SDA_INPUT();
|
|
}
|
|
|
|
if (usi_state & USI_ENABLE_SCL_HOLD)
|
|
{
|
|
/* Enable TWI Mode, hold SCL low after counter overflow, count both SCL edges */
|
|
USICR = (1<<USIWM1) | (1<<USIWM0) | (1<<USICS1);
|
|
}
|
|
else
|
|
{
|
|
/* Enable TWI, hold SCL low only after start condition, count both SCL edges */
|
|
USICR = (1<<USIWM1) | (1<<USICS1);
|
|
}
|
|
|
|
/* clear start/overflow/stop condition flags */
|
|
usisr &= ((1<<USISIF) | (1<<USIOIF) | (1<<USIPF));
|
|
if (usi_state & USI_WAIT_FOR_ACK)
|
|
{
|
|
/* count 2 SCL edges (ACK/NAK bit) */
|
|
USISR = usisr | ((16 -2)<<USICNT0);
|
|
}
|
|
else
|
|
{
|
|
/* count 16 SCL edges (8bit data) */
|
|
USISR = usisr | ((16 -16)<<USICNT0);
|
|
}
|
|
} /* usi_statemachine */
|
|
#endif /* defined (USICR) */
|
|
|
|
|
|
/* *************************************************************************
|
|
* TIMER0_OVF_vect
|
|
* ************************************************************************* */
|
|
static void TIMER0_OVF_vect(void)
|
|
{
|
|
/* restart timer */
|
|
TCNT0 = 0xFF - TIMER_MSEC2TICKS(TIMER_IRQFREQ_MS);
|
|
|
|
/* blink LED while running */
|
|
LED_GN_TOGGLE();
|
|
|
|
/* count down for app-boot */
|
|
if (boot_timeout > 1)
|
|
{
|
|
boot_timeout--;
|
|
}
|
|
else if (boot_timeout == 1)
|
|
{
|
|
/* trigger app-boot */
|
|
cmd = CMD_BOOT_APPLICATION;
|
|
}
|
|
} /* TIMER0_OVF_vect */
|
|
|
|
|
|
#if (VIRTUAL_BOOT_SECTION)
|
|
static void (*jump_to_app)(void) __attribute__ ((noreturn)) = (void*)APPVECT_ADDR;
|
|
#else
|
|
static void (*jump_to_app)(void) __attribute__ ((noreturn)) = (void*)0x0000;
|
|
#endif
|
|
|
|
|
|
/* *************************************************************************
|
|
* init1
|
|
* ************************************************************************* */
|
|
void init1(void) __attribute__((naked, section(".init1")));
|
|
void init1(void)
|
|
{
|
|
/* make sure r1 is 0x00 */
|
|
asm volatile ("clr __zero_reg__");
|
|
|
|
/* on some MCUs the stack pointer defaults NOT to RAMEND */
|
|
#if defined(__AVR_ATmega8__) || defined(__AVR_ATmega8515__) || \
|
|
defined(__AVR_ATmega8535__) || defined (__AVR_ATmega16__) || \
|
|
defined (__AVR_ATmega32__) || defined (__AVR_ATmega64__) || \
|
|
defined (__AVR_ATmega128__) || defined (__AVR_ATmega162__)
|
|
SP = RAMEND;
|
|
#endif
|
|
} /* init1 */
|
|
|
|
|
|
/*
|
|
* For newer devices the watchdog timer remains active even after a
|
|
* system reset. So disable it as soon as possible.
|
|
* automagically called on startup
|
|
*/
|
|
#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) || \
|
|
defined (__AVR_ATmega328P__)
|
|
/* *************************************************************************
|
|
* disable_wdt_timer
|
|
* ************************************************************************* */
|
|
void disable_wdt_timer(void) __attribute__((naked, section(".init3")));
|
|
void disable_wdt_timer(void)
|
|
{
|
|
MCUSR = 0;
|
|
WDTCSR = (1<<WDCE) | (1<<WDE);
|
|
WDTCSR = (0<<WDE);
|
|
} /* disable_wdt_timer */
|
|
#endif
|
|
|
|
|
|
/* *************************************************************************
|
|
* main
|
|
* ************************************************************************* */
|
|
int main(void) __attribute__ ((OS_main, section (".init9")));
|
|
int main(void)
|
|
{
|
|
LED_INIT();
|
|
LED_GN_ON();
|
|
|
|
#if (VIRTUAL_BOOT_SECTION)
|
|
/* load current values (for reading flash) */
|
|
rstvect_save[0] = pgm_read_byte_near(RSTVECT_ADDR);
|
|
rstvect_save[1] = pgm_read_byte_near(RSTVECT_ADDR + 1);
|
|
appvect_save[0] = pgm_read_byte_near(APPVECT_ADDR);
|
|
appvect_save[1] = pgm_read_byte_near(APPVECT_ADDR + 1);
|
|
#endif /* (VIRTUAL_BOOT_SECTION) */
|
|
|
|
/* timer0: running with F_CPU/1024 */
|
|
#if defined (TCCR0)
|
|
TCCR0 = (1<<CS02) | (1<<CS00);
|
|
#elif defined (TCCR0B)
|
|
TCCR0B = (1<<CS02) | (1<<CS00);
|
|
#else
|
|
#error "TCCR0(B) not defined"
|
|
#endif
|
|
|
|
#if defined (TWCR)
|
|
/* TWI init: set address, auto ACKs */
|
|
TWAR = (TWI_ADDRESS<<1);
|
|
TWCR = (1<<TWEA) | (1<<TWEN);
|
|
#elif defined (USICR)
|
|
USI_PIN_INIT();
|
|
usi_statemachine(0x00);
|
|
#else
|
|
#error "No TWI/USI peripheral found"
|
|
#endif
|
|
|
|
while (cmd != CMD_BOOT_APPLICATION)
|
|
{
|
|
#if defined (TWCR)
|
|
if (TWCR & (1<<TWINT))
|
|
{
|
|
TWI_vect();
|
|
}
|
|
#elif defined (USICR)
|
|
if (USISR & ((1<<USISIF) | (1<<USIOIF) | (1<<USIPF)))
|
|
{
|
|
usi_statemachine(USISR);
|
|
}
|
|
#endif
|
|
|
|
#if defined (TIFR)
|
|
if (TIFR & (1<<TOV0))
|
|
{
|
|
TIMER0_OVF_vect();
|
|
TIFR = (1<<TOV0);
|
|
}
|
|
#elif defined (TIFR0)
|
|
if (TIFR0 & (1<<TOV0))
|
|
{
|
|
TIMER0_OVF_vect();
|
|
TIFR0 = (1<<TOV0);
|
|
}
|
|
#else
|
|
#error "TIFR(0) not defined"
|
|
#endif
|
|
}
|
|
|
|
#if defined (TWCR)
|
|
/* Disable TWI but keep address! */
|
|
TWCR = 0x00;
|
|
#elif defined (USICR)
|
|
/* Disable USI peripheral */
|
|
USICR = 0x00;
|
|
#endif
|
|
|
|
/* disable timer0 */
|
|
#if defined (TCCR0)
|
|
TCCR0 = 0x00;
|
|
#elif defined (TCCR0B)
|
|
TCCR0B = 0x00;
|
|
#else
|
|
#error "TCCR0(B) not defined"
|
|
#endif
|
|
|
|
LED_OFF();
|
|
|
|
#if (LED_SUPPORT)
|
|
uint16_t wait = 0x0000;
|
|
do {
|
|
__asm volatile ("nop");
|
|
} while (--wait);
|
|
#endif /* (LED_SUPPORT) */
|
|
|
|
jump_to_app();
|
|
} /* main */
|