364 lines
12 KiB
C
364 lines
12 KiB
C
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/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef MV_OS_H
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#define MV_OS_H
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/*************/
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/* Includes */
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/*************/
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#include "mvTypes.h"
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#include "mvCommon.h"
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#include <malloc.h>
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#include <common.h>
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#include "mvSysHwConfig.h"
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#include "mvCtrlEnvSpec.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*************/
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/* Constants */
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/*************/
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#define MV_OS_WAIT_FOREVER 0
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/*************/
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/* Datatypes */
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/*************/
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#define CPU_PHY_MEM(x) (MV_U32)x
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#define CPU_MEMIO_CACHED_ADDR(x) (void*)x
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#define CPU_MEMIO_UNCACHED_ADDR(x) (void*)x
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/* CPU architecture dependent 32, 16, 8 bit read/write IO addresses */
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#define MV_MEMIO32_WRITE(addr, data) \
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((*((volatile unsigned int*)(addr))) = ((unsigned int)(data)))
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#define MV_MEMIO32_READ(addr) \
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((*((volatile unsigned int*)(addr))))
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#define MV_MEMIO16_WRITE(addr, data) \
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((*((volatile unsigned short*)(addr))) = ((unsigned short)(data)))
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#define MV_MEMIO16_READ(addr) \
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((*((volatile unsigned short*)(addr))))
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#define MV_MEMIO8_WRITE(addr, data) \
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((*((volatile unsigned char*)(addr))) = ((unsigned char)(data)))
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#define MV_MEMIO8_READ(addr) \
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((*((volatile unsigned char*)(addr))))
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/* No Fast Swap implementation (in assembler) for ARM */
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#define MV_32BIT_LE_FAST(val) MV_32BIT_LE(val)
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#define MV_16BIT_LE_FAST(val) MV_16BIT_LE(val)
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#define MV_32BIT_BE_FAST(val) MV_32BIT_BE(val)
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#define MV_16BIT_BE_FAST(val) MV_16BIT_BE(val)
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/* 32 and 16 bit read/write in big/little endian mode */
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/* 16bit write in little endian mode */
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#define MV_MEMIO_LE16_WRITE(addr, data) \
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MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data))
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/* 16bit read in little endian mode */
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static __inline MV_U16 MV_MEMIO_LE16_READ(MV_U32 addr)
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{
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MV_U16 data;
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data= (MV_U16)MV_MEMIO16_READ(addr);
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return (MV_U16)MV_16BIT_LE_FAST(data);
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}
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/* 32bit write in little endian mode */
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#define MV_MEMIO_LE32_WRITE(addr, data) \
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MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data))
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/* 32bit read in little endian mode */
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static __inline MV_U32 MV_MEMIO_LE32_READ(MV_U32 addr)
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{
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MV_U32 data;
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data= (MV_U32)MV_MEMIO32_READ(addr);
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return (MV_U32)MV_32BIT_LE_FAST(data);
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}
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/******************************************************************************
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* This debug function enable the write of each register that u-boot access to
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* to an array in the DRAM, the function record only MV_REG_WRITE access.
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* The function could not be operate when booting from flash.
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* In order to print the array we use the printreg command.
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******************************************************************************/
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/* #define REG_DEBUG */
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#if defined(REG_DEBUG)
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#define REG_ARRAY_SIZE 4096
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extern int reg_arry[REG_ARRAY_SIZE][2];
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extern int reg_arry_index;
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void reglog(unsigned int offset, unsigned int data);
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#endif
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/* Marvell controller register read/write macros */
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#define MV_REG_VALUE(offset) \
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(MV_MEMIO32_READ((INTER_REGS_BASE | (offset))))
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#define MV_REG_READ(offset) \
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(MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset)))
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#if defined(REG_DEBUG)
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#define MV_REG_WRITE(offset, val) \
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MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); \
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reglog((INTER_REGS_BASE | (offset)), (val));
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#else
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#define MV_REG_WRITE(offset, val) \
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MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val));
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#endif
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#if defined(REG_DEBUG)
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#define MV_REG_WORD_WRITE(offset, val) \
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MV_MEMIO_LE16_WRITE((INTER_REGS_BASE | (offset)), (val)); \
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reglog((INTER_REGS_BASE | (offset)), (val));
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#else
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#define MV_REG_WORD_WRITE(offset, val) \
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MV_MEMIO_LE16_WRITE((INTER_REGS_BASE | (offset)), (val))
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#endif
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#define MV_REG_WORD_READ(offset) \
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(MV_MEMIO16_READ((INTER_REGS_BASE | (offset))))
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#define MV_REG_BYTE_READ(offset) \
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(MV_MEMIO8_READ((INTER_REGS_BASE | (offset))))
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#if defined(REG_DEBUG)
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#define MV_REG_BYTE_WRITE(offset, val) \
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MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)); \
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reglog((INTER_REGS_BASE | (offset)), (val));
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#else
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#define MV_REG_BYTE_WRITE(offset, val) \
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MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val))
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#endif
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#if defined(REG_DEBUG)
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#define MV_REG_BIT_SET(offset, bitMask) \
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(MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \
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(MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \
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MV_32BIT_LE_FAST(bitMask)))); \
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reglog((INTER_REGS_BASE | (offset)), (MV_MEMIO32_READ(INTER_REGS_BASE | (offset))));
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#else
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#define MV_REG_BIT_SET(offset, bitMask) \
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(MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \
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(MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \
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MV_32BIT_LE_FAST(bitMask))))
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#endif
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#if defined(REG_DEBUG)
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#define MV_REG_BIT_RESET(offset,bitMask) \
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(MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \
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(MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \
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MV_32BIT_LE_FAST(~bitMask)))); \
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reglog((INTER_REGS_BASE | (offset)), (MV_MEMIO32_READ(INTER_REGS_BASE | (offset))));
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#else
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#define MV_REG_BIT_RESET(offset,bitMask) \
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(MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \
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(MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \
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MV_32BIT_LE_FAST(~bitMask))))
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#endif
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/* Flash APIs */
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#define MV_FL_8_READ MV_MEMIO8_READ
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#define MV_FL_16_READ MV_MEMIO_LE16_READ
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#define MV_FL_32_READ MV_MEMIO_LE32_READ
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#define MV_FL_8_DATA_READ MV_MEMIO8_READ
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#define MV_FL_16_DATA_READ MV_MEMIO16_READ
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#define MV_FL_32_DATA_READ MV_MEMIO32_READ
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#define MV_FL_8_WRITE MV_MEMIO8_WRITE
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#define MV_FL_16_WRITE MV_MEMIO_LE16_WRITE
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#define MV_FL_32_WRITE MV_MEMIO_LE32_WRITE
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#define MV_FL_8_DATA_WRITE MV_MEMIO8_WRITE
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#define MV_FL_16_DATA_WRITE MV_MEMIO16_WRITE
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#define MV_FL_32_DATA_WRITE MV_MEMIO32_WRITE
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/* CPU cache information */
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#define CPU_I_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */
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#define CPU_D_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */
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/* Data cache flush one line */
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#define mvOsCacheLineFlushInv(handle, addr)
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#define mvOsCacheLineInv(handle, addr)
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/* Flush CPU pipe */
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#define CPU_PIPE_FLUSH
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#define INLINE inline
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#define mvOsSPrintf sprintf
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/* In order to minimize image size printf, is defined as NULL */
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#ifdef MV_RT_DEBUG
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# define mvOsPrintf printf
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#else
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# define mvOsPrintf(fmt,args...)
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#endif /* MV_RT_DEBUG */
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#define mvOsOutput printf
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#define mvOsMalloc malloc
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#define mvOsFree free
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#define mvOsMemcpy memcpy
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#define mvOsDelay(ms) udelay(ms*1000)
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#define mvOsSleep(us) mvOsDelay(us)
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#define mvOsTaskLock()
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#define mvOsTaskUnlock()
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#define mvOsIntLock() 0
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#define mvOsIntUnlock(key)
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#define mvOsUDelay(x) udelay(x)
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#define strtol simple_strtoul
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#define mvOsDivide(num, div) \
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({ \
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int i=0, rem=(num); \
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\
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while(rem >= (div)) \
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{ \
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rem -= (div); \
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i++; \
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} \
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(i); \
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})
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#define mvOsReminder(num, div) \
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({ \
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int rem = (num); \
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\
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while(rem >= (div)) \
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rem -= (div); \
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(rem); \
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})
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#if defined(MV_BRIDGE_SYNC_REORDER)
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extern MV_U32 *mvUncachedParam;
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static INLINE void mvOsBridgeReorderWA(void)
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{
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/* sync write reordering in the bridge */
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volatile MV_U32 val = 0;
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val = mvUncachedParam[0];
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}
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#endif
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static INLINE void mvOsBCopy(MV_U8* srcAddr, MV_U8* dstAddr, int byteCount)
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{
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while(byteCount != 0)
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{
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*dstAddr = *srcAddr;
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dstAddr++;
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srcAddr++;
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byteCount--;
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}
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}
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/* ARM architecture APIs */
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MV_U32 mvOsCpuRevGet (MV_VOID);
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MV_U32 mvOsCpuPartGet (MV_VOID);
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MV_U32 mvOsCpuArchGet (MV_VOID);
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MV_U32 mvOsCpuVarGet (MV_VOID);
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MV_U32 mvOsCpuAsciiGet (MV_VOID);
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MV_U32 mvOsIoVirtToPhy( void* osHandle, void* pVirtAddr );
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void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32* memHandle);
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void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle);
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void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32* memHandle);
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void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle);
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MV_U32 mvOsCacheFlush( void* osHandle, void* p, int size );
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MV_U32 mvOsCacheInvalidate( void* osHandle, void* p, int size );
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int mvOsRand(void);
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int mvOsStrCmp(const char *str1,const char *str2);
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#ifdef __cplusplus
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}
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#endif
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||
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#endif /* MV_OS_H */
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