474 lines
18 KiB
C
474 lines
18 KiB
C
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/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef _INC_BOOTSTRAP_OS_H
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#define _INC_BOOTSTRAP_OS_H
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/* BE/ LE swap for Asm */
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#if defined(MV_CPU_LE)
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#define htoll(x) x
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#define HTOLL(sr,tr)
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#elif defined(MV_CPU_BE)
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#define htoll(x) ((((x) & 0x00ff) << 24) | \
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(((x) & 0xff00) << 8) | \
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(((x) >> 8) & 0xff00) | \
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(((x) >> 24) & 0x00ff))
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#define HTOLL(sr,temp) /*sr = A ,B ,C ,D */\
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eor temp, sr, sr, ROR #16 ; /*temp = A^C,B^D,C^A,D^B */\
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bic temp, temp, #0xFF0000 ; /*temp = A^C,0 ,C^A,D^B */\
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mov sr, sr, ROR #8 ; /*sr = D ,A ,B ,C */\
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eor sr, sr, temp, LSR #8 /*sr = D ,C ,B ,A */
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#endif
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#define MV_REG_READ_ASM(toReg, tmpReg, regOffs) \
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ldr tmpReg, =(INTER_REGS_BASE + regOffs) ; \
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ldr toReg, [tmpReg] ; \
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HTOLL(toReg,tmpReg)
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#define MV_REG_WRITE_ASM(fromReg, tmpReg, regOffs) \
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HTOLL(fromReg,tmpReg) ; \
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ldr tmpReg, =(INTER_REGS_BASE + regOffs) ; \
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str fromReg, [tmpReg]
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#define MV_DV_REG_READ_ASM(toReg, tmpReg, regOffs) \
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ldr tmpReg, =(CFG_DFL_MV_REGS + regOffs) ; \
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ldr toReg, [tmpReg] ; \
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HTOLL(toReg,tmpReg)
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#define MV_DV_REG_WRITE_ASM(fromReg, tmpReg, regOffs) \
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HTOLL(fromReg,tmpReg) ; \
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ldr tmpReg, =(CFG_DFL_MV_REGS + regOffs) ; \
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str fromReg, [tmpReg]
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/* Defines */
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/* The following is a list of Marvell status */
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#define MV_ERROR (-1)
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#define MV_OK (0x00) /* Operation succeeded */
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#define MV_FAIL (0x01) /* Operation failed */
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#define MV_BAD_VALUE (0x02) /* Illegal value (general) */
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#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */
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#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */
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#define MV_BAD_PTR (0x05) /* Illegal pointer value */
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#define MV_BAD_SIZE (0x06) /* Illegal size */
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#define MV_BAD_STATE (0x07) /* Illegal state of state machine */
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#define MV_SET_ERROR (0x08) /* Set operation failed */
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#define MV_GET_ERROR (0x09) /* Get operation failed */
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#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */
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#define MV_NOT_FOUND (0x0B) /* Item not found */
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#define MV_NO_MORE (0x0C) /* No more items found */
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#define MV_NO_SUCH (0x0D) /* No such item */
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#define MV_TIMEOUT (0x0E) /* Time Out */
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#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */
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#define MV_NOT_SUPPORTED (0x10) /* This request is not support */
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#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented */
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#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */
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#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
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#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
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#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
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#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */
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#define MV_HW_ERROR (0x17) /* Hardware error */
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#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
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#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
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#define MV_NOT_READY (0x1A) /* The other side is not ready yet */
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#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */
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#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */
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#define MV_NOT_STARTED (0x1D) /* Not started yet */
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#define MV_BUSY (0x1E) /* Item is busy. */
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#define MV_TERMINATE (0x1F) /* Item terminates it's work. */
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#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */
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#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */
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#define MV_WRITE_PROTECT (0x22) /* Write protected */
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#define MV_INVALID (int)(-1)
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#define MV_FALSE 0
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#define MV_TRUE (!(MV_FALSE))
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#ifndef NULL
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#define NULL ((void*)0)
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#endif
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#ifndef MV_ASMLANGUAGE
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/* typedefs */
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typedef char MV_8;
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typedef unsigned char MV_U8;
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typedef int MV_32;
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typedef unsigned int MV_U32;
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typedef short MV_16;
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typedef unsigned short MV_U16;
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#ifdef MV_PPC64
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typedef long MV_64;
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typedef unsigned long MV_U64;
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#else
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typedef long long MV_64;
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typedef unsigned long long MV_U64;
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#endif
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typedef long MV_LONG; /* 32/64 */
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typedef unsigned long MV_ULONG; /* 32/64 */
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typedef int MV_STATUS;
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typedef int MV_BOOL;
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/*typedef void MV_VOID;*/
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#define MV_VOID void
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typedef float MV_FLOAT;
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typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */
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typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */
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typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double*/
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typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */
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typedef MV_U32 MV_KHZ;
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typedef MV_U32 MV_MHZ;
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typedef MV_U32 MV_HZ;
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#if defined(_HOST_COMPILER)
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#define __MV_PACKED
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#else
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#define __MV_PACKED /*__packed*/
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#endif
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#endif /* MV_ASMLANGUAGE */
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/* Bit field definitions */
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#define NO_BIT 0x00000000
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#define BIT0 0x00000001
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#define BIT1 0x00000002
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#define BIT2 0x00000004
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#define BIT3 0x00000008
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#define BIT4 0x00000010
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#define BIT5 0x00000020
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#define BIT6 0x00000040
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#define BIT7 0x00000080
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#define BIT8 0x00000100
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#define BIT9 0x00000200
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#define BIT10 0x00000400
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#define BIT11 0x00000800
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#define BIT12 0x00001000
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#define BIT13 0x00002000
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#define BIT14 0x00004000
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#define BIT15 0x00008000
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#define BIT16 0x00010000
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#define BIT17 0x00020000
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#define BIT18 0x00040000
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#define BIT19 0x00080000
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#define BIT20 0x00100000
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#define BIT21 0x00200000
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#define BIT22 0x00400000
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#define BIT23 0x00800000
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#define BIT24 0x01000000
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#define BIT25 0x02000000
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#define BIT26 0x04000000
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#define BIT27 0x08000000
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#define BIT28 0x10000000
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#define BIT29 0x20000000
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#define BIT30 0x40000000
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#define BIT31 0x80000000
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/* includes */
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#define _1K 0x00000400
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#define _4K 0x00001000
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#define _8K 0x00002000
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#define _16K 0x00004000
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#define _32K 0x00008000
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#define _64K 0x00010000
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#define _128K 0x00020000
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#define _256K 0x00040000
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#define _512K 0x00080000
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/* Sizes */
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#define _1M 0x00100000
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#define _2M 0x00200000
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#define _4M 0x00400000
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#define _8M 0x00800000
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#define _16M 0x01000000
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#define _32M 0x02000000
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#define _64M 0x04000000
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#define _128M 0x08000000
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#define _256M 0x10000000
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#define _512M 0x20000000
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#define _1G 0x40000000
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#define _2G 0x80000000
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/* Speed */
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#define _133MHZ 133333333
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#define _150MHZ 150000000
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#define _166MHZ 166666667
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#define _200MHZ 200000000
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/* Swap tool */
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/* 16bit nibble swap. For example 0x1234 -> 0x2143 */
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#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \
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((X&0xf0) >> 4) | \
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((X&0xf00) << 4) | \
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((X&0xf000) >> 4))
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/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */
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#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \
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((X&0xf0) >> 4) | \
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((X&0xf00) << 4) | \
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((X&0xf000) >> 4) | \
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((X&0xf0000) << 4) | \
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((X&0xf00000) >> 4) | \
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((X&0xf000000) << 4) | \
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((X&0xf0000000) >> 4))
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/* 16bit byte swap. For example 0x1122 -> 0x2211 */
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#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8))
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/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */
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#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \
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(((X)&0xff00)<<8) | \
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(((X)&0xff0000)>>8) | \
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(((X)&0xff000000)>>24))
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/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */
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#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \
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(((X)&0xff00ULL)<<40) | \
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(((X)&0xff0000ULL)<<24) | \
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(((X)&0xff000000ULL)<<8) | \
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(((X)&0xff00000000ULL)>>8) | \
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(((X)&0xff0000000000ULL)>>24) | \
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(((X)&0xff000000000000ULL)>>40) | \
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(((X)&0xff00000000000000ULL)>>56)))
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/* Endianess macros. */
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#if defined(MV_CPU_LE)
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#define MV_16BIT_LE(X) (X)
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#define MV_32BIT_LE(X) (X)
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#define MV_64BIT_LE(X) (X)
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#define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X)
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#define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X)
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#define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X)
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#elif defined(MV_CPU_BE)
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#define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X)
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#define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X)
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#define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X)
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#define MV_16BIT_BE(X) (X)
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#define MV_32BIT_BE(X) (X)
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#define MV_64BIT_BE(X) (X)
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#endif
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#ifndef MV_ASMLANGUAGE
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/* Get the min between 'a' or 'b' */
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#define MV_MIN(a,b) (((a) < (b)) ? (a) : (b))
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/* Marvell controller register read/write macros */
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#define CPU_PHY_MEM(x) (MV_U32)x
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#define CPU_MEMIO_CACHED_ADDR(x) (void*)x
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#define CPU_MEMIO_UNCACHED_ADDR(x) (void*)x
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/* CPU architecture dependent 32, 16, 8 bit read/write IO addresses */
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#define MV_MEMIO32_WRITE(addr, data) \
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((*((volatile unsigned int*)(addr))) = ((unsigned int)(data)))
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#define MV_MEMIO32_READ(addr) \
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((*((volatile unsigned int*)(addr))))
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#define MV_MEMIO16_WRITE(addr, data) \
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((*((volatile unsigned short*)(addr))) = ((unsigned short)(data)))
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#define MV_MEMIO16_READ(addr) \
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((*((volatile unsigned short*)(addr))))
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#define MV_MEMIO8_WRITE(addr, data) \
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((*((volatile unsigned char*)(addr))) = ((unsigned char)(data)))
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#define MV_MEMIO8_READ(addr) \
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((*((volatile unsigned char*)(addr))))
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/* No Fast Swap implementation (in assembler) for ARM */
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#define MV_32BIT_LE_FAST(val) MV_32BIT_LE(val)
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#define MV_16BIT_LE_FAST(val) MV_16BIT_LE(val)
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#define MV_32BIT_BE_FAST(val) MV_32BIT_BE(val)
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#define MV_16BIT_BE_FAST(val) MV_16BIT_BE(val)
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/* 32 and 16 bit read/write in big/little endian mode */
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/* 16bit write in little endian mode */
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#define MV_MEMIO_LE16_WRITE(addr, data) \
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MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data))
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/* 16bit read in little endian mode */
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static __inline MV_U16 MV_MEMIO_LE16_READ(MV_U32 addr)
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{
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MV_U16 data;
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data= (MV_U16)MV_MEMIO16_READ(addr);
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return (MV_U16)MV_16BIT_LE_FAST(data);
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}
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/* 32bit write in little endian mode */
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#define MV_MEMIO_LE32_WRITE(addr, data) \
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MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data))
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/* 32bit read in little endian mode */
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static __inline MV_U32 MV_MEMIO_LE32_READ(MV_U32 addr)
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{
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MV_U32 data;
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data= (MV_U32)MV_MEMIO32_READ(addr);
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return (MV_U32)MV_32BIT_LE_FAST(data);
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}
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/* Flash APIs */
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#define MV_FL_8_READ MV_MEMIO8_READ
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#define MV_FL_16_READ MV_MEMIO_LE16_READ
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#define MV_FL_32_READ MV_MEMIO_LE32_READ
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#define MV_FL_8_DATA_READ MV_MEMIO8_READ
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#define MV_FL_16_DATA_READ MV_MEMIO16_READ
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#define MV_FL_32_DATA_READ MV_MEMIO32_READ
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#define MV_FL_8_WRITE MV_MEMIO8_WRITE
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#define MV_FL_16_WRITE MV_MEMIO_LE16_WRITE
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#define MV_FL_32_WRITE MV_MEMIO_LE32_WRITE
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#define MV_FL_8_DATA_WRITE MV_MEMIO8_WRITE
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#define MV_FL_16_DATA_WRITE MV_MEMIO16_WRITE
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#define MV_FL_32_DATA_WRITE MV_MEMIO32_WRITE
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/* CPU cache information */
|
||
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#define CPU_I_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */
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#define CPU_D_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */
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#define MV_REG_VALUE(offset) \
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(MV_MEMIO32_READ((INTER_REGS_BASE | (offset))))
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#define MV_REG_READ(offset) \
|
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(MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset)))
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#define MV_REG_WRITE(offset, val) \
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||
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MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val))
|
||
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#define MV_REG_BYTE_READ(offset) \
|
||
|
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(MV_MEMIO8_READ((INTER_REGS_BASE | (offset))))
|
||
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#define MV_REG_BYTE_WRITE(offset, val) \
|
||
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MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val))
|
||
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|
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|
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#define MV_REG_SHORT_READ(offset) \
|
||
|
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(MV_MEMIO_LE16_READ(INTER_REGS_BASE | (offset)))
|
||
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||
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|
||
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#define MV_REG_BIT_SET(offset, bitMask) \
|
||
|
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(MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \
|
||
|
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(MV_MEMIO32_READ((INTER_REGS_BASE | (offset))) | \
|
||
|
|
MV_32BIT_LE_FAST((bitMask)))))
|
||
|
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|
||
|
|
#define MV_REG_BIT_RESET(offset,bitMask) \
|
||
|
|
(MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \
|
||
|
|
(MV_MEMIO32_READ((INTER_REGS_BASE | (offset))) & \
|
||
|
|
MV_32BIT_LE_FAST(~(bitMask)))))
|
||
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|
||
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|
||
|
|
#define mvOsDelay(us) uDelay(us*1000)
|
||
|
|
#define mvOsUDelay uDelay
|
||
|
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|
||
|
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|
||
|
|
#define u32 MV_U32
|
||
|
|
#define u16 MV_U16
|
||
|
|
#define u8 MV_U8
|
||
|
|
#define s16 short
|
||
|
|
#define s32 long
|
||
|
|
#define s8 char
|
||
|
|
|
||
|
|
#define UINT32 MV_U32
|
||
|
|
#define UINT16 MV_U16
|
||
|
|
#define UINT8 MV_U8
|
||
|
|
|
||
|
|
typedef UINT32* PUINT32;
|
||
|
|
typedef UINT16* PUINT16;
|
||
|
|
typedef UINT8* PUINT8;
|
||
|
|
|
||
|
|
#define TRUE MV_TRUE
|
||
|
|
#define FALSE MV_FALSE
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
#endif /* #ifndef MV_ASMLANGUAGE */
|
||
|
|
|
||
|
|
#endif /* _INC_BOOTSTRAP_OS_H */
|
||
|
|
|