119 lines
3.6 KiB
C
119 lines
3.6 KiB
C
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/*-
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* Copyright (c) 2007-2008, Juniper Networks, Inc.
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* PCI Configuration Space.
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*/
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#define EHCI_PCICS_BASEC PCI_CLASS_CODE
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#define EHCI_PCICS_SCC PCI_CLASS_SUB_CODE
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#define EHCI_PCICS_PI PCI_CLASS_PROG
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#define EHCI_PCICS_USBBASE PCI_BASE_ADDRESS_0
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#define EHCI_PCICS_SBRN 0x60
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#define EHCI_PCICS_FLADJ 0x61
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#define EHCI_PCICS_PORTWAKECAP 0x62
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#define EHCI_PCICS_USBLEGSUP
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#define EHCI_PCICS_USBLEGCTLSTS
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#define EHCI_PCI_BASEC 0x0c /* Serial Bus Controller. */
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#define EHCI_PCI_SCC 0x03 /* USB Host Controller. */
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#define EHCI_PCI_PI 0x20 /* USB 2.0 Host Controller. */
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/*
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* Register Space.
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*/
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struct ehci_hccr {
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uint8_t cr_caplength;
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uint16_t cr_hciversion;
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uint32_t cr_hcsparams;
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uint32_t cr_hccparams;
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uint8_t cr_hcsp_portrt[8];
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};
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struct ehci_hcor {
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uint32_t or_usbcmd;
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uint32_t or_usbsts;
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uint32_t or_usbintr;
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uint32_t or_frindex;
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uint32_t or_ctrldssegment;
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uint32_t or_periodiclistbase;
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uint32_t or_asynclistaddr;
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uint32_t _reserved_[9];
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uint32_t or_configflag;
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uint32_t or_portsc[2];
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uint32_t _reserved1_[7];
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uint32_t or_usbmode;
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};
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#define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current */
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#define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect */
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#define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect */
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#define EHCI_PS_PTC 0x000f0000 /* RW port test control */
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#define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */
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#define EHCI_PS_PO 0x00002000 /* RW port owner */
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#define EHCI_PS_PP 0x00001000 /* RW,RO port power */
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#define EHCI_PS_LS 0x00000c00 /* RO line status */
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#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400)
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#define EHCI_PS_PR 0x00000100 /* RW port reset */
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#define EHCI_PS_SUSP 0x00000080 /* RW suspend */
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#define EHCI_PS_FPR 0x00000040 /* RW force port resume */
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#define EHCI_PS_OCC 0x00000020 /* RWC over current change */
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#define EHCI_PS_OCA 0x00000010 /* RO over current active */
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#define EHCI_PS_PEC 0x00000008 /* RWC port enable change */
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#define EHCI_PS_PE 0x00000004 /* RW port enable */
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#define EHCI_PS_CSC 0x00000002 /* RWC connect status change */
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#define EHCI_PS_CS 0x00000001 /* RO connect status */
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#define EHCI_PS_CLEAR (EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC)
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#define EHCI_PS_PSPD 0x0c000000 /* RW,RO port power */
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/*
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* Schedule Interface Space.
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*
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* IMPORTANT: Software must ensure that no interface data structure
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* reachable by the EHCI host controller spans a 4K page boundary!
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*
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* Periodic transfers (i.e. isochronous and interrupt transfers) are
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* not supported.
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*/
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/* Queue Element Transfer Descriptor (qTD). */
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struct qTD {
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uint32_t qt_next;
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#define QT_NEXT_TERMINATE 1
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uint32_t qt_altnext;
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uint32_t qt_token;
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uint32_t qt_buffer[5];
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};
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/* Queue Head (QH). */
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struct QH {
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uint32_t qh_link;
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#define QH_LINK_TERMINATE 1
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#define QH_LINK_TYPE_ITD 0
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#define QH_LINK_TYPE_QH 2
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#define QH_LINK_TYPE_SITD 4
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#define QH_LINK_TYPE_FSTN 6
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uint32_t qh_endpt1;
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uint32_t qh_endpt2;
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uint32_t qh_curtd;
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struct qTD qh_overlay;
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};
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