595 lines
14 KiB
C
595 lines
14 KiB
C
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/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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*******************************************************************************/
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/* Code for setting up pagetables or the protection unit,
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* and enabling the cache. */
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#include <config.h>
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#include <common.h>
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#include <asm/types.h>
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#include <command.h>
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#include "mvSysHwConfig.h"
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#if defined(MV_INCLUDE_MONT_EXT) && defined (MV_INCLUDE_MONT_MMU)
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#include "mvCpuIf.h"
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#include "cpu/mvCpu.h"
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int mpuMap(void);
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/* This file refers to the A.R.M.--The ARM Architecture Reference Manual */
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enum access
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{
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NO_ACCESS,
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NO_USR_W,
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SVC_RW,
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ALL_ACCESS
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};
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enum entrytype
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{
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INVALID,
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PAGE,
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SECTION
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};
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#define U_BIT 16
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#define C_BIT 8
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#define B_BIT 4
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#define WRITE_BACK (C_BIT|B_BIT)
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#define WRITE_THROUGH (C_BIT)
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#define L1Entry(type,addr,dom,ucb,acc) \
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( (type == SECTION) ? ( ((addr) & 0xfff00000) | \
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((acc) << 10) | ((dom) << 5) | \
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(ucb) | (type) ) : \
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(type == PAGE) ? ( ((addr) &0xfffffc00) | \
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((dom) << 5) | \
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((ucb) & U_BIT) | (type) ) : \
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0)
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#define L1EntryAddr(type, entry) \
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( (type == SECTION) ? ((entry) & 0xfff00000): \
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(type == PAGE) ? ((entry) &0xfffffc00):0)
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#define L1EntryAcc(type, entry) \
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(((entry) & 0xc00) >> 10)
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#define L1EntryUcb(type, entry) \
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((entry) & 0x1c)
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#define L1EntryType(type, entry) \
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((entry) & 0x3)
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static void detectPageTable(void)
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{
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int i;
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#if defined(MV78XX0)
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unsigned int *p = (unsigned int *)CFG_PT_BASE(whoAmI());
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#else
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unsigned int *p = (unsigned int *)CFG_PT_BASE;
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#endif
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unsigned int entry;
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unsigned int ucb;
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unsigned int acc;
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unsigned int nextEntry;
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char* envCacheMode = getenv("cacheMode");
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unsigned int startVirAddr = 0;
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unsigned int startPhyAddr = 0;
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if(envCacheMode && (strcmp(envCacheMode,"write-through") == 0))
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{
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printf("Cache Mode - write-through\n");
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}
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else /*"write-back"*/
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{
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printf("Cache Mode - write-back\n");
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}
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printf("page table:\n");
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for (i = 0; i < 4096; i++)
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{
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entry = *p;
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nextEntry = *(++p);
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ucb = L1EntryUcb(SECTION, entry);
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acc = L1EntryAcc(SECTION, entry);
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if ( (ucb != L1EntryUcb(SECTION, nextEntry))||
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(acc != L1EntryAcc(SECTION, nextEntry))||
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(L1EntryAddr(SECTION, entry) > L1EntryAddr(SECTION, nextEntry)) ||
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((L1EntryAddr(SECTION, entry) + _1M) < L1EntryAddr(SECTION, nextEntry)))
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{
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printf("Section (0x%08x - 0x%08x) =>",startPhyAddr, ((i << 20)| 0xfffff));
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printf(" (0x%08x - 0x%08x)",startVirAddr, (L1EntryAddr(SECTION, entry)| 0xfffff));
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if (ucb & C_BIT)
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printf(" Cachable/");
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else
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printf(" Non-Cachable/");
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if (ucb & B_BIT)
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printf(" Bufferable");
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else
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printf(" Non-Bufferable");
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switch(acc){
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case(NO_ACCESS):
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printf("\tNO_ACCESS");
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break;
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case(NO_USR_W):
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printf("\tNO_USR_W");
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break;
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case(SVC_RW):
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printf("\tSVC_RW");
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break;
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case(ALL_ACCESS):
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printf("\tALL_ACCESS");
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break;
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default:
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printf("\tALL_ACCESS");
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break;
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}
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printf("\n");
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startVirAddr = L1EntryAddr(SECTION, nextEntry);
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startPhyAddr = ((i+1) << 20);
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}
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}
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}
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static unsigned int createPageTable(void)
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{
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int i;
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unsigned int entry;
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char* envCacheMode = getenv("cacheMode");
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unsigned int cacheMode;
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#if defined(MV78XX0)
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unsigned int *p = (unsigned int *)CFG_PT_BASE(whoAmI());
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#else
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unsigned int *p = (unsigned int *)CFG_PT_BASE;
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#endif
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if(envCacheMode && (strcmp(envCacheMode,"write-through") == 0))
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{
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setenv("cacheMode","write-through");
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cacheMode = WRITE_THROUGH;
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}
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else /*"write-back"*/
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{
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setenv("cacheMode","write-back");
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cacheMode = WRITE_BACK;
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}
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/* first region 0 MB - 0x10000000(256MB) none cacheable/bufferable */
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entry = L1Entry(SECTION, 0, 0, U_BIT, ALL_ACCESS);
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for (i = 0; i < 256; i++)
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{
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*p++ = (entry | (i << 20));
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}
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/* second region 0x10000000 (256MB) - 0x80000000 (2GB) cacheable/bufferable */
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entry = L1Entry(SECTION, 0, 0, U_BIT|cacheMode, ALL_ACCESS);
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for (; i < 2048 ; i++)
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{
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*p++ = (entry | (i << 20));
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}
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/* 3rd region 0x80000000 (2GB) - 0x90000000 cacheable/ bufferable to 0x0*/
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entry = L1Entry(SECTION, 0, 0, U_BIT|cacheMode, ALL_ACCESS);
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for (; i < 2304; i++)
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{
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*p++ = (entry | ((i - 2048) << 20));
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}
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/* 4rd region 0x90000000 - 0xa0000000 not cacheable/not bufferable */
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entry = L1Entry(SECTION, 0, 0, U_BIT, ALL_ACCESS);
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for (; i < 2560; i++)
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{
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*p++ = (entry | (i << 20));
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}
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/* 5th region 0xa0000000 - 0xb0000000 cacheable/bufferable to 0x90000000 */
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entry = L1Entry(SECTION, 0, 0, U_BIT|cacheMode, ALL_ACCESS);
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for (; i < 2816; i++)
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{
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*p++ = (entry | ((i - 256) << 20));
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}
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/* 6th region 0xb0000000 - 0xe0000000 cacheable/bufferable */
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entry = L1Entry(SECTION, 0, 0, U_BIT|cacheMode, ALL_ACCESS);
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for (; i < 3584; i++)
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{
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*p++ = (entry | (i << 20));
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}
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/* 7th region 0xe0000000 - 0xf0000000 cacheable/bufferable to 0xf0000000 */
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entry = L1Entry(SECTION, 0, 0, U_BIT|cacheMode, ALL_ACCESS);
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for (; i < 3840; i++)
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{
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*p++ = (entry | ((i+256) << 20));
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}
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/* 8th region 0xf0000000 - 0xffffffff none cacheable/bufferable */
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entry = L1Entry(SECTION, 0, 0, U_BIT, ALL_ACCESS);
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for (; i < 4096; i++)
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{
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*p++ = (entry | (i << 20));
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}
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#if defined(MV78XX0)
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return CFG_PT_BASE(whoAmI());
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#else
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return CFG_PT_BASE;
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#endif
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}
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extern int PTexist(void);
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int cpumap_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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printf("CPU Memory mapping :\n");
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if ((mvOsCpuPartGet() == CPU_PART_ARM926) ||
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(mvOsCpuPartGet() == CPU_PART_MRVL131))
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{
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if(enaMonExt())
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{
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if(PTexist())
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{
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detectPageTable();
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}
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else
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printf("No page table. \n");
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}
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else
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printf("No page table. \n");
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}
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#ifndef MV_TINY_IMAGE
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#if defined(MV_INCLUDE_MONT_EXT) && defined (MV_INCLUDE_MONT_MPU)
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else if (mvOsCpuPartGet() == CPU_PART_ARM946)
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{
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mpuMap();
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}
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#endif
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#endif
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return 1;
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}
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U_BOOT_CMD(
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cpumap, 1, 1, cpumap_cmd,
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"cpumap - Display CPU memory mapping settings.\n",
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" \n"
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"\tdisplay CPU memory mapping settings.\n"
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);
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/* These are all the bits currently defined for the control register */
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/* A.R.M. 7.4.2 */
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#define MMU_V 0x2000
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#define MMU_I 0x1000
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#define MMU_Z 0x0800
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#define MMU_F 0x0400
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#define MMU_R 0x0200
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#define MMU_S 0x0100
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#define MMU_B 0x0080
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#define MMU_RES 0x50078 /* reserved bits should be 1 */
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#define MMU_C 0x0004
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#define MMU_A 0x0002
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#define MMU_M 0x0001
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/*
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* The functions below take arguments to specify which "caches" the
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* action is to be directed at. For the I-cache, pass "MMU_I". For
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* the D-cache, "MMU_C". For both, pass "MMU_ID". For combined ID-Cache
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* processors, use "MMU_C"
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*/
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#define MMU_ID (MMU_I | MMU_C)
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/*
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* Inline functions for MMU functions
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*/
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/* Set the page tables base register: register 2 (A.R.M. 7.4.3) */
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inline void mmuSetPageTabBase(unsigned int pagetab)
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{
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__asm__ __volatile__(
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"mcr p15, 0, %0, c2, c0\n"
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:
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: "r" (pagetab));
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}
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/* Set the domain access-control register: register 3 (A.R.M. 7.4.4) */
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inline void mmuSetDomainAccessControl(unsigned long flags)
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{
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__asm__ __volatile__(
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"mcr p15, 0, %0, c3, c0\n"
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:
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: "r" (flags));
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}
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/* Flush the cache(s).
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*/
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inline void mmuInvCache(unsigned caches)
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{
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unsigned long dummy = 0;
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switch (caches)
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{
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case MMU_C:
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__asm__ __volatile__(
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"mcr p15, 0, %0, c7, c6, 0\n"
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:
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: "r" (dummy));
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break;
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case MMU_I:
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__asm__ __volatile__(
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"mcr p15, 0, %0, c7, c5, 0\n"
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:
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: "r" (dummy));
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break;
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case MMU_ID:
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__asm__ __volatile__(
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"mcr p15, 0, %0, c7, c7, 0\n"
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:
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: "r" (dummy));
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break;
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}
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}
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/* Flush the TLB(s)
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*/
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inline void mmuFlushTLB( unsigned tlbs)
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{
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unsigned long dummy = 0;
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/* flush TLB(s): write to register 8, with flags (A.R.M. 7.4.9) */
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switch (tlbs)
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{
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case MMU_C:
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__asm__ __volatile__(
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"mcr p15, 0, %0, c8, c6, 0\n"
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:
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: "r" (dummy));
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break;
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case MMU_I:
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__asm__ __volatile__(
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"mcr p15, 0, %0, c8, c5, 0\n"
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:
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: "r" (dummy));
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break;
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case MMU_ID:
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__asm__ __volatile__(
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"mcr p15, 0, %0, c8, c7, 0\n"
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:
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: "r" (dummy));
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Enable the cache/MMU/TLB etc.
|
||
|
|
*/
|
||
|
|
inline void cpuCfgEnable(unsigned long flags, MV_BOOL enable)
|
||
|
|
{
|
||
|
|
unsigned long tmp;
|
||
|
|
|
||
|
|
if (enable == MV_TRUE)
|
||
|
|
{
|
||
|
|
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (tmp));
|
||
|
|
tmp |= flags;
|
||
|
|
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (tmp));
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (tmp));
|
||
|
|
tmp &= ~flags;
|
||
|
|
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (tmp));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Disable the I/D cache.
|
||
|
|
*/
|
||
|
|
|
||
|
|
inline void disableIDCache(void)
|
||
|
|
{
|
||
|
|
unsigned long tmp;
|
||
|
|
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (tmp));
|
||
|
|
tmp &= ~MMU_ID;
|
||
|
|
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (tmp));
|
||
|
|
|
||
|
|
/* invalidate I/D-cache */
|
||
|
|
tmp = 0;
|
||
|
|
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (tmp));
|
||
|
|
}
|
||
|
|
|
||
|
|
/* return 0 in case cache is absent */
|
||
|
|
inline unsigned long getDCacheAssociativity(void)
|
||
|
|
{
|
||
|
|
|
||
|
|
unsigned long tmp, dassoc, mul;
|
||
|
|
|
||
|
|
/* Read cache type information */
|
||
|
|
/* Bit[11:0] - I cache size */
|
||
|
|
/* Bit[23:12] - D cache size */
|
||
|
|
/* Bit 24 - if '1' Seperate I-cache and D-cache */
|
||
|
|
/* bit[28:24] - ctype */
|
||
|
|
asm ("mrc p15, 0, %0, c0, c0, 1":"=r" (tmp));
|
||
|
|
|
||
|
|
/* D cache data only */
|
||
|
|
/* Bit[1:0] - cache line length */
|
||
|
|
/* Bit2 - M */
|
||
|
|
/* Bit[5:3] - cache associativity */
|
||
|
|
/* Bit[9:6] - cache size */
|
||
|
|
tmp = (tmp >> 12) & 0xfff;
|
||
|
|
|
||
|
|
/* Detect cache associativity - the formulae are teken from ARM DDI reference manual */
|
||
|
|
mul = 2 + ((tmp >> 2) & 1);
|
||
|
|
dassoc = ((tmp >> 3) & 0x7);
|
||
|
|
if ((dassoc == 0) && (mul == 2))
|
||
|
|
dassoc = 1;
|
||
|
|
else
|
||
|
|
{
|
||
|
|
if ((dassoc == 0) && (mul == 3))
|
||
|
|
dassoc = 0;
|
||
|
|
else
|
||
|
|
dassoc = mul << (dassoc - 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
return dassoc;
|
||
|
|
}
|
||
|
|
|
||
|
|
inline unsigned long getDCacheSize(void)
|
||
|
|
{
|
||
|
|
|
||
|
|
unsigned long tmp, dsize, mul;
|
||
|
|
|
||
|
|
/* Read cache type information */
|
||
|
|
/* Bit[11:0] - I cache size */
|
||
|
|
/* Bit[23:12] - D cache size */
|
||
|
|
/* Bit 24 - if '1' Seperate I-cache and D-cache */
|
||
|
|
/* bit[28:24] - ctype */
|
||
|
|
asm ("mrc p15, 0, %0, c0, c0, 1":"=r" (tmp));
|
||
|
|
|
||
|
|
/* D cache data only */
|
||
|
|
/* Bit[1:0] - cache line length */
|
||
|
|
/* Bit2 - M */
|
||
|
|
/* Bit[5:3] - cache associativity */
|
||
|
|
/* Bit[9:6] - cache size */
|
||
|
|
tmp = (tmp >> 12) & 0xfff;
|
||
|
|
|
||
|
|
/* Detect cache size - the formulae are teken from ARM DDI reference manual */
|
||
|
|
mul = 2 + ((tmp >> 2) & 1);
|
||
|
|
dsize = ((tmp >> 6) & 0xf);
|
||
|
|
dsize = mul << (dsize + 8);
|
||
|
|
|
||
|
|
return dsize;
|
||
|
|
}
|
||
|
|
|
||
|
|
inline unsigned long getDCacheLine(void)
|
||
|
|
{
|
||
|
|
|
||
|
|
unsigned long tmp, dline;
|
||
|
|
|
||
|
|
/* Read cache type information */
|
||
|
|
/* Bit[11:0] - I cache size */
|
||
|
|
/* Bit[23:12] - D cache size */
|
||
|
|
/* Bit 24 - if '1' Seperate I-cache and D-cache */
|
||
|
|
/* bit[28:24] - ctype */
|
||
|
|
asm ("mrc p15, 0, %0, c0, c0, 1":"=r" (tmp));
|
||
|
|
|
||
|
|
/* D cache data only */
|
||
|
|
/* Bit[1:0] - cache line length */
|
||
|
|
/* Bit2 - M */
|
||
|
|
/* Bit[5:3] - cache associativity */
|
||
|
|
/* Bit[9:6] - cache size */
|
||
|
|
tmp = (tmp >> 12) & 0xfff;
|
||
|
|
|
||
|
|
/* Detect cache line - the formulae are teken from ARM DDI reference manual */
|
||
|
|
dline = 1 << ((tmp & 0x3) + 3);
|
||
|
|
|
||
|
|
return dline;
|
||
|
|
}
|
||
|
|
|
||
|
|
extern ulong _dcache_index_max;
|
||
|
|
extern ulong _dcache_index_inc;
|
||
|
|
extern ulong _dcache_set_max;
|
||
|
|
extern ulong _dcache_set_index;
|
||
|
|
|
||
|
|
void pageTableInit(void)
|
||
|
|
{
|
||
|
|
unsigned long dsize, dassoc, dline, log2Assoc, tmp;
|
||
|
|
|
||
|
|
printf("D-Cache type information\n");
|
||
|
|
|
||
|
|
/* Detect cache size */
|
||
|
|
dsize = getDCacheSize();
|
||
|
|
/* Detect cache number of way */
|
||
|
|
dassoc = getDCacheAssociativity();
|
||
|
|
/* Detect cache number of way */
|
||
|
|
dline = getDCacheLine();
|
||
|
|
|
||
|
|
/* Detected cache absent */
|
||
|
|
if (dassoc == 0)
|
||
|
|
{
|
||
|
|
printf("DCache absent!\n");
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
printf("DCache size: %dKB\n",dsize/1024);
|
||
|
|
printf("DCache associativity: %d way\n",dassoc);
|
||
|
|
printf("DCache line length: %dB\n",dline);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/* Calc num of digits for assoc representation */
|
||
|
|
log2Assoc = 0;
|
||
|
|
tmp = dassoc - 1;
|
||
|
|
do
|
||
|
|
{
|
||
|
|
log2Assoc++;
|
||
|
|
tmp = tmp >> 1;
|
||
|
|
}while (tmp > 0);
|
||
|
|
|
||
|
|
printf("Intializing Page Table...");
|
||
|
|
|
||
|
|
/* The num of assoc is set in the ip address from bit 31 backward */
|
||
|
|
if (dassoc == 1)
|
||
|
|
{
|
||
|
|
_dcache_index_max = 0;
|
||
|
|
_dcache_index_inc = 0;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
_dcache_index_max = ~ ((1 << (31 - log2Assoc + 1)) - 1);
|
||
|
|
_dcache_index_inc = (1 << (31 - log2Assoc + 1));
|
||
|
|
}
|
||
|
|
|
||
|
|
_dcache_set_max = (dsize/dassoc) - dline;
|
||
|
|
_dcache_set_index = dline;
|
||
|
|
|
||
|
|
disableIDCache();
|
||
|
|
/* Disable D cache and MMU. */
|
||
|
|
cpuCfgEnable(MMU_C | MMU_M, MV_FALSE);
|
||
|
|
/* set up the page table, domain control registers */
|
||
|
|
mmuSetPageTabBase(createPageTable());
|
||
|
|
mmuSetDomainAccessControl(3);
|
||
|
|
/* flush caches and TLBs */
|
||
|
|
mmuInvCache(MMU_ID);
|
||
|
|
mmuFlushTLB(MMU_ID);
|
||
|
|
/* write to control register :-
|
||
|
|
* I-cache on, 32-bit data and program space,
|
||
|
|
* write-buffer on, D-cache on, MMU on
|
||
|
|
*/
|
||
|
|
cpuCfgEnable(MMU_I | MMU_RES | MMU_C | MMU_M, MV_TRUE);
|
||
|
|
|
||
|
|
printf("Done \n");
|
||
|
|
return ;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* defined(MV_INCLUDE_MONT_EXT) */
|
||
|
|
|
||
|
|
|
||
|
|
|