212 lines
6.6 KiB
C
212 lines
6.6 KiB
C
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#define MUSTANG_SDHC_BASE 0xf1080000 // from 00-4c
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#define INTEGRATOR_GPIO_BASE 0x1b000000
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//#define SC_BASE
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#define P(x) (MUSTANG_SDHC_BASE + (2 * x))
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#define GPIO_REG_READ32(addr) (*(volatile unsigned int*)(INTEGRATOR_GPIO_BASE+addr))
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#define GPIO_REG_WRITE32(addr, val) (*(volatile unsigned int*)(INTEGRATOR_GPIO_BASE+addr)=val)
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#define SDIO_REG_WRITE16(addr,val) (*(volatile unsigned short*)(P(addr)) = val)
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#define SDIO_REG_READ16(addr) (*(volatile unsigned short*)(P(addr)))
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/* SDIO register offset */
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#define SDIO_SYS_ADDR_LOW 0x000
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#define SDIO_SYS_ADDR_HI 0x002
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#define SDIO_BLK_SIZE 0x004
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#define SDIO_BLK_COUNT 0x006
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#define SDIO_ARG_LOW 0x008
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#define SDIO_ARG_HI 0x00A
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#define SDIO_XFER_MODE 0x00C
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#define SDIO_CMD 0x00E
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#define SDIO_RSP0 0x010
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#define SDIO_RSP1 0x012
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#define SDIO_RSP2 0x014
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#define SDIO_RSP3 0x016
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#define SDIO_RSP4 0x018
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#define SDIO_RSP5 0x01A
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#define SDIO_RSP6 0x01C
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#define SDIO_RSP7 0x01E
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#define SDIO_BUF_DATA_PORT 0x020
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#define SDIO_RSVED 0x022
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#define SDIO_PRESENT_STATE0 0x024
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#define CARD_BUSY ((unsigned short)(0x1 << 1))
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#define SDIO_PRESENT_STATE1 0x026
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#define SDIO_HOST_CTRL 0x028
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#define SDIO_BLK_GAP_CTRL 0x02A
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#define SDIO_CLK_CTRL 0x02C
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#define SDIO_SW_RESET 0x02E
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#define SDIO_NOR_INTR_STATUS 0x030
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#define SDIO_ERR_INTR_STATUS 0x032
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#define SDIO_NOR_STATUS_EN 0x034
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#define SDIO_ERR_STATUS_EN 0x036
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#define SDIO_NOR_INTR_EN 0x038
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#define SDIO_ERR_INTR_EN 0x03A
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#define SDIO_AUTOCMD12_ERR_STATUS 0x03C
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#define SDIO_CURR_BLK_SIZE 0x03E
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#define SDIO_CURR_BLK_COUNT 0x040
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#define SDIO_AUTOCMD12_ARG_LOW 0x042
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#define SDIO_AUTOCMD12_ARG_HI 0x044
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#define SDIO_AUTOCMD12_INDEX 0x046
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#define SDIO_AUTO_RSP0 0x048
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#define SDIO_AUTO_RSP1 0x04A
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#define SDIO_AUTO_RSP2 0x04C
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/************** SDIO_HOST_CTRL ****/
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#define SDIO_HOST_CTRL_PUSH_PULL_EN 1
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#define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY 0
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#define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY (1<<1)
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#define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO (2<<1)
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#define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC (3<<1)
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#define SDIO_HOST_CTRL_BIG_ENDAN (1<<3)
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#define SDIO_HOST_CTRL_LSB_FIRST (1<<4)
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#define SDIO_HOST_CTRL_ID_MODE_LOW_FREQ (1<<5)
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#define SDIO_HOST_CTRL_HALF_SPEED (1<<6)
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#define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS (1<<9)
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#define SDIO_HOST_CTRL_HI_SPEED_EN (1<<10)
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#define SDIO_HOST_CTRL_TMOUT_SHIFT 11
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#define SDIO_HOST_CTRL_TMOUT_EN (1<<15)
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#define SDIO_HOST_CTRL_DFAULT_OPEN_DRAIN (0xF<<SDIO_HOST_CTRL_TMOUT_SHIFT)
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#define SDIO_HOST_CTRL_DFAULT_PUSH_PULL ((0xF<<SDIO_HOST_CTRL_TMOUT_SHIFT)|SDIO_HOST_CTRL_PUSH_PULL_EN)
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/* nor status mask */
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#define SDIO_NOR_UNEXP_RSP ((unsigned short)0x1 << 14)
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#define SDIO_NOR_AUTOCMD12_DONE ((unsigned short)0x1 << 13)
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#define SDIO_NOR_SUSPENSE_ON ((unsigned short)0x1 << 12)
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#define SDIO_NOR_LMB_FF_8W_AVAIL ((unsigned short)0x1 << 11)
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#define SDIO_NOR_LMB_FF_8W_FILLED ((unsigned short)0x1 << 10)
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#define SDIO_NOR_READ_WAIT_ON ((unsigned short)0x1 << 9)
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#define SDIO_NOR_CARD_INT ((unsigned short)0x1 << 8)
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#define SDIO_NOR_READ_READY ((unsigned short)0x1 << 5)
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#define SDIO_NOR_WRITE_READY ((unsigned short)0x1 << 4)
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#define SDIO_NOR_DMA_INI ((unsigned short)0x1 << 3)
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#define SDIO_NOR_BLK_GAP_EVT ((unsigned short)0x1 << 2)
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#define SDIO_NOR_XFER_DONE ((unsigned short)0x1 << 1)
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#define SDIO_NOR_CMD_DONE ((unsigned short)0x1 << 0)
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/* err status mask */
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#define SDIO_ERR_CRC_STATUS ((unsigned short)0x1 << 14)
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#define SDIO_ERR_CRC_STARTBIT ((unsigned short)0x1 << 13)
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#define SDIO_ERR_CRC_ENDBIT ((unsigned short)0x1 << 12)
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#define SDIO_ERR_RESP_TBIT ((unsigned short)0x1 << 11)
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#define SDIO_ERR_SIZE ((unsigned short)0x1 << 10)
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#define SDIO_ERR_CMD_STARTBIT ((unsigned short)0x1 << 9)
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#define SDIO_ERR_AUTOCMD12 ((unsigned short)0x1 << 8)
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#define SDIO_ERR_DATA_ENDBIT ((unsigned short)0x1 << 6)
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#define SDIO_ERR_DATA_CRC ((unsigned short)0x1 << 5)
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#define SDIO_ERR_DATA_TIMEOUT ((unsigned short)0x1 << 4)
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#define SDIO_ERR_CMD_INDEX ((unsigned short)0x1 << 3)
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#define SDIO_ERR_CMD_ENDBIT ((unsigned short)0x1 << 2)
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#define SDIO_ERR_CMD_CRC ((unsigned short)0x1 << 1)
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#define SDIO_ERR_CMD_TIMEOUT ((unsigned short)0x1 << 0)
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#define SDIO_ERR_INTR_MASK 0xFFFF
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#define SDIO_CMD_RSP_NONE ((unsigned short)0x0)
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#define SDIO_CMD_RSP_136 ((unsigned short)0x1)
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#define SDIO_CMD_RSP_48 ((unsigned short)0x2)
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#define SDIO_CMD_RSP_48BUSY ((unsigned short)0x3)
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#define MMC_BLOCK_SIZE 512
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#define MMC_CMD_RESET 0
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#define MMC_CMD_SEND_OP_COND 1
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#define MMC_CMD_ALL_SEND_CID 2
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#define MMC_CMD_SET_RCA 3
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#define MMC_CMD_SELECT_CARD 7
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#define MMC_CMD_SEND_CSD 9
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#define MMC_CMD_SEND_CID 10
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#define MMC_CMD_SEND_STATUS 13
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#define MMC_CMD_SET_BLOCKLEN 16
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#define MMC_CMD_READ_BLOCK 17
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#define MMC_CMD_RD_BLK_MULTI 18
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#define MMC_CMD_WRITE_BLOCK 24
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#define MMC_MAX_BLOCK_SIZE 512
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//*****************************************************************************
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// GPIO definition for SD host controller
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// GPIO1 => EXTINT1 (IRQ24) a can be used as SD_CARD_IN
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// GPIO6 => can be used as SD_WP
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// GPIO7 => can be used as SD_ON
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#define SDHC_GPIO_CARD_IN 0x00000002
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#define SDHC_GPIO_WP 0x00000040
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#define SDHC_GPIO_POWER 0x00000080
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#define MUSTANG_GPIO_DIRECTION_OFFSET 8
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#define MUSTANG_GPIO_CLEAR_OFFSET 4
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#define MUSTANG_GPIO_SET_OFFSET 0
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#define MUSTANG_GPIO_DATAIN 0
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//SC Flag bit 0 for Card Detection
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// if bit 0 of 0x11000030 is zero,
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// Card Insertion interrupt will be detected
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// if bit 0 of 0x11000030 is 1
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// card Removal interrupt will be detected
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#define MUSTANG_SCFLAG_STATUS_OFFSET 0x0
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#define MUSTANG_SCFLAG_SET_OFFSET 0x0
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#define MUSTANG_SCFLAG_CLEAR_OFFSET 0x4
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#define MUSTANG_SD_CARDDET_TOGGLE_BIT 0x1
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typedef struct mmc_cid
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{
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/* FIXME: BYTE_ORDER */
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uchar year:4,
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month:4;
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uchar sn[3];
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uchar fwrev:4,
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hwrev:4;
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uchar name[6];
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uchar id[3];
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} mmc_cid_t;
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typedef struct mmc_csd
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{
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uchar ecc:2,
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file_format:2,
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tmp_write_protect:1,
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perm_write_protect:1,
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copy:1,
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file_format_grp:1;
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uint64_t content_prot_app:1,
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rsvd3:4,
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write_bl_partial:1,
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write_bl_len:4,
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r2w_factor:3,
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default_ecc:2,
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wp_grp_enable:1,
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wp_grp_size:5,
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erase_grp_mult:5,
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erase_grp_size:5,
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c_size_mult1:3,
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vdd_w_curr_max:3,
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vdd_w_curr_min:3,
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vdd_r_curr_max:3,
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vdd_r_curr_min:3,
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c_size:12,
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rsvd2:2,
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dsr_imp:1,
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read_blk_misalign:1,
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write_blk_misalign:1,
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read_bl_partial:1;
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ushort read_bl_len:4,
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ccc:12;
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uchar tran_speed;
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uchar nsac;
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uchar taac;
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uchar rsvd1:2,
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spec_vers:4,
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csd_structure:2;
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} mmc_csd_t;
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