208 lines
7.5 KiB
C
208 lines
7.5 KiB
C
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "mvOs.h"
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#include "mvCpuCntrs.h"
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const static MV_CPU_CNTRS_OPS mvCpuCntrsOpsTbl[MV_CPU_CNTRS_NUM][MV_CPU_CNTRS_OPS_NUM] =
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{
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/*0*/
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{
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MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_HIT, MV_CPU_CNTRS_DCACHE_READ_MISS,
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MV_CPU_CNTRS_DCACHE_WRITE_HIT, MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_INSTRUCTIONS,
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MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID,
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MV_CPU_CNTRS_MMU_READ_LATENCY, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_LATENCY,
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MV_CPU_CNTRS_LDM_STM_HOLD, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID,
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MV_CPU_CNTRS_DATA_WRITE_ACCESS, MV_CPU_CNTRS_DATA_READ_ACCESS, MV_CPU_CNTRS_INVALID,
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MV_CPU_CNTRS_BRANCH_PREDICT_COUNT,
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},
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/*1*/
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{
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MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_ICACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_READ_MISS,
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MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_ITLB_MISS, MV_CPU_CNTRS_SINGLE_ISSUE,
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MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_RETIRED, MV_CPU_CNTRS_INVALID,
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MV_CPU_CNTRS_MMU_READ_BEAT, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_BEAT,
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MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_IS_HOLD, MV_CPU_CNTRS_DATA_READ_ACCESS,
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MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID,
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MV_CPU_CNTRS_INVALID,
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},
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/*2*/
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{
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MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_ACCESS,
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MV_CPU_CNTRS_DTLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID,
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MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_PREDICT_MISS, MV_CPU_CNTRS_WB_WRITE_BEAT,
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MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_LATENCY, MV_CPU_CNTRS_DCACHE_WRITE_LATENCY,
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MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_SIMULT_ACCESS,
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MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID,
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MV_CPU_CNTRS_INVALID,
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},
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/*3*/
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{
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MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_WRITE_MISS,
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MV_CPU_CNTRS_TLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID,
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MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_TAKEN, MV_CPU_CNTRS_WB_FULL_CYCLES,
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MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_BEAT, MV_CPU_CNTRS_DCACHE_WRITE_BEAT,
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MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_ANY_ACCESS,
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MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DATA_WRITE_ACCESS,
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MV_CPU_CNTRS_INVALID,
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}
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};
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MV_CPU_CNTRS_ENTRY mvCpuCntrsTbl[MV_CPU_CNTRS_NUM];
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MV_CPU_CNTRS_EVENT* mvCpuCntrsEventTbl[128];
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void mvCpuCntrsReset(void)
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{
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MV_U32 reg = 0;
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MV_ASM ("mcr p15, 0, %0, c15, c13, 0" : : "r" (reg));
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MV_ASM ("mcr p15, 0, %0, c15, c13, 1" : : "r" (reg));
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MV_ASM ("mcr p15, 0, %0, c15, c13, 2" : : "r" (reg));
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MV_ASM ("mcr p15, 0, %0, c15, c13, 3" : : "r" (reg));
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MV_ASM ("mcr p15, 0, %0, c15, c13, 4" : : "r" (reg));
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MV_ASM ("mcr p15, 0, %0, c15, c13, 5" : : "r" (reg));
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MV_ASM ("mcr p15, 0, %0, c15, c13, 6" : : "r" (reg));
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MV_ASM ("mcr p15, 0, %0, c15, c13, 7" : : "r" (reg));
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}
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void program_counter(int counter, int op)
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{
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MV_U32 reg = (1 << op) | 0x1; /*enable*/
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switch(counter)
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{
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case 0:
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__asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 0" : : "r" (reg));
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return;
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case 1:
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__asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 1" : : "r" (reg));
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return;
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case 2:
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__asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 2" : : "r" (reg));
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return;
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case 3:
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__asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 3" : : "r" (reg));
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return;
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default:
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mvOsPrintf("error in program_counter: bad counter number (%d)\n", counter);
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}
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return;
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}
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void mvCpuCntrsEventClear(MV_CPU_CNTRS_EVENT* pEvent)
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{
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int i;
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for(i=0; i<MV_CPU_CNTRS_NUM; i++)
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{
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pEvent->counters_sum[i] = 0;
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}
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pEvent->num_of_measurements = 0;
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}
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MV_CPU_CNTRS_EVENT* mvCpuCntrsEventCreate(char* name, MV_U32 print_threshold)
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{
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int i;
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MV_CPU_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_CNTRS_EVENT));
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if(event)
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{
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strncpy(event->name, name, sizeof(event->name));
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event->num_of_measurements = 0;
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event->avg_sample_count = print_threshold;
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for(i=0; i<MV_CPU_CNTRS_NUM; i++)
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{
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event->counters_before[i] = 0;
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event->counters_after[i] = 0;
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event->counters_sum[i] = 0;
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}
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}
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return event;
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}
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void mvCpuCntrsEventDelete(MV_CPU_CNTRS_EVENT* event)
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{
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if(event != NULL)
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mvOsFree(event);
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}
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MV_STATUS mvCpuCntrsProgram(int counter, MV_CPU_CNTRS_OPS op,
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char* name, MV_U32 overhead)
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{
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int i;
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/* Find required operations */
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for(i=0; i<MV_CPU_CNTRS_OPS_NUM; i++)
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{
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if( mvCpuCntrsOpsTbl[counter][i] == op)
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{
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strncpy(mvCpuCntrsTbl[counter].name, name, sizeof(mvCpuCntrsTbl[counter].name));
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mvCpuCntrsTbl[counter].operation = op;
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mvCpuCntrsTbl[counter].opIdx = i+1;
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mvCpuCntrsTbl[counter].overhead = overhead;
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program_counter(counter, mvCpuCntrsTbl[counter].opIdx);
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mvOsPrintf("Counter=%d, opIdx=%d, overhead=%d\n",
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counter, mvCpuCntrsTbl[counter].opIdx, mvCpuCntrsTbl[counter].overhead);
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return MV_OK;
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}
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}
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return MV_NOT_FOUND;
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}
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void mvCpuCntrsShow(MV_CPU_CNTRS_EVENT* pEvent)
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{
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int i;
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MV_U64 counters_avg;
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if(pEvent->num_of_measurements < pEvent->avg_sample_count)
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return;
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mvOsPrintf("%16s: ", pEvent->name);
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for(i=0; i<MV_CPU_CNTRS_NUM; i++)
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{
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counters_avg = mvOsDivMod64(pEvent->counters_sum[i],
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pEvent->num_of_measurements, NULL);
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if(counters_avg >= mvCpuCntrsTbl[i].overhead)
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counters_avg -= mvCpuCntrsTbl[i].overhead;
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else
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counters_avg = 0;
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mvOsPrintf("%s=%5llu, ", mvCpuCntrsTbl[i].name, counters_avg);
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}
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mvOsPrintf("\n");
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mvCpuCntrsEventClear(pEvent);
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mvCpuCntrsReset();
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}
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void mvCpuCntrsStatus(void)
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{
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int i;
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for(i=0; i<MV_CPU_CNTRS_NUM; i++)
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{
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mvOsPrintf("#%d: %s, overhead=%d\n",
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i, mvCpuCntrsTbl[i].name, mvCpuCntrsTbl[i].overhead);
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}
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}
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