530 lines
20 KiB
ArmAsm
530 lines
20 KiB
ArmAsm
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/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/*******************************************************************************
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* mvDramIfBasicAsm.s
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*
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* DESCRIPTION:
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* Memory full detection and best timing configuration is done in
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* C code. C runtime environment requires a stack. This module API
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* initialize DRAM interface chip select 0 for basic functionality for
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* the use of stack.
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* The module API assumes DRAM information is stored in I2C EEPROM reside
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* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM
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* internal data structure is assumed to be orgenzied in common DRAM
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* vendor SPD structure.
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* NOTE: DFCDL values are assumed to be already initialized prior to
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* this module API activity.
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*
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*
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* DEPENDENCIES:
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* None.
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*
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*******************************************************************************/
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/* includes */
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#define _ASMLANGUAGE
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#define MV_ASMLANGUAGE
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#include "mvOsAsm.h"
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#include "mvSysHwConfig.h"
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#include "mvDramIfRegs.h"
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#include "mvDramIfConfig.h"
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#include "ctrlEnv/sys/mvCpuIfRegs.h"
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#include "pex/mvPexRegs.h"
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#include "ctrlEnv/mvCtrlEnvSpec.h"
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#include "mvCommon.h"
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/* defines */
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/* locals */
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.data
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.globl _mvDramIfConfig
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.text
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.globl _mvDramIfMemInit
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/*******************************************************************************
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* _mvDramIfConfig - Basic DRAM interface initialization.
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*
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* DESCRIPTION:
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* The function will initialize the following DRAM parameters using the
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* values prepared by mvDramIfDetect routine. Values are located
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* in predefined registers.
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*
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* INPUT:
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* None.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* None.
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*
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*******************************************************************************/
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_mvDramIfConfig:
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/* Save register on stack */
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cmp sp, #0
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beq no_stack_s
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save_on_stack:
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stmdb sp!, {r1, r2, r3, r4}
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no_stack_s:
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/* Dunit FTDLL Configuration Register */
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/* 0) Write to SDRAM FTDLL coniguration register */
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ldr r4, = SDRAM_FTDLL_REG_DEFAULT_LEFT;
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ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_LEFT_REG)
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str r4, [r1]
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ldr r4, = SDRAM_FTDLL_REG_DEFAULT_RIGHT;
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ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_RIGHT_REG)
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str r4, [r1]
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ldr r4, = SDRAM_FTDLL_REG_DEFAULT_UP;
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ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_UP_REG)
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str r4, [r1]
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/* 1) Write to SDRAM coniguration register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG)
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str r4, [r1]
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/* 2) Write Dunit control low register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG)
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str r4, [r1]
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/* 2) Write Dunit control high register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG13)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_HI_REG)
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str r4, [r1]
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/* 3) Write SDRAM address control register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG)
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str r4, [r1]
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#if defined(MV_STATIC_DRAM_ON_BOARD)
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/* 4) Write SDRAM bank 0 size register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0,0))
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str r4, [r1]
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#endif
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/* 5) Write SDRAM open pages control register */
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ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG)
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ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV
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str r4, [r1]
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/* 6) Write SDRAM timing Low register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG)
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str r4, [r1]
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/* 7) Write SDRAM timing High register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG)
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str r4, [r1]
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/* Config DDR2 On Die Termination (ODT) registers */
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/* Write SDRAM DDR2 ODT control low register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG)
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str r4, [r1]
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/* Write SDRAM DDR2 ODT control high register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG)
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str r4, [r1]
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/* Write SDRAM DDR2 Dunit ODT control register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG)
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str r4, [r1]
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/* Write DDR2 SDRAM timing Low register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG11)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_LO_REG)
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str r4, [r1]
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/* Write DDR2 SDRAM timing High register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG12)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_HI_REG)
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str r4, [r1]
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/* 8) Write SDRAM mode register */
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/* The CPU must not attempt to change the SDRAM Mode register setting */
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/* prior to DRAM controller completion of the DRAM initialization */
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/* sequence. To guarantee this restriction, it is recommended that */
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/* the CPU sets the SDRAM Operation register to NOP command, performs */
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/* read polling until the register is back in Normal operation value, */
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/* and then sets SDRAM Mode register to its new value. */
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/* 8.1 write 'nop' to SDRAM operation */
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mov r4, #0x5 /* 'NOP' command */
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MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG)
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/* 8.2 poll SDRAM operation. Make sure its back to normal operation */
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_sdramOpPoll1:
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ldr r4, [r1]
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cmp r4, #0 /* '0' = Normal SDRAM Mode */
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bne _sdramOpPoll1
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/* 8.3 Now its safe to write new value to SDRAM Mode register */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG)
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str r4, [r1]
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/* 8.4 Make the Dunit write the DRAM its new mode */
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mov r4, #0x3 /* Mode Register Set command */
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MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
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/* 8.5 poll SDRAM operation. Make sure its back to normal operation */
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_sdramOpPoll2:
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ldr r4, [r1]
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cmp r4, #0 /* '0' = Normal SDRAM Mode */
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bne _sdramOpPoll2
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/* Now its safe to write new value to SDRAM Extended Mode regist */
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ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10)
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ldr r4, [r1]
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ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG)
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str r4, [r1]
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/* 9) Write SDRAM Extended mode register This operation should be */
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/* done for each memory bank */
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/* write 'nop' to SDRAM operation */
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mov r4, #0x5 /* 'NOP' command */
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MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
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/* poll SDRAM operation. Make sure its back to normal operation */
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_sdramOpPoll3:
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ldr r4, [r1]
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cmp r4, #0 /* '0' = Normal SDRAM Mode */
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bne _sdramOpPoll3
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/* Go over each of the Banks */
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ldr r3, =0 /* r3 = DRAM bank Num */
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extModeLoop:
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/* Set the SDRAM Operation Control to each of the DRAM banks */
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mov r4, r3 /* Do not swap the bank counter value */
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MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_CTRL_REG)
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/* Make the Dunit write the DRAM its new mode */
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mov r4, #0x4 /* Extended Mode Register Set command */
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MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
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/* poll SDRAM operation. Make sure its back to normal operation */
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_sdramOpPoll4:
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ldr r4, [r1]
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cmp r4, #0 /* '0' = Normal SDRAM Mode */
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bne _sdramOpPoll4
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add r3, r3, #1
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cmp r3, #4 /* 4 = Number of banks */
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bne extModeLoop
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extModeEnd:
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cmp sp, #0
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beq no_stack_l
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mov r1, LR /* Save link register */
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#if defined(MV78XX0)
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bl _mvDramIfMemInit
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#endif
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mov LR,r1 /* restore link register */
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load_from_stack:
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/* Restore registers */
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ldmia sp!, {r1, r2, r3, r4}
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no_stack_l:
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mov pc, lr
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/*******************************************************************************
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* _mvDramIfEccMemInit - Basic DRAM ECC initialization.
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*
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* DESCRIPTION:
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*
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* INPUT:
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* None.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* None.
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*
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*******************************************************************************/
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#define XOR_CHAN0 0 /* XOR channel 0 used for memory initialization */
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#define XOR_UNIT0 0 /* XOR unit 0 used for memory initialization */
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#define XOR_ADDR_DEC_WIN0 0 /* Enable DRAM access using XOR decode window 0 */
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/* XOR engine register offsets macros */
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#define XOR_CONFIG_REG(chan) (XOR_UNIT_BASE(0) + 0x10 + ((chan) * 4))
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#define XOR_ACTIVATION_REG(chan) (XOR_UNIT_BASE(0) + 0x20 + ((chan) * 4))
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#define XOR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x30)
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#define XOR_ERROR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x50)
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#define XOR_ERROR_ADDR_REG (XOR_UNIT_BASE(0) + 0x60)
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#define XOR_INIT_VAL_LOW_REG (XOR_UNIT_BASE(0) + 0x2E0)
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#define XOR_INIT_VAL_HIGH_REG (XOR_UNIT_BASE(0) + 0x2E4)
|
||
|
|
#define XOR_DST_PTR_REG(chan) (XOR_UNIT_BASE(0) + 0x2B0 + ((chan) * 4))
|
||
|
|
#define XOR_BLOCK_SIZE_REG(chan) (XOR_UNIT_BASE(0) + 0x2C0 + ((chan) * 4))
|
||
|
|
|
||
|
|
/* XOR Engine Address Decoding Register Map */
|
||
|
|
#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4)))
|
||
|
|
#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4)))
|
||
|
|
#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4)))
|
||
|
|
|
||
|
|
.globl _mvDramIfEccMemInit
|
||
|
|
/*******************************************************************************
|
||
|
|
* _mvDramIfEccMemInit - mem init for dram cs
|
||
|
|
*
|
||
|
|
* DESCRIPTION:
|
||
|
|
* This function will clean the cs by ussing the XOR mem init.
|
||
|
|
*
|
||
|
|
* INPUT:
|
||
|
|
* r0 - dram bank number.
|
||
|
|
*
|
||
|
|
* OUTPUT:
|
||
|
|
* none
|
||
|
|
*/
|
||
|
|
_mvDramIfEccMemInit:
|
||
|
|
|
||
|
|
/* Save register on stack */
|
||
|
|
cmp sp, #0
|
||
|
|
beq no_stack_s1
|
||
|
|
save_on_stack1:
|
||
|
|
stmdb sp!, {r0,r1, r2, r3, r4, r5, r6}
|
||
|
|
no_stack_s1:
|
||
|
|
|
||
|
|
ldr r1, = 0
|
||
|
|
|
||
|
|
/* Disable all XOR address decode windows to avoid possible overlap */
|
||
|
|
MV_REG_WRITE_ASM (r1, r5, (XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0)))
|
||
|
|
|
||
|
|
/* Init r5 to first XOR_SIZE_MASK_REG */
|
||
|
|
mov r5, r0, LSL #3
|
||
|
|
add r5, r5,#0x1500
|
||
|
|
add r5, r5,#0x04
|
||
|
|
add r5, r5,#(INTER_REGS_BASE)
|
||
|
|
ldr r6, [r5]
|
||
|
|
HTOLL(r6,r5)
|
||
|
|
MV_REG_WRITE_ASM (r6, r5, XOR_SIZE_MASK_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0))
|
||
|
|
|
||
|
|
mov r5, r0, LSL #3
|
||
|
|
add r5, r5,#0x1500
|
||
|
|
add r5, r5,#(INTER_REGS_BASE)
|
||
|
|
ldr r6, [r5]
|
||
|
|
HTOLL(r6,r5)
|
||
|
|
/* Update destination & size */
|
||
|
|
MV_REG_WRITE_ASM(r6, r5, XOR_DST_PTR_REG(XOR_CHAN0))
|
||
|
|
HTOLL(r6,r5)
|
||
|
|
/* Init r6 to first XOR_BASE_ADDR_REG */
|
||
|
|
ldr r4, = 0xf
|
||
|
|
ldr r5, = 0x1
|
||
|
|
mov r5, r5, LSL r0
|
||
|
|
bic r4, r4, r5
|
||
|
|
mov r4, r4, LSL #8
|
||
|
|
|
||
|
|
orr r6, r6, r4
|
||
|
|
MV_REG_WRITE_ASM (r6, r5, XOR_BASE_ADDR_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0))
|
||
|
|
|
||
|
|
ldr r6, = 0xff0001
|
||
|
|
MV_REG_WRITE_ASM (r6, r5, XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0))
|
||
|
|
|
||
|
|
/* Configure XOR engine for memory init function. */
|
||
|
|
MV_REG_READ_ASM (r6, r5, XOR_CONFIG_REG(XOR_CHAN0))
|
||
|
|
and r6, r6, #~0x7 /* Clear operation mode field */
|
||
|
|
orr r6, r6, #0x4 /* Set operation to memory init */
|
||
|
|
MV_REG_WRITE_ASM(r6, r5, XOR_CONFIG_REG(XOR_CHAN0))
|
||
|
|
|
||
|
|
/* Set initVal in the XOR Engine Initial Value Registers */
|
||
|
|
ldr r6, = 0xfeedfeed
|
||
|
|
MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_LOW_REG)
|
||
|
|
ldr r6, = 0xfeedfeed
|
||
|
|
MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_HIGH_REG)
|
||
|
|
|
||
|
|
/* Set block size using DRAM bank size */
|
||
|
|
|
||
|
|
mov r5, r0, LSL #3
|
||
|
|
add r5, r5,#0x1500
|
||
|
|
add r5, r5,#0x04
|
||
|
|
add r5, r5,#(INTER_REGS_BASE)
|
||
|
|
|
||
|
|
ldr r6, [r5]
|
||
|
|
HTOLL(r6,r5)
|
||
|
|
and r6, r6, #SCSR_SIZE_MASK
|
||
|
|
mov r5, r6, LSR #SCSR_SIZE_OFFS
|
||
|
|
add r5, r5, #1
|
||
|
|
mov r6, r5, LSL #SCSR_SIZE_OFFS
|
||
|
|
MV_REG_WRITE_ASM(r6, r5, XOR_BLOCK_SIZE_REG(XOR_CHAN0))
|
||
|
|
|
||
|
|
/* Clean interrupt cause*/
|
||
|
|
MV_REG_WRITE_ASM(r1, r5, XOR_CAUSE_REG)
|
||
|
|
|
||
|
|
/* Clean error interrupt cause*/
|
||
|
|
MV_REG_READ_ASM(r6, r5, XOR_ERROR_CAUSE_REG)
|
||
|
|
MV_REG_READ_ASM(r6, r5, XOR_ERROR_ADDR_REG)
|
||
|
|
|
||
|
|
/* Start transfer */
|
||
|
|
MV_REG_READ_ASM (r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0))
|
||
|
|
orr r6, r6, #0x1 /* Preform start command */
|
||
|
|
MV_REG_WRITE_ASM(r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0))
|
||
|
|
|
||
|
|
/* Wait for engine to finish */
|
||
|
|
waitForComplete:
|
||
|
|
MV_REG_READ_ASM(r6, r5, XOR_CAUSE_REG)
|
||
|
|
and r6, r6, #2
|
||
|
|
cmp r6, #0
|
||
|
|
beq waitForComplete
|
||
|
|
|
||
|
|
/* Clear all error report registers */
|
||
|
|
MV_REG_WRITE_ASM(r1, r5, SDRAM_SINGLE_BIT_ERR_CNTR_REG)
|
||
|
|
MV_REG_WRITE_ASM(r1, r5, SDRAM_DOUBLE_BIT_ERR_CNTR_REG)
|
||
|
|
|
||
|
|
MV_REG_WRITE_ASM(r1, r5, SDRAM_ERROR_CAUSE_REG)
|
||
|
|
|
||
|
|
cmp sp, #0
|
||
|
|
beq no_stack_l1
|
||
|
|
load_from_stack1:
|
||
|
|
ldmia sp!, {r0, r1, r2, r3, r4, r5, r6}
|
||
|
|
no_stack_l1:
|
||
|
|
mov pc, lr
|
||
|
|
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* mvDramIfMemInit - Use XOR to clear all memory.
|
||
|
|
*
|
||
|
|
* DESCRIPTION:
|
||
|
|
* Use assembler function _mvDramIfEccMemInit to fill all memory with FEADFEAD pattern.
|
||
|
|
* INPUT:
|
||
|
|
* None.
|
||
|
|
*
|
||
|
|
* OUTPUT:
|
||
|
|
* None.
|
||
|
|
*
|
||
|
|
* RETURN:
|
||
|
|
* None.
|
||
|
|
*
|
||
|
|
*******************************************************************************/
|
||
|
|
#if defined(MV78XX0)
|
||
|
|
|
||
|
|
_mvDramIfMemInit:
|
||
|
|
stmdb sp!, {r0,r1, r2, r3, r4, r5, r6}
|
||
|
|
mov r6, LR /* Save link register */
|
||
|
|
/* Check if dram bank 0 has to be init for ECC */
|
||
|
|
MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,0))
|
||
|
|
and r3, r0, #SCSR_WIN_EN
|
||
|
|
cmp r3, #0
|
||
|
|
beq no_bank_0
|
||
|
|
MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,0))
|
||
|
|
cmp r0, #0
|
||
|
|
beq no_bank_0
|
||
|
|
mov r0,#0
|
||
|
|
bl _mvDramIfEccMemInit
|
||
|
|
|
||
|
|
no_bank_0:
|
||
|
|
/* Check if dram bank 1 has to be init for ECC */
|
||
|
|
MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,1))
|
||
|
|
and r0, r0, #SCSR_WIN_EN
|
||
|
|
cmp r0, #0
|
||
|
|
beq no_bank_1
|
||
|
|
mov r0,#1
|
||
|
|
bl _mvDramIfEccMemInit
|
||
|
|
no_bank_1:
|
||
|
|
/* Check if dram bank 2 has to be init for ECC */
|
||
|
|
MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,2))
|
||
|
|
and r0, r0, #SCSR_WIN_EN
|
||
|
|
cmp r0, #0
|
||
|
|
beq no_bank_2
|
||
|
|
MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,2))
|
||
|
|
cmp r0, #0
|
||
|
|
beq no_bank_2
|
||
|
|
mov r0,#2
|
||
|
|
bl _mvDramIfEccMemInit
|
||
|
|
|
||
|
|
no_bank_2:
|
||
|
|
/* Check if dram bank 3 has to be init for ECC */
|
||
|
|
MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,3))
|
||
|
|
and r0, r0, #SCSR_WIN_EN
|
||
|
|
cmp r0, #0
|
||
|
|
beq no_bank_3
|
||
|
|
mov r0,#3
|
||
|
|
bl _mvDramIfEccMemInit
|
||
|
|
no_bank_3:
|
||
|
|
mov LR ,r6 /* restore link register */
|
||
|
|
ldmia sp!, {r0, r1, r2, r3, r4, r5, r6}
|
||
|
|
mov pc, lr
|
||
|
|
#endif
|
||
|
|
|