193 lines
7.2 KiB
C
193 lines
7.2 KiB
C
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/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __INCmvDram
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#define __INCmvDram
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#include "ddr2/mvDramIf.h"
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#include "twsi/mvTwsi.h"
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#define MAX_DIMM_NUM 2
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#define SPD_SIZE 128
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/* Dimm spd offsets */
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#define DIMM_MEM_TYPE 2
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#define DIMM_ROW_NUM 3
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#define DIMM_COL_NUM 4
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#define DIMM_MODULE_BANK_NUM 5
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#define DIMM_DATA_WIDTH 6
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#define DIMM_VOLT_IF 8
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#define DIMM_MIN_CC_AT_MAX_CAS 9
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#define DIMM_ERR_CHECK_TYPE 11
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#define DIMM_REFRESH_INTERVAL 12
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#define DIMM_SDRAM_WIDTH 13
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#define DIMM_ERR_CHECK_DATA_WIDTH 14
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#define DIMM_MIN_CLK_DEL 15
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#define DIMM_BURST_LEN_SUP 16
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#define DIMM_DEV_BANK_NUM 17
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#define DIMM_SUP_CAL 18
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#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */
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#define DIMM_BUF_ADDR_CONT_IN 21
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#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23
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#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25
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#define DIMM_MIN_ROW_PRECHARGE_TIME 27
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#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28
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#define DIMM_MIN_RAS_TO_CAS_DELAY 29
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#define DIMM_MIN_RAS_PULSE_WIDTH 30
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#define DIMM_BANK_DENSITY 31
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#define DIMM_MIN_WRITE_RECOVERY_TIME 36
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#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37
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#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38
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#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42
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#define DIMM_SPD_VERSION 62
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/* Dimm Memory Type values */
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#define DIMM_MEM_TYPE_SDRAM 0x4
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#define DIMM_MEM_TYPE_DDR1 0x7
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#define DIMM_MEM_TYPE_DDR2 0x8
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#define DIMM_MODULE_MANU_OFFS 64
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#define DIMM_MODULE_MANU_SIZE 8
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#define DIMM_MODULE_VEN_OFFS 73
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#define DIMM_MODULE_VEN_SIZE 25
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#define DIMM_MODULE_ID_OFFS 99
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#define DIMM_MODULE_ID_SIZE 18
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/* enumeration for voltage levels. */
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typedef enum _mvDimmVoltageIf
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{
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TTL_5V_TOLERANT,
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LVTTL,
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HSTL_1_5V,
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SSTL_3_3V,
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SSTL_2_5V,
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VOLTAGE_UNKNOWN,
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} MV_DIMM_VOLTAGE_IF;
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/* enumaration for SDRAM CAS Latencies. */
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typedef enum _mvDimmSdramCas
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{
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SD_CL_1 =1,
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SD_CL_2,
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SD_CL_3,
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SD_CL_4,
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SD_CL_5,
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SD_CL_6,
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SD_CL_7,
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SD_FAULT
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}MV_DIMM_SDRAM_CAS;
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/* DIMM information structure */
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typedef struct _mvDimmInfo
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{
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MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */
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MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */
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/* DIMM dimensions */
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MV_U32 numOfRowAddr;
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MV_U32 numOfColAddr;
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MV_U32 numOfModuleBanks;
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MV_U32 dataWidth;
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MV_U32 errorCheckType; /* ECC , PARITY..*/
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MV_U32 sdramWidth; /* 4,8,16 or 32 */
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MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */
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MV_U32 burstLengthSupported;
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MV_U32 numOfBanksOnEachDevice;
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MV_U32 suportedCasLatencies;
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MV_U32 refreshInterval;
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MV_U32 dimmBankDensity;
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MV_U32 dimmTypeInfo; /* DDR2 only */
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MV_U32 dimmAttributes;
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/* DIMM timing parameters */
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MV_U32 minCycleTimeAtMaxCasLatPs;
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MV_U32 minCycleTimeAtMaxCasLatMinus1Ps;
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MV_U32 minCycleTimeAtMaxCasLatMinus2Ps;
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MV_U32 minRowPrechargeTime;
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MV_U32 minRowActiveToRowActive;
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MV_U32 minRasToCasDelay;
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MV_U32 minRasPulseWidth;
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MV_U32 minWriteRecoveryTime; /* DDR2 only */
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MV_U32 minWriteToReadCmdDelay; /* DDR2 only */
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MV_U32 minReadToPrechCmdDelay; /* DDR2 only */
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MV_U32 minRefreshToActiveCmd; /* DDR2 only */
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/* Parameters calculated from the extracted DIMM information */
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MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */
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MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */
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MV_U32 numberOfDevices;
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} MV_DIMM_INFO;
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MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo);
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MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo);
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MV_VOID dimmSpdPrint(MV_U32 dimmNum);
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MV_STATUS dimmSpdCpy(MV_VOID);
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#endif /* __INCmvDram */
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