459 lines
17 KiB
C
459 lines
17 KiB
C
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/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/*******************************************************************************
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* mvIdma.c - Implementation file for IDMA HW library
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*
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* DESCRIPTION:
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* This file contains Marvell Controller IDMA HW library API
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* implementation.
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* NOTE:
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* 1) This HW library API assumes IDMA source, destination and
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* descriptors are cache coherent.
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* 2) In order to gain high performance, the API does not parform
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* API parameter checking.
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*
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* DEPENDENCIES:
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* None.
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*
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*******************************************************************************/
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#include "idma/mvIdma.h"
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/* defines */
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#ifdef MV_DEBUG
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#define DB(x) x
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#else
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#define DB(x)
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#endif
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/*******************************************************************************
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* mvDmaInit - Initialize IDMA engine
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*
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* DESCRIPTION:
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* This function initialize IDMA unit.
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* INPUT:
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* None.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* MV_ERROR if setting fail.
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*******************************************************************************/
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MV_VOID mvDmaHalInit(MV_U32 dmaChanNum)
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{
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MV_U32 i;
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/* Abort any DMA activity */
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for(i = 0; i < dmaChanNum; i++)
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{
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mvDmaCommandSet(i, MV_STOP);
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#if defined(MV_CPU_LE) || defined(MV78XX0)
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/* The following must be set */
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mvDmaCtrlHighSet(i, (ICCHR_ENDIAN_LITTLE
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#if defined(MV_CPU_LE)
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| ICCHR_DESC_BYTE_SWAP_EN
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#endif /* MV_CPU_LE */
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));
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#endif /* MV_CPU_LE || MV78XX0 */
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}
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MV_REG_WRITE( IDMA_CAUSE_REG, 0);
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}
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/*******************************************************************************
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* mvDmaCtrlLowSet - Set IDMA channel control low register
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*
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* DESCRIPTION:
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* Each IDMA Channel has its own unique control registers (high and low)
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* where certain IDMA modes are programmed.
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* This function writes 32bit word to IDMA control low register.
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*
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* !!!!!! WARNING !!!!!!
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* If system uses the IDMA DRAM HW cache coherency the source and
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* destination maximum DTL size must be cache line size.
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*
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* INPUT:
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* chan - DMA channel number. See MV_DMA_CHANNEL enumerator.
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* ctrlWord - Channel control word for low register.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* MV_OK
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*
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* NOTE: This function can modified the Override attribute that mvDmaOverrideSet
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* configured.
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*******************************************************************************/
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MV_STATUS mvDmaCtrlLowSet(MV_U32 chan, MV_U32 ctrlWord)
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{
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MV_REG_WRITE(IDMA_CTRL_LOW_REG(chan), ctrlWord);
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return MV_OK;
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}
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/*******************************************************************************
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* mvDmaCtrlHighSet - Set IDMA channel control high register
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*
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* DESCRIPTION:
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* Each IDMA Channel has its own unique control registers (high and low)
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* where certain IDMA modes are programmed.
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* This function writes 32bit word to IDMA control high register.
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*
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* INPUT:
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* chan - DMA channel number. See MV_DMA_CHANNEL enumerator.
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* ctrlWord - Channel control word for high register.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* MV_OK.
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*
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*******************************************************************************/
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MV_STATUS mvDmaCtrlHighSet(MV_U32 chan, MV_U32 ctrlWord)
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{
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MV_REG_WRITE(IDMA_CTRL_HIGH_REG(chan), ctrlWord);
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return MV_OK;
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}
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/*******************************************************************************
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* mvDmaTransfer - Transfer data from source to destination
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*
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* DESCRIPTION:
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* This function initiates IDMA channel, according to function parameters,
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* in order to perform DMA transaction.
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* This routine supports both chain and none chained DMA modes.
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* To use the function in chain mode just set phyNextDesc parameter with
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* chain second descriptor address (the first one is given in other
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* function paarameters). Otherwise (none chain mode) set it to NULL.
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* To gain maximum performance the user is asked to keep the following
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* restrictions:
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* 1) Selected engine is available (not busy).
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* 1) This module does not take into consideration CPU MMU issues.
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* In order for the IDMA engine to access the appropreate source
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* and destination, address parameters must be given in system
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* physical mode.
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* 2) This API does not take care of cache coherency issues. The source,
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* destination and in case of chain the descriptor list are assumed
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* to be cache coherent.
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* 3) In case of chain mode, the API does not align the user descriptor
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* chain. Instead, the user must make sure the descriptor chain is
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* aligned according to IDMA rquirements.
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* 4) Parameters validity. For example, does size parameter exceeds
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* maximum byte count of descriptor mode (16M or 64K).
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*
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* INPUT:
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* chan - DMA channel number. See MV_DMA_CHANNEL enumerator.
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* phySrc - Physical source address.
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* phyDst - Physical destination address.
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* size - The total number of bytes to transfer.
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* *pPhyNextDesc - Physical address pointer to 2nd descriptor in chain.
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* In case of none chain mode set it to NULL.
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*
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* OUTPUT:
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* None.
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*
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* RETURS:
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* MV_OK.
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*
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*******************************************************************************/
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MV_STATUS mvDmaTransfer(MV_U32 chan, MV_U32 phySrc, MV_U32 phyDst, MV_U32 size,
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MV_U32 phyNextDescPtr)
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{
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/* Set byte count register */
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MV_REG_WRITE(IDMA_BYTE_COUNT_REG(chan), size);
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/* Set source address register */
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MV_REG_WRITE(IDMA_SRC_ADDR_REG(chan), phySrc);
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/* Set destination address register */
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MV_REG_WRITE(IDMA_DST_ADDR_REG(chan), phyDst);
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/* UnLock the Source address in dma operation */
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MV_REG_BIT_RESET(IDMA_CTRL_LOW_REG(chan), ICCLR_SRC_HOLD);
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if (0 != phyNextDescPtr)
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{ /* Chain mode. Set next descriptor register */
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MV_REG_WRITE(IDMA_NEXT_DESC_PTR_REG(chan), phyNextDescPtr);
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}
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/* Start DMA */
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MV_REG_BIT_SET(IDMA_CTRL_LOW_REG(chan), ICCLR_CHAN_ENABLE);
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return MV_OK;
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}
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/*******************************************************************************
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* mvDmaMemInit - Initialize a memory buffer with a given 64bit value pattern
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*
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* DESCRIPTION:
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* This function initiates IDMA channel, according to function parameters,
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* in order to perform DMA transaction for the purpose of initializing a
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* memory buffer with a user supplied pattern.
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* This routine supports both chain and none chained DMA modes.
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* To use the function in chain mode just set phyNextDesc parameter with
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* chain second descriptor address (the first one is given in other
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* function paarameters). Otherwise (none chain mode) set it to NULL.
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* To gain maximum performance the user is asked to keep the following
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* restrictions:
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* 1) Selected engine is available (not busy).
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* 1) This module does not take into consideration CPU MMU issues.
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* In order for the IDMA engine to access the appropreate source
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* and destination, address parameters must be given in system
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* physical mode.
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* 2) This API does not take care of cache coherency issues. The source,
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* destination and in case of chain the descriptor list are assumed
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* to be cache coherent.
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* 3) No chain mode support.
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* 4) Parameters validity. For example, does size parameter exceeds
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* maximum byte count of descriptor mode (16M or 64K).
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*
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* INPUT:
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* chan - DMA channel number. See MV_DMA_CHANNEL enumerator.
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* ptrnPtr - Physical source address of the 64bit pattern
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* startPtr - Physical destinaation address to start with
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* size - The total number of bytes to transfer.
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*
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* OUTPUT:
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* None.
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*
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* RETURS:
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* MV_OK.
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*
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*******************************************************************************/
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MV_STATUS mvDmaMemInit(MV_U32 chan, MV_U32 ptrnPtr, MV_U32 startPtr, MV_U32 size)
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{
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/* Set byte count register */
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MV_REG_WRITE(IDMA_BYTE_COUNT_REG(chan), size);
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/* Set source address register */
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MV_REG_WRITE(IDMA_SRC_ADDR_REG(chan), ptrnPtr);
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/* Set destination address register */
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MV_REG_WRITE(IDMA_DST_ADDR_REG(chan), startPtr);
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/* Lock the Source address in dma operation */
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MV_REG_BIT_SET(IDMA_CTRL_LOW_REG(chan), ICCLR_SRC_HOLD);
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/* Start DMA */
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MV_REG_BIT_SET(IDMA_CTRL_LOW_REG(chan), ICCLR_CHAN_ENABLE);
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return MV_OK;
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}
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/*******************************************************************************
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* mvDmaStateGet - Get IDMA channel status.
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*
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* DESCRIPTION:
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* DMA channel status can be active, stopped, paused.
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* This function retrunes the channel status.
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*
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* INPUT:
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* chan - IDMA channel number. See MV_DMA_CHANNEL enumerator.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* One of MV_STATE enumerator values.
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*
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*******************************************************************************/
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MV_STATE mvDmaStateGet(MV_U32 chan)
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{
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MV_U32 ctrlLow;
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/* Read control low register */
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ctrlLow = MV_REG_READ(IDMA_CTRL_LOW_REG(chan));
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/* Leave only enable/active bits */
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ctrlLow &= (ICCLR_CHAN_ENABLE | ICCLR_CHAN_ACTIVE);
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/* If channel is enabled and active then its running */
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if (ctrlLow == (ICCLR_CHAN_ENABLE | ICCLR_CHAN_ACTIVE))
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{
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return MV_ACTIVE;
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}
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/* If channel is disabled but active then its paused */
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else if (ctrlLow == ICCLR_CHAN_ACTIVE)
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{
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return MV_PAUSED;
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}
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else
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{
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return MV_IDLE;
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}
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}
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/*******************************************************************************
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* mvDmaCommandSet - Set command to DMA channel
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*
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* DESCRIPTION:
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* DMA channel can be started, idel, paused and restarted.
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* Paused can be set only if channel is active.
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* Start can be set only if channel is idle.
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* Restart can be set only if channel is paused.
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* Stop activate the channel abort which cause the DMA to aborts in the
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* middle of a transaction.
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*
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* INPUT:
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* chan - IDMA channel number. See MV_DMA_CHANNEL enumerator.
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* command - Requested command. See MV_COMMAND enumerator.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* MV_ERROR if requested command can not be set.
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*
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*******************************************************************************/
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MV_STATUS mvDmaCommandSet(MV_U32 chan, MV_COMMAND command)
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{
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MV_U32 ctrlLow;
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MV_U32 dmaStatus;
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/* Read control low register */
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ctrlLow = MV_REG_READ(IDMA_CTRL_LOW_REG(chan));
|
||
|
|
|
||
|
|
/* Get current DMA status */
|
||
|
|
dmaStatus = mvDmaStateGet(chan);
|
||
|
|
|
||
|
|
if ((command == MV_START) && (dmaStatus == MV_IDLE))
|
||
|
|
{
|
||
|
|
/* To start, set DMA channel enable bit */
|
||
|
|
ctrlLow |= ICCLR_CHAN_ENABLE;
|
||
|
|
}
|
||
|
|
else if ((command == MV_PAUSE) && (dmaStatus == MV_ACTIVE))
|
||
|
|
{
|
||
|
|
/* To pause, reset DMA channel enable bit */
|
||
|
|
ctrlLow &= ~ICCLR_CHAN_ENABLE;
|
||
|
|
}
|
||
|
|
else if ((command == MV_RESTART) && (dmaStatus == MV_PAUSED))
|
||
|
|
{
|
||
|
|
/* To restart, set DMA channel enable bit */
|
||
|
|
ctrlLow |= ICCLR_CHAN_ENABLE;
|
||
|
|
}
|
||
|
|
else if (command == MV_STOP)
|
||
|
|
{
|
||
|
|
/* To stop, set DMA channel abort bit */
|
||
|
|
ctrlLow |= ICCLR_CHANNEL_ABORT;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
DB(mvOsPrintf("mvDmaCommandSet: ERR. Can not set command %d in \
|
||
|
|
status %d\n", command, dmaStatus));
|
||
|
|
return MV_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Write control word to register */
|
||
|
|
MV_REG_WRITE(IDMA_CTRL_LOW_REG(chan), ctrlLow);
|
||
|
|
|
||
|
|
/* If comman is stop, ensure channel is stopped */
|
||
|
|
if (command == MV_STOP)
|
||
|
|
{
|
||
|
|
while(MV_IDLE != mvDmaStateGet(chan));
|
||
|
|
}
|
||
|
|
|
||
|
|
return MV_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/************ DEBUG ***********/
|
||
|
|
MV_VOID mvIdmaRegs(MV_U32 chan)
|
||
|
|
{
|
||
|
|
mvOsPrintf("\t IDMA #%d Registers:\n", chan);
|
||
|
|
|
||
|
|
mvOsPrintf("IDMA_BYTE_COUNT_REG : 0x%X = 0x%08x\n",
|
||
|
|
IDMA_BYTE_COUNT_REG(chan),
|
||
|
|
MV_REG_READ( IDMA_BYTE_COUNT_REG(chan) ) );
|
||
|
|
|
||
|
|
mvOsPrintf("IDMA_SRC_ADDR_REG : 0x%X = 0x%08x\n",
|
||
|
|
IDMA_SRC_ADDR_REG(chan),
|
||
|
|
MV_REG_READ( IDMA_SRC_ADDR_REG(chan) ) );
|
||
|
|
|
||
|
|
mvOsPrintf("IDMA_DST_ADDR_REG : 0x%X = 0x%08x\n",
|
||
|
|
IDMA_DST_ADDR_REG(chan),
|
||
|
|
MV_REG_READ( IDMA_DST_ADDR_REG(chan) ) );
|
||
|
|
|
||
|
|
mvOsPrintf("IDMA_NEXT_DESC_PTR_REG : 0x%X = 0x%08x\n",
|
||
|
|
IDMA_NEXT_DESC_PTR_REG(chan),
|
||
|
|
MV_REG_READ( IDMA_NEXT_DESC_PTR_REG(chan) ) );
|
||
|
|
|
||
|
|
mvOsPrintf("IDMA_CURR_DESC_PTR_REG : 0x%X = 0x%08x\n",
|
||
|
|
IDMA_CURR_DESC_PTR_REG(chan),
|
||
|
|
MV_REG_READ( IDMA_CURR_DESC_PTR_REG(chan) ) );
|
||
|
|
|
||
|
|
mvOsPrintf("IDMA_CTRL_LOW_REG : 0x%X = 0x%08x\n",
|
||
|
|
IDMA_CTRL_LOW_REG(chan),
|
||
|
|
MV_REG_READ( IDMA_CTRL_LOW_REG(chan) ) );
|
||
|
|
|
||
|
|
mvOsPrintf("IDMA_CTRL_HIGH_REG : 0x%X = 0x%08x\n",
|
||
|
|
IDMA_CTRL_HIGH_REG(chan),
|
||
|
|
MV_REG_READ( IDMA_CTRL_HIGH_REG(chan) ) );
|
||
|
|
|
||
|
|
mvOsPrintf("IDMA_CAUSE_REG : 0x%X = 0x%08x\n",
|
||
|
|
IDMA_CAUSE_REG,
|
||
|
|
MV_REG_READ( IDMA_CAUSE_REG ) );
|
||
|
|
|
||
|
|
mvOsPrintf("IDMA_MASK_REG : 0x%X = 0x%08x\n",
|
||
|
|
IDMA_MASK_REG,
|
||
|
|
MV_REG_READ( IDMA_MASK_REG ) );
|
||
|
|
}
|
||
|
|
|