314 lines
11 KiB
C
314 lines
11 KiB
C
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/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#include "mvPex.h"
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//#define MV_DEBUG
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/* defines */
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#ifdef MV_DEBUG
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#define DB(x) x
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#else
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#define DB(x)
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#endif
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/* locals */
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typedef struct
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{
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MV_U32 data;
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MV_U32 mask;
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}PEX_HEADER_DATA;
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/* local function forwad decleration */
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MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func,
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MV_U32 regOff);
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MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev,
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MV_U32 func, MV_U32 regOff, MV_U32 data);
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void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev);
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PEX_HEADER_DATA configHdr[16] =
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{
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{0x888811ab, 0x00000000}, /*[device ID, vendor ID] */
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{0x00100007, 0x0000ffff}, /*[status register, command register] */
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{0x0604000e, 0x00000000}, /*[programming interface, sub class code, class code, revision ID] */
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{0x00010008, 0x00000000}, /*[BIST, header type, latency time, cache line] */
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{0x00000000, 0x00000000}, /*[base address 0] */
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{0x00000000, 0x00000000}, /*[base address 1] */
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{0x00000000, 0x00ffffff}, /*[secondary latency timersubordinate bus number, secondary bus number, primary bus number] */
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{0x0000f101, 0x00000000}, /*[secondary status ,IO limit, IO base] */
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{0x9ff0a000, 0x00000000}, /*[memory limit, memory base] */
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{0x0001fff1, 0x00000000}, /*[prefetch memory limit, prefetch memory base] */
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{0xffffffff, 0x00000000}, /*[prefetch memory base upper] */
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{0x00000000, 0x00000000}, /*[prefetch memory limit upper] */
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{0xeffff000, 0x00000000}, /*[IO limit upper 16 bits, IO base upper 16 bits] */
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{0x00000000, 0x00000000}, /*[reserved, capability pointer] */
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{0x00000000, 0x00000000}, /*[expansion ROM base address] */
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{0x00000000, 0x000000FF}, /*[bridge control, interrupt pin, interrupt line] */
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};
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#define HEADER_WRITE(data, offset) configHdr[offset/4].data = ((configHdr[offset/4].data & ~configHdr[offset/4].mask) | \
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(data & configHdr[offset/4].mask))
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#define HEADER_READ(offset) configHdr[offset/4].data
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/*******************************************************************************
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* mvVrtBrgPexInit - Initialize PEX interfaces
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*
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* DESCRIPTION:
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*
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* This function is responsible of intialization of the Pex Interface , It
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* configure the Pex Bars and Windows in the following manner:
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*
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* Assumptions :
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* Bar0 is always internal registers bar
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* Bar1 is always the DRAM bar
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* Bar2 is always the Device bar
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*
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* 1) Sets the Internal registers bar base by obtaining the base from
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* the CPU Interface
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* 2) Sets the DRAM bar base and size by getting the base and size from
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* the CPU Interface when the size is the sum of all enabled DRAM
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* chip selects and the base is the base of CS0 .
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* 3) Sets the Device bar base and size by getting these values from the
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* CPU Interface when the base is the base of the lowest base of the
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* Device chip selects, and the
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*
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*
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* INPUT:
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*
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* pexIf - PEX interface number.
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*
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM
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*
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*******************************************************************************/
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MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf)
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{
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/* reset PEX tree to recover previous U-boot/Boot configurations */
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MV_U32 localBus = mvPexLocalBusNumGet(pexIf);
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resetPexConfig(pexIf, localBus, 1);
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return MV_OK;
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}
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MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func,
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MV_U32 regOff)
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{
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MV_U32 localBus = mvPexLocalBusNumGet(pexIf);
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MV_U32 localDev = mvPexLocalDevNumGet(pexIf);
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MV_U32 val;
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if(bus == localBus)
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{
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if(dev > 1)
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{
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/* on the local device allow only device #0 & #1 */
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return 0xffffffff;
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}
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else
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if (dev == localDev)
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{
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/* read the memory controller registers */
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return mvPexHwConfigRead (pexIf, bus, dev, func, regOff);
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}
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else
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{
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/* access the virtual brg header */
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return HEADER_READ(regOff);
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}
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}
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else
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if(bus == (localBus + 1))
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{
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/* access the device behind the virtual bridge */
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if((dev == localDev) || (dev > 1))
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{
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return 0xffffffff;
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}
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else
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{
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/* access the device behind the virtual bridge, in this case
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* change the bus number to the local bus number in order to
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* generate type 0 config cycle
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*/
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mvPexLocalBusNumSet(pexIf, bus);
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mvPexLocalDevNumSet(pexIf, 1);
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val = mvPexHwConfigRead (pexIf, bus, 0, func, regOff);
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mvPexLocalBusNumSet(pexIf, localBus);
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mvPexLocalDevNumSet(pexIf, localDev);
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return val;
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}
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}
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/* for all other devices use the HW function to get the
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* requested registers
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*/
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mvPexLocalDevNumSet(pexIf, 1);
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val = mvPexHwConfigRead (pexIf, bus, dev, func, regOff);
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mvPexLocalDevNumSet(pexIf, localDev);
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return val;
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}
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MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev,
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MV_U32 func, MV_U32 regOff, MV_U32 data)
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{
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MV_U32 localBus = mvPexLocalBusNumGet(pexIf);
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MV_U32 localDev = mvPexLocalDevNumGet(pexIf);
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MV_STATUS status;
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if(bus == localBus)
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{
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if(dev > 1)
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{
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/* on the local device allow only device #0 & #1 */
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return MV_ERROR;
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}
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else
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if (dev == localDev)
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{
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/* read the memory controller registers */
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return mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data);
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}
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else
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{
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/* access the virtual brg header */
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HEADER_WRITE(data, regOff);
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return MV_OK;
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}
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}
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else
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if(bus == (localBus + 1))
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{
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/* access the device behind the virtual bridge */
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if((dev == localDev) || (dev > 1))
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{
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return MV_ERROR;
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}
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else
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{
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/* access the device behind the virtual bridge, in this case
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* change the bus number to the local bus number in order to
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* generate type 0 config cycle
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*/
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//return mvPexHwConfigWrite (pexIf, localBus, dev, func, regOff, data);
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mvPexLocalBusNumSet(pexIf, bus);
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mvPexLocalDevNumSet(pexIf, 1);
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status = mvPexHwConfigWrite (pexIf, bus, 0, func, regOff, data);
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mvPexLocalBusNumSet(pexIf, localBus);
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mvPexLocalDevNumSet(pexIf, localDev);
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return status;
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}
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}
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/* for all other devices use the HW function to get the
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* requested registers
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*/
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mvPexLocalDevNumSet(pexIf, 1);
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status = mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data);
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mvPexLocalDevNumSet(pexIf, localDev);
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return status;
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}
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void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev)
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{
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MV_U32 tData;
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MV_U32 i;
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/* restore the PEX configuration to initialization state */
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/* in case PEX P2P call recursive and reset config */
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tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x0);
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if(tData != 0xffffffff)
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{
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/* agent had been found - check whether P2P */
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tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x8);
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if((tData & 0xffff0000) == 0x06040000)
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{/* P2P */
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/* get the sec bus and the subordinate */
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MV_U32 secBus;
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tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x18);
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secBus = ((tData >> 8) & 0xff);
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/* now scan on sec bus */
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for(i = 0;i < 0xff;i++)
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{
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resetPexConfig(pexIf, secBus, i);
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}
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/* now reset this device */
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DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev));
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mvPexHwConfigWrite(pexIf, bus, dev, 0x0, 0x18, 0x0);
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DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev));
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}
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}
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}
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