268 lines
12 KiB
C
268 lines
12 KiB
C
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/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __INC_MV_TSU_REGS_H__
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#define __INC_MV_TSU_REGS_H__
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#define TSU_MAX_DECODE_WIN 4
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#define TSU_GLOBAL_REG_BASE 0xB4000
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#define TSU_REG_BASE(port) (0xB8000 + (port * 0x800))
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#define MV_TSU_MODES_REG (TSU_GLOBAL_REG_BASE + 0x00)
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#define MV_TSU_CONFIG_REG(port) (TSU_REG_BASE(port) + 0x00)
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#define MV_TSU_DMA_PARAMS_REG(port) (TSU_REG_BASE(port) + 0x04)
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#define MV_TSU_DONE_QUEUE_BASE_REG(port) (TSU_REG_BASE(port) + 0x08)
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#define MV_TSU_DESC_QUEUE_BASE_REG(port) (TSU_REG_BASE(port) + 0x0C)
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#define MV_TSU_DONE_QUEUE_WRITE_PTR_REG(port) (TSU_REG_BASE(port) + 0x10)
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#define MV_TSU_DONE_QUEUE_READ_PTR_REG(port) (TSU_REG_BASE(port) + 0x14)
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#define MV_TSU_DESC_QUEUE_WRITE_PTR_REG(port) (TSU_REG_BASE(port) + 0x18)
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#define MV_TSU_DESC_QUEUE_READ_PTR_REG(port) (TSU_REG_BASE(port) + 0x1C)
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#define MV_TSU_ENABLE_ACCESS_REG(port) (TSU_REG_BASE(port) + 0x2C)
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#define MV_TSU_TIMESTAMP_REG(port) (TSU_REG_BASE(port) + 0x30)
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#define MV_TSU_STATUS_REG(port) (TSU_REG_BASE(port) + 0x34)
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#define MV_TSU_TIMESTAMP_CTRL_REG(port) (TSU_REG_BASE(port) + 0x38)
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#define MV_TSU_TEST_REG(port) (TSU_REG_BASE(port) + 0x3C)
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#define MV_TSU_INTERRUPT_SRC_REG(port) (TSU_REG_BASE(port) + 0x40)
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#define MV_TSU_INTERRUPT_MASK_REG(port) (TSU_REG_BASE(port) + 0x44)
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#define MV_TSU_IRQ_PARAM_REG(port) (TSU_REG_BASE(port) + 0x48)
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#define MV_TSU_DEBUG_REG(port) (TSU_REG_BASE(port) + 0x4C)
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#define MV_TSU_NEXT_DESC_1_REG(port) (TSU_REG_BASE(port) + 0x50)
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#define MV_TSU_NEXT_DESC_2_REG(port) (TSU_REG_BASE(port) + 0x54)
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#define MV_TSU_SYNCBYTE_DETECT_REG(port) (TSU_REG_BASE(port) + 0x58)
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#define MV_TSU_AGGREGATION_CTRL_REG(port) (TSU_REG_BASE(port) + 0x60)
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#define MV_TSU_TIMESTAMP_INTERVAL_REG(port) (TSU_REG_BASE(port) + 0x64)
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#define MV_TSU_CONFIG_2_REG(port) (TSU_REG_BASE(port) + 0x68)
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/* TSU Modes register. */
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#define TSU_MODES_PAR_MODE_OFFS 14
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#define TSU_MODES_PAR_MODE_MASK (0x1 << TSU_MODES_PAR_MODE_OFFS)
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#define TSU_MODES_PAR_MODE_SER (0x0 << TSU_MODES_PAR_MODE_OFFS)
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#define TSU_MODES_PAR_MODE_PAR (0x1 << TSU_MODES_PAR_MODE_OFFS)
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#define TSU_MODES_TSCK_OFF 15
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#define TSU_MODES_TSCK_MASK (0x3 << TSU_MODES_TSCK_OFF)
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/* TSU config register. */
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#define TSU_CFG_RESET_OFFS 0
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#define TSU_CFG_RESET_MASK (0x3 << TSU_CFG_RESET_OFFS)
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#define TSU_CFG_RESET_SET (0x1 << TSU_CFG_RESET_OFFS)
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#define TSU_CFG_RESET_CLEAR (0x2 << TSU_CFG_RESET_OFFS)
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#define TSU_CFG_OPER_OFFS 2
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#define TSU_CFG_OPER_MASK (0x3 << TSU_CFG_OPER_OFFS)
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#define TSU_CFG_OPER_DISABLE (0x1 << TSU_CFG_OPER_OFFS)
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#define TSU_CFG_OPER_ENABLE (0x2 << TSU_CFG_OPER_OFFS)
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#define TSU_CFG_DATA_DIR_OFFS 8
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#define TSU_CFG_DATA_DIR_MASK (0x1 << TSU_CFG_DATA_DIR_OFFS)
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#define TSU_CFG_DATA_DIR_IN (0x0 << TSU_CFG_DATA_DIR_OFFS)
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#define TSU_CFG_DATA_DIR_OUT (0x1 << TSU_CFG_DATA_DIR_OFFS)
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#define TSU_CFG_DATA_MODE_OFFS 9
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#define TSU_CFG_DATA_MODE_MASK (0x1 << TSU_CFG_DATA_MODE_OFFS)
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#define TSU_CFG_DATA_MODE_SER (0x0 << TSU_CFG_DATA_MODE_OFFS)
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#define TSU_CFG_DATA_MODE_PAR (0x1 << TSU_CFG_DATA_MODE_OFFS)
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#define TSU_CFG_OUT_CLOCK_OFFS 10
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#define TSU_CFG_OUT_CLOCK_MASK (0x3 << TSU_CFG_OUT_CLOCK_OFFS)
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#define TSU_CFG_OUT_CLOCK_4_32 (0x0 << TSU_CFG_OUT_CLOCK_OFFS)
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#define TSU_CFG_OUT_CLOCK_2_16 (0x1 << TSU_CFG_OUT_CLOCK_OFFS)
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#define TSU_CFG_OUT_CLOCK_1_8 (0x2 << TSU_CFG_OUT_CLOCK_OFFS)
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#define TSU_CFG_OUT_CLOCK_EXT (0x3 << TSU_CFG_OUT_CLOCK_OFFS)
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#define TSU_CFG_CLK_MODE_OFFS 12
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#define TSU_CFG_CLK_MODE_MASK (0x1 << TSU_CFG_CLK_MODE_OFFS)
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#define TSU_CFG_CLK_MODE_CONT (0x0 << TSU_CFG_CLK_MODE_OFFS)
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#define TSU_CFG_CLK_MODE_GAPPED (0x1 << TSU_CFG_CLK_MODE_OFFS)
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#define TSU_CFG_TS_SYNC_OFFS 13
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#define TSU_CFG_TS_SYNC_MASK (0x1 << TSU_CFG_TS_SYNC_OFFS)
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#define TSU_CFG_TS_SYNC_8BIT (0x0 << TSU_CFG_TS_SYNC_OFFS)
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#define TSU_CFG_TS_SYNC_1BIT (0x1 << TSU_CFG_TS_SYNC_OFFS)
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#define TSU_CFG_DATA_ORD_OFFS 14
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#define TSU_CFG_DATA_ORD_MASK (0x1 << TSU_CFG_DATA_ORD_OFFS)
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#define TSU_CFG_DATA_ORD_MSB (0x0 << TSU_CFG_DATA_ORD_OFFS)
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#define TSU_CFG_DATA_ORD_LSB (0x1 << TSU_CFG_DATA_ORD_OFFS)
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#define TSU_CFG_TX_EDGE_OFFS 15
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#define TSU_CFG_TX_EDGE_MASK (0x1 << TSU_CFG_TX_EDGE_OFFS)
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#define TSU_CFG_FREQ_MODE_OFFS 16
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#define TSU_CFG_FREQ_MODE_MASK (0x1 << TSU_CFG_FREQ_MODE_OFFS)
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#define TSU_CFG_ERR_POL_OFFS 18
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#define TSU_CFG_ERR_POL_MASK (0x1 << TSU_CFG_ERR_POL_OFFS)
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#define TSU_CFG_ERR_USED_OFFS 19
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#define TSU_CFG_ERR_USED_MASK (0x1 << TSU_CFG_ERR_USED_OFFS)
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#define TSU_CFG_VAL_POL_OFFS 20
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#define TSU_CFG_VAL_POL_MASK (0x1 << TSU_CFG_VAL_POL_OFFS)
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#define TSU_CFG_VAL_USED_OFFS 21
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#define TSU_CFG_VAL_USED_MASK (0x1 << TSU_CFG_VAL_USED_OFFS)
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#define TSU_CFG_SYNC_POL_OFFS 22
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#define TSU_CFG_SYNC_POL_MASK (0x1 << TSU_CFG_SYNC_POL_OFFS)
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#define TSU_CFG_SYNC_USED_OFFS 23
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#define TSU_CFG_SYNC_USED_MASK (0x1 << TSU_CFG_SYNC_USED_OFFS)
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#define TSU_CFG_RESET_SET (0x1 << TSU_CFG_RESET_OFFS)
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#define TSU_CFG_PKT_SIZE_OFFS 24
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#define TSU_CFG_PKT_SIZE_MASK (0xFF << TSU_CFG_PKT_SIZE_OFFS)
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/* TSU DMA parameters register. */
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#define TSU_DMAP_DMA_LEN_OFFS 0
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#define TSU_DMAP_DMA_LEN_MASK (0xFFFF << TSU_DMAP_DMA_LEN_OFFS)
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#define TSU_DMAP_DATA_WTRMK_OFFS 16
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#define TSU_DMAP_DATA_WTRMK_MASK (0xFF << TSU_DMAP_DATA_WTRMK_OFFS)
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#define TSU_DMAP_DATA_WTRMK_MAX 0xFF
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#define TSU_DMAP_DESC_Q_SIZE_OFFS 24
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#define TSU_DMAP_DESC_Q_SIZE_MASK (0xF << TSU_DMAP_DESC_Q_SIZE_OFFS)
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#define TSU_DMAP_DONE_Q_SIZE_OFFS 28
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#define TSU_DMAP_DONE_Q_SIZE_MASK (0xF << TSU_DMAP_DONE_Q_SIZE_OFFS)
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/* TSU Done queue base register. */
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#define TSU_DONE_PTR_BASE_OFFS 2
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#define TSU_DONE_PTR_BASE_MASK (0x3FFFFFFF << TSU_DONE_PTR_BASE_OFFS)
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/* TSU Desc queue base register. */
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#define TSU_DESC_PTR_BASE_OFFS 2
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#define TSU_DESC_PTR_BASE_MASK (0x3FFFFFFF << TSU_DESC_PTR_BASE_OFFS)
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/* TSU Done queue write pointer register. */
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#define TSU_DONE_WRITE_PTR_OFFS 0
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#define TSU_DONE_WRITE_PTR_MASK (0xFFF << TSU_DONE_WRITE_PTR_OFFS)
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/* TSU Done queue read pointer register. */
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#define TSU_DONE_READ_PTR_OFFS 0
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#define TSU_DONE_READ_PTR_MASK (0xFFF << TSU_DONE_READ_PTR_OFFS)
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/* TSU Desc queue write pointer register. */
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#define TSU_DESC_WRITE_PTR_OFFS 0
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#define TSU_DESC_WRITE_PTR_MASK (0xFFF << TSU_DESC_WRITE_PTR_OFFS)
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/* TSU Desc queue read pointer register. */
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#define TSU_DESC_READ_PTR_OFFS 0
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#define TSU_DESC_READ_PTR_MASK (0xFFF << TSU_DESC_READ_PTR_OFFS)
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/* TSU access enable reg. */
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#define TSU_ENACC_TS_READ_OFFS 0
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#define TSU_ENACC_TS_WRITE_OFFS 8
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#define TSU_ENACC_DESC_WRITE_OFFS 16
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#define TSU_ENACC_DESC_READ_OFFS 24
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/* TSU Timestamp register. */
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#define TSU_TMSTMP_TIMESTAMP_OFFS 0
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#define TSU_TMSTMP_TIMESTAMP_MASK (0xFFFFFFF << TSU_TMSTMP_TIMESTAMP_OFFS)
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/* TSU status register. */
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#define TSU_STATUS_OFFS 0
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#define TSU_STATUS_MASK (0x7FF << TSU_STATUS_OFFS)
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#define TSU_STATUS_IF_ERR (0x100 << TSU_STATUS_OFFS)
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#define TSU_STATUS_FIFO_OVFL_ERR (0x200 << TSU_STATUS_OFFS)
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#define TSU_STATUS_CONN_ERR (0x400 << TSU_STATUS_OFFS)
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/* TSU interrupt source register. */
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#define TSU_INT_TS_IF_ERROR (1 << 3)
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#define TSU_INT_FIFO_OVFL_ERROR (1 << 4)
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#define TSU_INT_TS_CONN_ERROR (1 << 5)
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#define TSU_INT_CLOCK_SYNC_EXP (1 << 6)
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/* TSU SyncByte detect register. */
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#define TSU_SYNC_DETECT_CNT_OFFS 0
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#define TSU_SYNC_DETECT_CNT_MASK (0xF << TSU_SYNC_DETECT_CNT_OFFS)
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#define TSU_SYNC_LOSS_CNT_OFFS 4
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#define TSU_SYNC_LOSS_CNT_MASK (0xF << TSU_SYNC_LOSS_CNT_OFFS)
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/* TSU Aggregation control register. */
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#define TSU_AGGR_PCKT_NUM_OFFS 0
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#define TSU_AGGR_PCKT_NUM_MASK (0xFF << TSU_AGGR_PCKT_NUM_OFFS)
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#define TSU_AGGR_TMSTMP_OFF_OFFS 8
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#define TSU_AGGR_TMSTMP_OFF_MASK (0xF << TSU_AGGR_TMSTMP_OFF_OFFS)
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#define TSU_AGGR_FLUSH_ERR_OFFS 26
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#define TSU_AGGR_FLUSH_ERR_MASK (0x3 << TSU_AGGR_FLUSH_ERR_OFFS)
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#define TSU_AGGR_FLUSH_ERR_DISABLE (0x1 << TSU_AGGR_FLUSH_ERR_OFFS)
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#define TSU_AGGR_FLUSH_ERR_ENABLE (0x2 << TSU_AGGR_FLUSH_ERR_OFFS)
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#define TSU_AGGR_TMSTMP_MODE_OFFS 28
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#define TSU_AGGR_TMSTMP_MODE_MASK (0x3 << TSU_AGGR_TMSTMP_MODE_OFFS)
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#define TSU_AGGR_TMSTMP_TO_DONE_Q (0x1 << TSU_AGGR_TMSTMP_MODE_OFFS)
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#define TSU_AGGR_TMSTMP_TO_PCKT (0x2 << TSU_AGGR_TMSTMP_MODE_OFFS)
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#define TSU_AGGR_ENABLE_OFFS 30
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#define TSU_AGGR_ENABLE_MASK (0x3 << TSU_AGGR_ENABLE_OFFS)
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#define TSU_AGGR_DISABLE (0x1 << TSU_AGGR_ENABLE_OFFS)
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#define TSU_AGGR_ENABLE (0x2 << TSU_AGGR_ENABLE_OFFS)
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/* TSU timestamp interval register. */
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#define TSU_TMSTP_INTRVL_OFFS 0
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#define TSU_TMSTP_INTRVL_MASK (0xFFFFFFF << TSU_TMSTP_INTRVL_OFFS)
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/* TSU timestamp control register. */
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#define TSU_TMS_CTRL_TIMER_OFFS 0
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#define TSU_TMS_CTRL_TIMER_MASK (0x3 << TSU_TMS_CTRL_TIMER_OFFS)
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#define TSU_TMS_CTRL_TIMER_DIS (0x1 << TSU_TMS_CTRL_TIMER_OFFS)
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#define TSU_TMS_CTRL_TIMER_EN (0x2 << TSU_TMS_CTRL_TIMER_OFFS)
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#define TSU_TMS_CTRL_AUTO_ADJ_OFFS 2
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#define TSU_TMS_CTRL_AUTO_ADJ_MASK (0x3 << TSU_TMS_CTRL_AUTO_ADJ_OFFS)
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#define TSU_TMS_CTRL_AUTO_ADJ_OFF (0x1 << TSU_TMS_CTRL_AUTO_ADJ_OFFS)
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#define TSU_TMS_CTRL_AUTO_ADJ_ON (0x2 << TSU_TMS_CTRL_AUTO_ADJ_OFFS)
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#define TSU_TMS_CTRL_READ_TIMER_OFFS 4
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#define TSU_TMS_CTRL_READ_TIMER_MASK (0x1 << TSU_TMS_CTRL_READ_TIMER_OFFS)
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#endif /* __INC_MV_TSU_REGS_H__ */
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