273 lines
11 KiB
C
273 lines
11 KiB
C
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/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __INCmvTdmRegsh
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#define __INCmvTdmRegsh
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/************************************************/
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/* TDM to Mbus Bridge Register Map */
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/************************************************/
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#define TDM_SPI_MUX_REG (TDM_REG_BASE + 0x4000)
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#define TDM_MBUS_CONFIG_REG (TDM_REG_BASE + 0x4010)
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#define TDM_MISC_REG (TDM_REG_BASE + 0x4070)
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#define TDM_CLK_DIV_REG (TDM_REG_BASE + 0x4074)
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/*****************************************/
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/* TDM Control Register Map */
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/*****************************************/
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#define PCM_CTRL_REG TDM_REG_BASE
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#define TIMESLOT_CTRL_REG (TDM_REG_BASE + 0x4)
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#define FRAME_TIMESLOT_REG (TDM_REG_BASE + 0x38)
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#define PCM_CLK_RATE_DIV_REG (TDM_REG_BASE + 0x3c)
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#define INT_EVENT_MASK_REG (TDM_REG_BASE + 0x40)
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//#define INT_EVENT_REG 0xb0044
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#define INT_STATUS_MASK_REG (TDM_REG_BASE + 0x48)
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#define INT_RESET_SELECT_REG (TDM_REG_BASE + 0x4c)
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#define INT_STATUS_REG (TDM_REG_BASE + 0x50)
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#define DUMMY_RX_WRITE_DATA_REG (TDM_REG_BASE + 0x54)
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#define MISC_CTRL_REG (TDM_REG_BASE + 0x58)
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#define TESTBUS_MUX_SELECT_REG (TDM_REG_BASE + 0x5c)
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#define CUR_TIMESLOT_REG (TDM_REG_BASE + 0x70)
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#define TDM_REV_REG (TDM_REG_BASE + 0x74)
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#define DMA_ABORT_ADDR_REG (TDM_REG_BASE + 0x80)
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#define DMA_ABORT_INFO_REG (TDM_REG_BASE + 0x84)
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#define CH_WB_DELAY_CTRL_REG(ch) ((TDM_REG_BASE + 0x88) | ((ch)<<2))
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#define CH_DELAY_CTRL_REG(ch) ((TDM_REG_BASE + 0x8) | ((ch)<<2))
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#define CH_SAMPLE_REG(ch) ((TDM_REG_BASE + 0x30) | ((ch)<<2))
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#define CH_DBG_REG(ch) ((TDM_REG_BASE + 0x78) | ((ch)<<2))
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#define CH_TX_CUR_ADDR_REG(ch) ((TDM_REG_BASE + 0x60) | ((ch)<<3))
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#define CH_RX_CUR_ADDR_REG(ch) ((TDM_REG_BASE + 0x64) | ((ch)<<3))
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#define CH_ENABLE_REG(ch) ((TDM_REG_BASE) | (((ch)+1)<<4))
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#define CH_BUFF_OWN_REG(ch) ((TDM_REG_BASE + 0x4) | (((ch)+1)<<4))
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#define CH_TX_ADDR_REG(ch) ((TDM_REG_BASE + 0x8) | (((ch)+1)<<4))
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#define CH_RX_ADDR_REG(ch) ((TDM_REG_BASE + 0xc) | (((ch)+1)<<4))
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/* PCM_CLK_RATE_DIV_REG bits */
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#define PCM_256KHZ 1
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#define PCM_512KHZ (1<<1)
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#define PCM_1024KHZ (1<<2)
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#define PCM_2048KHZ (1<<3)
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#define PCM_4096KHZ (1<<4)
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#define PCM_8192KHZ (1<<5)
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/* FRAME_TIMESLOT_REG bits */
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#define TIMESLOTS4_256KHZ (1<<2)
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#define TIMESLOTS8_512KHZ (1<<3)
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#define TIMESLOTS16_1024KHZ (1<<4)
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#define TIMESLOTS32_2048KHZ (1<<5)
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#define TIMESLOTS64_4096KHZ (1<<6)
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#define TIMESLOTS128_8192KHZ (1<<7)
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/* PCM_CTRL_REG bits */
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#define MASTER_PCLK_OFFS 0
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#define MASTER_PCLK_TDM (0<<MASTER_PCLK_OFFS)
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#define MASTER_PCLK_EXTERNAL (1<<MASTER_PCLK_OFFS)
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#define MASTER_FS_OFFS 1
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#define MASTER_FS_TDM (0<<MASTER_FS_OFFS)
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#define MASTER_FS_EXTERNAL (1<<MASTER_FS_OFFS)
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#define DATA_POLAR_OFFS 2
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#define DATA_POLAR_NEG (0<<DATA_POLAR_OFFS)
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#define DATA_POLAR_POS (1<<DATA_POLAR_OFFS)
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#define FS_POLAR_OFFS 3
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#define FS_POLAR_NEG (0<<FS_POLAR_OFFS)
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#define FS_POLAR_POS (1<<FS_POLAR_OFFS)
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#define INVERT_FS_OFFS 4
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#define INVERT_FS_HI (0<<INVERT_FS_OFFS)
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#define INVERT_FS_LO (1<<INVERT_FS_OFFS)
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#define FS_TYPE_OFFS 5
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#define FS_TYPE_SHORT (0<<FS_TYPE_OFFS)
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#define FS_TYPE_LONG (1<<FS_TYPE_OFFS)
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#define PCM_SAMPLE_SIZE_OFFS 6
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#define PCM_SAMPLE_SIZE_1 (0<<PCM_SAMPLE_SIZE_OFFS)
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#define PCM_SAMPLE_SIZE_2 (1<<PCM_SAMPLE_SIZE_OFFS)
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#define CH_DELAY_OFFS 8
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#define CH_DELAY_DISABLE (0<<CH_DELAY_OFFS)
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#define CH_DELAY_ENABLE (3<<CH_DELAY_OFFS)
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#define CH_QUALITY_OFFS 10
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#define CH_QUALITY_DISABLE (0<<CH_QUALITY_OFFS)
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#define CH_QUALITY_ENABLE (3<<CH_QUALITY_OFFS)
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#define QUALITY_POLARITY_OFFS 12
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#define QUALITY_POLARITY_NEG (0<<QUALITY_POLARITY_OFFS)
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#define QUALITY_POLARITY_POS (1<<QUALITY_POLARITY_OFFS)
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#define QUALITY_TYPE_OFFS 13
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#define QUALITY_TYPE_TIME_SLOT (0<<QUALITY_TYPE_OFFS)
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#define QUALITY_TYPE_MSB (3<<QUALITY_TYPE_OFFS)
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#define CS_CTRL_OFFS 15
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#define CS_CTRL_DONT_CARE (0<<CS_CTRL_OFFS)
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#define CS_CTRL (1<<CS_CTRL_OFFS)
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#define CS_CTRL_0 (0<<CS_CTRL_OFFS)
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#define CS_CTRL_1 (1<<CS_CTRL_OFFS)
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#define WIDEBAND_OFFS 16
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#define WIDEBAND_OFF (0<<WIDEBAND_OFFS)
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#define WIDEBAND_ON (3<<WIDEBAND_OFFS)
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#define PERF_GBUS_OFFS 31
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#define PERF_GBUS_ONE_ACCESS (0<<PERF_GBUS_OFFS)
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#define PERF_GBUS_TWO_ACCESS (1<<PERF_GBUS_OFFS)
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/* TIMESLOT_CTRL_REG bits */
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#define CH0_RX_SLOT_OFFS 0
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#define CH0_TX_SLOT_OFFS 8
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#define CH1_RX_SLOT_OFFS 16
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#define CH1_TX_SLOT_OFFS 24
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/* CH_SAMPLE_REG bits */
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#define TOTAL_CNT_OFFS 0
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#define TOTAL_CNT_MASK (0xff<<TOTAL_CNT_OFFS)
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#define INT_CNT_OFFS 8
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#define INT_CNT_MASK (0xff<<INT_CNT_OFFS)
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/* CH_BUFF_OWN_REG bits */
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#define RX_OWN_BYTE_OFFS 0
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#define TX_OWN_BYTE_OFFS 1
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#define OWNER_MASK 1
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#define OWN_BY_SW 0
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#define OWN_BY_HW 1
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/* CH_ENABLE_REG bits */
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#define RX_ENABLE_BYTE_OFFS 0
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#define TX_ENABLE_BYTE_OFFS 1
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#define CH_ENABLE 1
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#define CH_DISABLE 0
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/* INT_STATUS_REG bits */
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#define RX_OVERFLOW_BIT(ch) (1<<(0+(ch)*2))
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#define TX_UNDERFLOW_BIT(ch) (1<<(1+((ch)*2)))
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#define RX_BIT(ch) (1<<(4+((ch)*2)))
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#define TX_BIT(ch) (1<<(5+((ch)*2)))
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#define RX_IDLE_BIT(ch) (1<<(8+((ch)*2)))
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#define TX_IDLE_BIT(ch) (1<<(9+((ch)*2)))
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#define RX_FIFO_FULL(ch) (1<<(12+((ch)*2)))
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#define TX_FIFO_EMPTY(ch) (1<<(13+((ch)*2)))
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#define DMA_ABORT_BIT (1<<16)
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#define SLIC_INT_BIT (1<<17)
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/* TDU_INTR_SET_RESET bits */
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#define CLEAR_MODE_OFFS 0
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#define CLEAR_ON_READ (1<<CLEAR_MODE_OFFS)
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#define CLEAR_ON_ZERO (0<<CLEAR_MODE_OFFS)
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/* CH_DELAY_CTRL_REG bits */
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#define CH_RX_DELAY_OFFS 0
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#define CH_RX_DELAY_MASK (0x3ff<<CH_RX_DELAY_OFFS)
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#define CH_TX_DELAY_OFFS 16
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#define CH_TX_DELAY_MASK (0x3ff<<CH_RX_DELAY_OFFS)
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/*********************************/
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/* SPI Register Map */
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/*********************************/
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#define SPI_CLK_PRESCALAR_REG (TDM_REG_BASE +0x3100)
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#define SPI_GLOBAL_CTRL_REG (TDM_REG_BASE +0x3104)
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#define SPI_CTRL_REG (TDM_REG_BASE +0x3108)
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#define SPI_MICRO_WIRE_CTRL_REG (TDM_REG_BASE +0x310c)
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#define SPI_TWSI_CTRL_REG (TDM_REG_BASE +0x3110)
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#define SPI_MV_STATUS_REG (TDM_REG_BASE +0x311c)
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#define SPI_INT_MASK_REG (TDM_REG_BASE +0x3120)
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#define SPI_DATA_REG (TDM_REG_BASE +0x3124)
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#define SPI_ADDR_REG (TDM_REG_BASE +0x3128)
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#define SPI_CODEC_CMD_LO_REG (TDM_REG_BASE +0x3130)
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#define SPI_CODEC_CMD_HI_REG (TDM_REG_BASE +0x3134)
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#define SPI_CODEC_CTRL_REG (TDM_REG_BASE +0x3138)
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#define SPI_CODEC_READ_DATA_REG (TDM_REG_BASE +0x313c)
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/* SPI CLK_PRESCALAR_REG bits */
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#define SPI_CLK_4MHZ 0x2A32 /* refers to tclk = 200MHz */
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#define SPI_CLK_8MHZ 0x2A19 /* refers to tclk = 200MHz */
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/* SPI_CTRL_REG bits */
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#define SPI_STAT_OFFS 10
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#define SPI_STAT_MASK (1<<SPI_STAT_OFFS)
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#define SPI_READY (0<<SPI_STAT_OFFS)
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#define SPI_ACTIVE (1<<SPI_STAT_OFFS)
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/* SPI_GLOBAL_CTRL_REG bits */
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#define SPI_GLOBAL_ENABLE_OFFS 0
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#define SPI_GLOBAL_ENABLE_MASK (1<<SPI_GLOBAL_ENABLE_OFFS)
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#define SPI_GLOBAL_DISABLE (0<<SPI_GLOBAL_ENABLE_OFFS)
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#define SPI_GLOBAL_ENABLE (1<<SPI_GLOBAL_ENABLE_OFFS)
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/* SPI_CODEC_CTRL_REG bits */
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#define TRANSFER_BYTES_OFFS 0
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#define TRANSFER_BYTES(count) ((count-1)<<TRANSFER_BYTES_OFFS)
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#define ENDIANESS_MODE_OFFS 2
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#define ENDIANESS_MSB_MODE (0<<ENDIANESS_MODE_OFFS)
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#define ENDIANESS_LSB_MODE (1<<ENDIANESS_MODE_OFFS)
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#define RD_WR_MODE_OFFS 3
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#define WR_MODE (0<<RD_WR_MODE_OFFS)
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#define RD_MODE (1<<RD_WR_MODE_OFFS)
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#define READ_BYTES_OFFS 4
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#define READ_1_BYTE (0<<READ_BYTES_OFFS)
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#define READ_2_BYTE (1<<READ_BYTES_OFFS)
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#define CLK_SPEED_OFFS 5
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#define CLK_SPEED_LO_DIV (0<<CLK_SPEED_OFFS)
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#define CLK_SPEED_HI_DIV (1<<CLK_SPEED_OFFS)
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#define CS_HI_CNT_VAL_RD_OFFS 6
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#define CS_HI_CNT_VAL_RD_MASK (0xff3<<CS_HI_CNT_VAL_RD_OFFS)
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#endif /*__INCmvTdmRegsh*/
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