412 lines
13 KiB
ArmAsm
412 lines
13 KiB
ArmAsm
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#define MV_ASMLANGUAGE
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#include "mvDramIfRegs.h"
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#include "mvDramIfConfig.h"
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#include "nBootstrap.h"
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#if !defined(MV_BOOTROM)
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.globl nbootStart
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nbootStart:
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/*
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* set the cpu to SVC32 mode, I and F disabled.
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*/
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mov r1, #0xd3
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msr cpsr,r1
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/*
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* flush v4 I/D caches
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*/
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mcr p15, 0, r1, c7, c7, 0 /* invalidate v3/v4 cache */
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r1, c1, c0, 0
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bic r1, r1, #0x00000300 /* clear bits 9:8 (--V- --RS) */
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bic r1, r1, #0x00000007 /* clear bits 2:0 (-CAM) */
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orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */
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/* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */
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mcr p15, 0, r1, c1, c0, 0
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/* Add nop commands for cache flush operations */
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nop
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nop
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nop
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nop
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nop
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nop
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/* here. MUST BE IN THE SAME CACHE LINE */
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mov r0, #0 /* We use r0 as always '0' */
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#ifdef NAND_CTRL_88F528x
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/* Load CPU controller base address 0xD0020000 */
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mov r2, #0xd0000000
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orr r2, r2, #0x20000
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MV_REG_READ_ASM (r1, r2, 0x20120)
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bic r1, r1, #MV_32BIT_LE(0x7F00)
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orr r1, r1, #MV_32BIT_LE(0x8200)
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bic r1, r1, #MV_32BIT_LE(0x007F)
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orr r1, r1, #MV_32BIT_LE(0x001b)
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MV_REG_WRITE_ASM(r1, r2, 0x20120)
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/* Set CPU to Mbus-L DDR Interface Tick Driver and Tick Sample */
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MV_REG_READ_ASM (r1, r2, 0x20100)
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bic r1, r1, #MV_32BIT_LE(0xFF00)
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orr r1, r1, #MV_32BIT_LE(CPU_2_MBUSL_DDR_CLK)
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MV_REG_WRITE_ASM(r1, r2, 0x20100)
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#endif /* NAND_CTRL_88F528x */
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/* DRAM memory initialization */
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/* Load SDRAM controller base address 0xd0001000 */
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mov r2, #0xd0000000
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orr r2, r2, #0x1000
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/* Write to SDRAM coniguration register */
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#ifndef MV_88W8660
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GPR_LOAD(r1, MV_32BIT_LE(SDRAM_CONFIG_REG_DV))
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#else
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GPR_LOAD(r1, MV_32BIT_LE((SDRAM_CONFIG_REG_DV & ~(0x40))))
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#endif /* MV_88W8660 */
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MV_REG_WRITE_ASM(r1, r2, SDRAM_CONFIG_REG)
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/* Write Dunit control low register */
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GPR_LOAD(r1, MV_32BIT_LE(SDRAM_DUNIT_CTRL_REG_DV))
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MV_REG_WRITE_ASM(r1, r2, SDRAM_DUNIT_CTRL_REG)
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/* Write SDRAM address control register */
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GPR_LOAD(r1, MV_32BIT_LE(SDRAM_ADDR_CTRL_REG_DV))
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MV_REG_WRITE_ASM(r1, r2, SDRAM_ADDR_CTRL_REG)
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/* Write SDRAM timing Low register */
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GPR_LOAD(r1, MV_32BIT_LE(SDRAM_TIMING_CTRL_LOW_REG_DVAL))
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MV_REG_WRITE_ASM(r1, r2, SDRAM_TIMING_CTRL_LOW_REG)
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/* Write SDRAM timing High register */
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GPR_LOAD(r1, MV_32BIT_LE(SDRAM_TIMING_CTRL_HIGH_REG_DVAL))
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MV_REG_WRITE_ASM(r1, r2, SDRAM_TIMING_CTRL_HIGH_REG)
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/* Write SDRAM mode register */
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GPR_LOAD(r1, MV_32BIT_LE(SDRAM_MODE_REG_DV))
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MV_REG_WRITE_ASM(r1, r2, SDRAM_MODE_REG)
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/* Write SDRAM Extended mode register */
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GPR_LOAD(r1, MV_32BIT_LE(SDRAM_EXTENDED_MODE_REG_DV))
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MV_REG_WRITE_ASM(r1, r2, SDRAM_EXTENDED_MODE_REG)
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/* Config DDR2 registers pad calibration */
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MV_REG_READ_ASM (r1, r2, SDRAM_CONFIG_REG)
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tst r1, #SDRAM_DTYPE_DDR2
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beq ddr1PadCal
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/* Config DDR2 On Die Termination (ODT) registers */
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GPR_LOAD(r1, MV_32BIT_LE(DDR2_SDRAM_ODT_CTRL_LOW_REG_DV))
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MV_REG_WRITE_ASM(r1, r2, DDR2_SDRAM_ODT_CTRL_LOW_REG)
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/* Write SDRAM DDR2 ODT control high register */
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GPR_LOAD(r1, MV_32BIT_LE(DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV))
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MV_REG_WRITE_ASM(r1, r2, DDR2_SDRAM_ODT_CTRL_HIGH_REG)
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/* Write SDRAM DDR2 Dunit ODT control register */
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GPR_LOAD(r1, MV_32BIT_LE(DDR2_DUNIT_ODT_CTRL_REG_DV))
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MV_REG_WRITE_ASM(r1, r2, DDR2_DUNIT_ODT_CONTROL_REG)
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mov r3, #MV_32BIT_LE(DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV)
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mov r4, #MV_32BIT_LE(DDR2_DATA_PAD_STRENGTH_TYPICAL_DV)
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b next
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ddr1PadCal:
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mov r3, #MV_32BIT_LE(DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV)
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mov r4, #MV_32BIT_LE(DDR1_DATA_PAD_STRENGTH_TYPICAL_DV)
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next:
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/* Implement Guideline (GL# MEM-3) Drive Strength Value */
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/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
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/* DDR SDRAM Address/Control Pads Calibration */
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MV_REG_READ_ASM (r1, r2, SDRAM_ADDR_CTRL_PADS_CAL_REG)
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orr r5, r1, #MV_32BIT_LE(SDRAM_WR_EN) /* Make register writeable */
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MV_REG_WRITE_ASM (r5, r2, SDRAM_ADDR_CTRL_PADS_CAL_REG)
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orr r1, r3, r1 /* Set default value for DDR */
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MV_REG_WRITE_ASM (r1, r2, SDRAM_ADDR_CTRL_PADS_CAL_REG)
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/* DDR SDRAM Data Pads Calibration */
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MV_REG_READ_ASM (r1, r2, SDRAM_DATA_PADS_CAL_REG)
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orr r5, r1, #MV_32BIT_LE(SDRAM_WR_EN) /* Make register writeable */
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MV_REG_WRITE_ASM (r5, r2, SDRAM_DATA_PADS_CAL_REG)
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orr r1, r4, r1 /* Set default value for DDR */
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MV_REG_WRITE_ASM (r1, r2, SDRAM_DATA_PADS_CAL_REG)
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#ifndef MV_88W8660
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/* Write Dunit FTDLL Configuration Register */
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GPR_LOAD(r1, MV_32BIT_LE(SDRAM_FTDLL_CONFIG_REG_DV))
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MV_REG_WRITE_ASM(r1, r2, SDRAM_FTDLL_CONFIG_REG)
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#endif /* MV_88W8660 */
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/* DDR SDRAM Initialization Control Register. Init enable */
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mov r1, #MV_32BIT_LE(DSICR_INIT_EN)
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MV_REG_WRITE_ASM (r1, r2, DDR_SDRAM_INIT_CTRL_REG)
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ddrInitLoop:
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MV_REG_READ_ASM (r1, r2, DDR_SDRAM_INIT_CTRL_REG)
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cmp r1, #0
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bne ddrInitLoop
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/* Continue in next NAND page */
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/*****************************************************************************/
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/* This code open NAND page 1 for read and relocates the CPU to read */
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/* from that page. */
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/*****************************************************************************/
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/* r2 - is the page number */
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/* r5 - nand flash base */
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/* r6 - is cmd read */
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/* r0 - 0 */
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/* r9 - is cmd status */
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/* r4 - next address to jump */
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/* Load the NAND base address */
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GPR_LOAD(r5, NAND_FLASH_BASE)
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/* init */
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mov r0, #0
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mov r2, #0x1 /* start with page 1 */
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mov r6, #CMD_READ
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mov r9, #CMD_STATUS
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orr r4, r5, #0x200
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.align 5
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b ncl
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sop:
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/* issue read command */
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strb r6, [r5, #NAND_CMD_PORT]
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/* issue address */
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strb r0, [r5, #NAND_ADDR_PORT]
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strb r2, [r5, #NAND_ADDR_PORT] /* page address */
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strb r0, [r5, #NAND_ADDR_PORT]
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/* Check status */
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strb r9, [r5, #NAND_CMD_PORT]
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b busy_loop
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.align 5
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ncl:
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b ncl2
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busy_loop:
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ldrb r1, [r5]
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tst r1, #STATUS_READY
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beq busy_loop
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/* back to read mode */
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strb r6, [r5, #NAND_CMD_PORT]
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mov pc, r4
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.align 5
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ncl2:
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b sop
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/* Next page must be in page offset - 512 bytes */
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.align 9
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page1:
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/*****************************************************************************/
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/* This code extract the booter from the rest of block 1 which is known to */
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/* be error free (no need for ECC). This booter should copy the U-boot code */
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/* to DRAM */
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/*****************************************************************************/
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/* DRAM init - Cont'd */
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/* Load back SDRAM controller base address 0xd0001000 */
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mov r2, #0xd0000000
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orr r2, r2, #0x1000
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/* Open SDRAM bank 0 size register */
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GPR_LOAD(r1, MV_32BIT_LE(SDRAM_SIZE_REG_DV))
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MV_REG_WRITE_ASM(r1, r2, SDRAM_SIZE_REG(0))
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/* Close SDRAM bank 1,2,3 */
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MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(1))
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MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(2))
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MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(3))
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/* Prepare the address where to find the nandBoot function pointer */
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mov lr, #0x20000
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orr lr, lr, #0x600
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/* Initialize UART 0 to 115200 bps */
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GPR_LOAD(r2, 0xd0012000)
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mov r1, #0x07
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strb r1, [r2, #0x8]
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mov r1, #0x83
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strb r1, [r2, #0xC]
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mov r1, #0x5A
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strb r1, [r2, #0x0]
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mov r1, #0x03
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strb r1, [r2, #0xC]
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mov r1, #'N'
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strb r1, [r2]
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mov r1, #'A'
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strb r1, [r2]
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mov r1, #'N'
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strb r1, [r2]
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mov r1, #'D'
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strb r1, [r2]
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mov r1, #' '
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strb r1, [r2]
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mov r1, #'b'
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strb r1, [r2]
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mov r1, #'o'
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strb r1, [r2]
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mov r1, #'o'
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strb r1, [r2]
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mov r1, #'t'
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strb r1, [r2]
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mov r1, #'s'
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strb r1, [r2]
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mov r1, #'t'
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strb r1, [r2]
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mov r1, #'r'
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strb r1, [r2]
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mov r1, #'a'
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strb r1, [r2]
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mov r1, #'p'
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strb r1, [r2]
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mov r1, #10
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strb r1, [r2]
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mov r1, #13
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strb r1, [r2]
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/* init */
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mov r2, #0x3 /* start with page 3 */
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// mov r3, #BOOTER_BASE /* start of DRAM buffer */
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mov r3, #0x20000
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orr r3, r3, #0x600
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.align 5
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b ncl31
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sop1:
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cp_page_loop:
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mov r0, #0
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mov r6, #CMD_READ
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mov r9, #CMD_STATUS
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mov r4, #PAGE_SIZE /* Byte counter */
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b startRead
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.align 5
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ncl31:
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b ncl3
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startRead:
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/* issue read command */
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strb r6, [r5, #NAND_CMD_PORT]
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/* issue address */
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strb r0, [r5, #NAND_ADDR_PORT]
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strb r2, [r5, #NAND_ADDR_PORT] /* page address */
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strb r0, [r5, #NAND_ADDR_PORT]
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/* Check status */
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strb r9, [r5, #NAND_CMD_PORT]
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b busy_loop1
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.align 5
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ncl3:
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b ncl4
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busy_loop1:
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ldrb r1, [r5]
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tst r1, #STATUS_READY
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beq busy_loop1
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/* back to read mode */
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strb r6, [r5, #NAND_CMD_PORT]
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/* now perform reading */
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mov r0, r5
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b copy_loop1
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.align 5
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ncl4:
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b ncl5
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copy_loop1:
|
||
|
|
sub r4, r4, #32 /* 8 dwords * 4 bytes */
|
||
|
|
ldmia r0!, {r6-r13}
|
||
|
|
stmia r3!, {r6-r13}
|
||
|
|
|
||
|
|
cmp r4, #0 /* check if we have read a full Page */
|
||
|
|
bne copy_loop1
|
||
|
|
b nextPage
|
||
|
|
|
||
|
|
.align 5
|
||
|
|
ncl5:
|
||
|
|
b ncl6
|
||
|
|
|
||
|
|
nextPage:
|
||
|
|
add r2, r2, #1 /* increment page number */
|
||
|
|
cmp r2, #BOOTER_PAGE_NUM
|
||
|
|
bne cp_page_loop
|
||
|
|
b stack_setup
|
||
|
|
|
||
|
|
.align 5
|
||
|
|
ncl6:
|
||
|
|
b sop1
|
||
|
|
|
||
|
|
|
||
|
|
/* Set up the stack */
|
||
|
|
stack_setup:
|
||
|
|
sub sp, lr, #12 /* leave 3 words for abort-stack */
|
||
|
|
|
||
|
|
/* jump to new code */
|
||
|
|
mov pc, lr
|
||
|
|
|
||
|
|
|
||
|
|
.align 9
|
||
|
|
|
||
|
|
/* This is known to be address (BOOTER_BASE + 2 * PAGE_SIZE) */
|
||
|
|
_nandBootPtr:
|
||
|
|
.word nand_boot
|
||
|
|
|
||
|
|
#else /* MV_BOOTROM */
|
||
|
|
|
||
|
|
.globl nbootStart
|
||
|
|
nbootStart:
|
||
|
|
/* Enable I-Cache */
|
||
|
|
mrc p15, 0, r1, c1, c0, 0
|
||
|
|
orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */
|
||
|
|
/* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */
|
||
|
|
mcr p15, 0, r1, c1, c0, 0
|
||
|
|
|
||
|
|
/* Set up the stack */
|
||
|
|
mov r0, #BOOTER_BASE
|
||
|
|
sub sp, r0, #12 /* leave 3 words for abort-stack */
|
||
|
|
|
||
|
|
/* jump to new code */
|
||
|
|
|
||
|
|
ldr lr, =nand_boot
|
||
|
|
mov pc, lr
|
||
|
|
#endif /* !defined(MV_BOOTROM) */
|