GPL_TS-20121119-3.8.0

board/mv_feroceon/USP/mv_flash.c

@@ -1478,6 +1478,7 @@ int sflash_erase (MV_SFLASH_INFO *pInfo, MV_U32 s_first, MV_U32 s_last)
                       __FUNCTION__, i, mvSFlashModelGet(pInfo));)
             return 1;
         }
+        mvOsDelay(10); // add for fix "Error: sflash_erase - mvSFlashSectorErase on sector 199" from Tom's advice, wait 10 ms
     }
 
     return 0;

board/mv_feroceon/mv_hal/sflash/mvSFlash.c

@@ -149,6 +149,30 @@ static MV_SFLASH_DEVICE_PARAMS sflash[] = {
      MV_M25P128_MAX_FAST_SPI_FREQ,
      MV_M25P128_FAST_READ_DUMMY_BYTES
     },
+    /* MC N25Q128 SPI flash, 16MB, 256 sectors of 64K each */
+    {
+     MV_M25P_WREN_CMND_OPCD,
+     MV_M25P_WRDI_CMND_OPCD,
+     MV_M25P_RDID_CMND_OPCD,
+     MV_M25P_RDSR_CMND_OPCD,
+     MV_M25P_WRSR_CMND_OPCD,
+     MV_M25P_READ_CMND_OPCD,
+     MV_M25P_FAST_RD_CMND_OPCD,
+     MV_M25P_PP_CMND_OPCD,
+     MV_M25P_SE_CMND_OPCD,
+     MV_M25P_BE_CMND_OPCD,
+     MV_M25P_RES_CMND_OPCD,
+     MV_SFLASH_NO_SPECIFIC_OPCD,    /* power save not supported */
+     MC_N25Q128_SECTOR_SIZE, //64*1024
+     MC_N25Q128_SECTOR_NUMBER, //256
+     MC_N25Q_PAGE_SIZE,
+     "MC N25Q128",
+     MC_N25Q128_ST_MANF_ID, //0x20
+     MC_N25Q128_DEVICE_ID, //0xba18
+     MV_M25P128_MAX_SPI_FREQ,
+     MV_M25P128_MAX_FAST_SPI_FREQ,
+     MV_M25P128_FAST_READ_DUMMY_BYTES
+    },
     /* Macronix MXIC MX25L6405 SPI flash, 8MB, 128 sectors of 64K each */
     {
      MV_MX25L_WREN_CMND_OPCD,

board/mv_feroceon/mv_hal/sflash/mvSFlashSpec.h

@@ -146,6 +146,16 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define     MV_M25P_STATUS_BP_1_OF_2            (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET)
 #define     MV_M25P_STATUS_BP_ALL               (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET)
 
+/********************************/
+/*  Micron N25Qxxx Device Specific  */
+/********************************/
+#define     MC_N25Q128_SECTOR_SIZE              0x10000 /* 64K */
+#define     MC_N25Q128_SECTOR_NUMBER            256
+#define		MC_N25Q_PAGE_SIZE				    0x100   /* 256 byte */
+#define     MC_N25Q128_ST_MANF_ID               0x20
+#define     MC_N25Q128_DEVICE_ID                0xba18
+
+
 /************************************/
 /*  MXIC MX25L6405 Device Specific  */
 /************************************/

board/mv_feroceon/mv_hal/spi/mvSpi.c

@@ -322,7 +322,9 @@ MV_VOID mvSpiCsAssert(MV_VOID)
     /* For devices in which the SPI is muxed on the MPP with other interfaces*/
     mvMPPConfigToSPI();
 
+    mvOsUDelay(4); // There was a CS controller timming rule from 1 microsecond to 8 microsecond.
 	MV_REG_BIT_SET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK);
+    mvOsUDelay(8); 
 }
 
 /*******************************************************************************
@@ -344,8 +346,9 @@ MV_VOID mvSpiCsAssert(MV_VOID)
 ********************************************************************************/
 MV_VOID mvSpiCsDeassert(MV_VOID)
 {
+	mvOsUDelay(8); // There was a CS controller timming rule from 1 microsecond to 8 microsecond.
 	MV_REG_BIT_RESET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK);
-
+	mvOsUDelay(4); // There was a CS controller timming rule from 1 microsecond to 8 microsecond.
     /* For devices in which the SPI is muxed on the MPP with other interfaces*/
     mvMPPConfigToDefault();
 }

include/configs/DU405.h

@@ -32,7 +32,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_IDENT_STRING     " $Name: R-3-7-0-B20120603-branch $"
+#define CONFIG_IDENT_STRING     " $Name: R-3-8-0-B20121107-branch $"
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family	*/

include/configs/PCI405.h

@@ -32,7 +32,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_IDENT_STRING     " $Name: R-3-7-0-B20120603-branch $"
+#define CONFIG_IDENT_STRING     " $Name: R-3-8-0-B20121107-branch $"
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family	*/

include/configs/WUH405.h

@@ -32,7 +32,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_IDENT_STRING     " $Name: R-3-7-0-B20120603-branch $"
+#define CONFIG_IDENT_STRING     " $Name: R-3-8-0-B20121107-branch $"
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family	*/