130 lines
5.7 KiB
C
130 lines
5.7 KiB
C
/*
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* drivers/mtd/nandids.c
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*
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* Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de)
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*
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* $Id: nand_ids.c,v 1.10 2004/05/26 13:40:12 gleixner Exp $
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <common.h>
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#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
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#include <linux/mtd/nand.h>
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/*
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* Chip ID list
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*
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* Name. ID code, pagesize, chipsize in MegaByte, eraseblock size,
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* options
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*
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* Pagesize; 0, 256, 512
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* 0 get this information from the extended chip ID
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+ 256 256 Byte page size
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* 512 512 Byte page size
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*/
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struct nand_flash_dev nand_flash_ids[] = {
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{"NAND 1MB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
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{"NAND 2MB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
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{"NAND 4MB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
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{"NAND 1MB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
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{"NAND 1MB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
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{"NAND 2MB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
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{"NAND 4MB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
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{"NAND 4MB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
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{"NAND 4MB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
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{"NAND 8MB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
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{"NAND 8MB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
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{"NAND 8MB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
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{"NAND 8MB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
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{"NAND 8MB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
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{"NAND 16MB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
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{"NAND 16MB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
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{"NAND 16MB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 16MB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 32MB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
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{"NAND 32MB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
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{"NAND 32MB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 32MB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 64MB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
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{"NAND 64MB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
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{"NAND 64MB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 64MB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 128MB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
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{"NAND 128MB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
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{"NAND 128MB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 128MB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 256MB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
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/* These are the new chips with large page size. The pagesize
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* and the erasesize is determined from the extended id bytes
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*/
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/* 1 Gigabit */
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{"NAND 128MB 1,8V 8-bit", 0xA1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
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{"NAND 128MB 3,3V 8-bit", 0xF1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
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{"NAND 128MB 1,8V 16-bit", 0xB1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
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{"NAND 128MB 3,3V 16-bit", 0xC1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
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/* 2 Gigabit */
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{"NAND 256MB 1,8V 8-bit", 0xAA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
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{"NAND 256MB 3,3V 8-bit", 0xDA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
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{"NAND 256MB 1,8V 16-bit", 0xBA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
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{"NAND 256MB 3,3V 16-bit", 0xCA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
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/* 4 Gigabit */
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{"NAND 512MB 1,8V 8-bit", 0xAC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
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{"NAND 512MB 3,3V 8-bit", 0xDC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
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{"NAND 512MB 1,8V 16-bit", 0xBC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
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{"NAND 512MB 3,3V 16-bit", 0xCC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
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/* 8 Gigabit */
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{"NAND 1GB 1,8V 8-bit", 0xA3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
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{"NAND 1GB 3,3V 8-bit", 0xD3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
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{"NAND 1GB 1,8V 16-bit", 0xB3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
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{"NAND 1GB 3,3V 16-bit", 0xC3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
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/* 16 Gigabit */
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{"NAND 2GB 1,8V 8-bit", 0xA5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
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{"NAND 2GB 3,3V 8-bit", 0xD5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
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{"NAND 2GB 1,8V 16-bit", 0xB5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
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{"NAND 2GB 3,3V 16-bit", 0xC5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
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/* Renesas AND 1 Gigabit. Those chips do not support extended id and have a strange page/block layout !
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* The chosen minimum erasesize is 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page planes
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* 1 block = 2 pages, but due to plane arrangement the blocks 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7
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* Anyway JFFS2 would increase the eraseblock size so we chose a combined one which can be erased in one go
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* There are more speed improvements for reads and writes possible, but not implemented now
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*/
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{"AND 128MB 3,3V 8-bit", 0x01, 2048, 128, 0x4000, NAND_IS_AND | NAND_NO_AUTOINCR | NAND_4PAGE_ARRAY},
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{NULL,}
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};
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/*
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* Manufacturer ID list
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*/
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struct nand_manufacturers nand_manuf_ids[] = {
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{NAND_MFR_TOSHIBA, "Toshiba"},
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{NAND_MFR_SAMSUNG, "Samsung"},
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{NAND_MFR_FUJITSU, "Fujitsu"},
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{NAND_MFR_NATIONAL, "National"},
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{NAND_MFR_RENESAS, "Renesas"},
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{NAND_MFR_STMICRO, "ST Micro"},
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{NAND_MFR_HYNIX, "Hynix"},
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{NAND_MFR_MICRON, "Micron"},
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{NAND_MFR_AMD, "AMD"},
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{0x0, "Unknown"}
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};
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#endif
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