739 lines
31 KiB
C
739 lines
31 KiB
C
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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*******************************************************************************/
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/*******************************************************************************
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* mvSysHwCfg.h - Marvell system HW configuration file
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*
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* DESCRIPTION:
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* None.
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*
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* DEPENDENCIES:
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* None.
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*
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*******************************************************************************/
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#ifndef __INCmvSysHwConfigh
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#define __INCmvSysHwConfigh
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/****************************************/
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/* Soc supporetd Units definitions */
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/****************************************/
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#define MV_INCLUDE_PEX
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#define MV_INCLUDE_GIG_ETH
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#define MV_INCLUDE_TWSI
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#define MV_INCLUDE_CLK_PWR_CNTRL
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#define MV_INCLUDE_INTEG_SATA
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#ifndef MV_TINY_IMAGE
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#define MV_INCLUDE_SATA
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#define MV_INCLUDE_IDMA
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#define MV_INCLUDE_XOR
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#define MV_INCLUDE_SPI
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#define MV_INCLUDE_USB
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#endif
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/*********************************************/
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/* Board Specific defines : On-Board devices */
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/*********************************************/
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/* DRAM ddim detection support */
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#define MV_INC_BOARD_DDIM
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/* On-Board NOR Flash support */
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#define MV_INC_BOARD_NOR_FLASH
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#ifndef MV_TINY_IMAGE
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/* On-Board PCI\PEX SATA driver*/
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#define MV_INC_BOARD_PCI_SATA
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/* On-Board NAND Flash support */
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#define MV_INC_BOARD_NAND_FLASH
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/* On-Board SPI Flash support */
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#define MV_INC_BOARD_SPI_FLASH
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/* On-Board RTC */
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#define MV_INC_BOARD_RTC
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#endif
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#if defined(DB_MV78XX0) || defined (DB_MV88F632X)
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#define CFG_DRAM_BANKS 4
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#elif defined(RD_MV78XX0_AMC)
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#define PCIE_VIRTUAL_BRIDGE_SUPPORT
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#define MV_STATIC_DRAM_ON_BOARD
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#define CFG_DRAM_BANKS 1
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#elif defined(RD_MV78XX0_PCAC)
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#define MV_STATIC_DRAM_ON_BOARD
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#define CFG_DRAM_BANKS 1
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#elif defined(RD_MV78XX0_MASA)
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#define CFG_DRAM_BANKS 2
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#define CFG_NO_FLASH
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#undef MV_INC_BOARD_NOR_FLASH
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#define CONFIG_JFFS2_CMDLINE
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#define CONFIG_JFFS2_NAND
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#elif defined(RD_MV78XX0_H3C)
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#define MV_STATIC_DRAM_ON_BOARD
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#define CFG_DRAM_BANKS 1
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#define AMD_FLASH_16BIT_IN_8BIT_MODE
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#endif
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/************************************************/
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/* U-Boot Specific */
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/************************************************/
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#ifndef MV_TINY_IMAGE
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#define MV_INCLUDE_MONT_EXT
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#if defined(MV_INCLUDE_MONT_EXT)
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#define MV_INCLUDE_MONT_MMU
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#if defined(MV_INC_BOARD_NOR_FLASH)
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#define MV_INCLUDE_MONT_FFS
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#endif
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#endif
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#endif
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#define MV_CACHEABLE(address) ((address) | 0x80000000)
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/* includes */
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#define _1K 0x00000400
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#define _4K 0x00001000
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#define _8K 0x00002000
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#define _16K 0x00004000
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#define _32K 0x00008000
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#define _64K 0x00010000
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#define _128K 0x00020000
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#define _256K 0x00040000
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#define _512K 0x00080000
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#define _1M 0x00100000
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#define _2M 0x00200000
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#define _4M 0x00400000
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#define _8M 0x00800000
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#define _16M 0x01000000
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#define _32M 0x02000000
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#define _64M 0x04000000
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#define _128M 0x08000000
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#define _256M 0x10000000
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#define _512M 0x20000000
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/*
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* System memory mapping
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*/
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/* SDRAM: actual mapping is auto detected */
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#define SDRAM_CS0_BASE 0x00000000
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#define SDRAM_CS0_SIZE _8M
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#define SDRAM_CS1_BASE 0x00800000
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#define SDRAM_CS1_SIZE _8M
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#define SDRAM_CS2_BASE 0x01000000
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#define SDRAM_CS2_SIZE _8M
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#define SDRAM_CS3_BASE 0x01800000
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#define SDRAM_CS3_SIZE _8M
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/* PCI/PEX: IO and memory size */
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#define PCIx_IO_SIZE _1M
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#define PCIx_MEM0_SIZE _32M
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/* PEX Work arround */
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/* the target we will use for the workarround */
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#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM
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/*a flag that indicates if we are going to use the
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size and base of the target we using for the workarround
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window */
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/* PCI0: IO and memory space */
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#define PCI0_IO_BASE 0xf0000000
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#define PCI0_IO_SIZE _1M
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#define PCI0_MEM0_BASE 0xc0000000
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#define PCI0_MEM0_ME_BASE 0x90000000
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#define PCI0_MEM0_SIZE _64M
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#define PCI0_MEM0_ME_SIZE _32M
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/* PCI1: IO and memory space */
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#define PCI1_IO_BASE 0xf0100000
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#define PCI1_IO_SIZE _1M
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#define PCI1_MEM0_BASE 0xc4000000
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#define PCI1_MEM0_ME_BASE 0x92000000
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#define PCI1_MEM0_SIZE _64M
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#define PCI1_MEM0_ME_SIZE _32M
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/* PCI2: IO and memory space */
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#define PCI2_IO_BASE 0xf0200000
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#define PCI2_IO_SIZE _1M
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#define PCI2_MEM0_BASE 0xd0000000
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#define PCI2_MEM0_ME_BASE 0x94000000
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#define PCI2_MEM0_SIZE _64M
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#define PCI2_MEM0_ME_SIZE _32M
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/* PCI3: IO and memory space */
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#define PCI3_IO_BASE 0xf0300000
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#define PCI3_IO_SIZE _1M
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#define PCI3_MEM0_BASE 0xcc000000
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#define PCI3_MEM0_ME_BASE 0x96000000
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#define PCI3_MEM0_SIZE _64M
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#define PCI3_MEM0_ME_SIZE _32M
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/* PCI4: IO and memory space */
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#define PCI4_IO_BASE 0xf0400000
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#define PCI4_IO_SIZE _1M
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#define PCI4_MEM0_BASE 0xc8000000
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#define PCI4_MEM0_ME_BASE 0x98000000
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#define PCI4_MEM0_SIZE _64M
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#define PCI4_MEM0_ME_SIZE _32M
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/* PCI5: IO and memory space */
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#define PCI5_IO_BASE 0
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#define PCI5_IO_SIZE 0
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#define PCI5_MEM0_BASE 0xd4000000
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#define PCI5_MEM0_ME_BASE 0x9A000000
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#define PCI5_MEM0_SIZE _64M
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#define PCI5_MEM0_ME_SIZE _32M
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/* PCI6: IO and memory space */
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#define PCI6_IO_BASE 0
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#define PCI6_IO_SIZE 0
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#define PCI6_MEM0_BASE 0xd8000000
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#define PCI6_MEM0_ME_BASE 0x9C000000
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#define PCI6_MEM0_SIZE _64M
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#define PCI6_MEM0_ME_SIZE _32M
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/* PCI7: IO and memory space */
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#define PCI7_IO_BASE 0
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#define PCI7_IO_SIZE 0
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#define PCI7_MEM0_BASE 0xdc000000
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#define PCI7_MEM0_ME_BASE 0x9E000000
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#define PCI7_MEM0_SIZE _64M
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#define PCI7_MEM0_ME_SIZE _32M
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/* Crypto memory space */
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#define CRYPTO_BASE 0xd8000000
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#define CRYPTO_SIZE _1M
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/* Internal registers: size is defined in Controllerenvironment */
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#define INTER_REGS_BASE 0xf1000000 /*0x14000000*/
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/* #define IDMA_INTER_REGS_BASE 0xf1060000 0x14000000 */
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/* Device: CS0 - 32MB 32bit FLASH, CS1 - 7seg, CS2 - NAND, CS3 - SPI */
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#ifdef MV78200
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#define DEVICE_CS0_BASE 0xf8000000
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#define DEVICE_CS0_SIZE _1M
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#define DEVICE_CS1_BASE 0xf9000000
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#define DEVICE_CS1_SIZE _1M
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#define DEVICE_CS2_BASE 0xfc000000
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#define DEVICE_CS2_SIZE _8M
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#define DEVICE_CS3_BASE 0xfd000000
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#define DEVICE_CS3_SIZE _1M
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#else
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#define DEVICE_CS0_BASE 0xf8000000
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#define DEVICE_CS0_SIZE _1M
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#define DEVICE_CS1_BASE 0xf9000000
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#define DEVICE_CS1_SIZE _1M
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#define DEVICE_CS2_BASE 0xfc000000
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#define DEVICE_CS2_SIZE _1M
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#define DEVICE_CS3_BASE 0xfd000000
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#define DEVICE_CS3_SIZE _8M
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#endif
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#define BOOTDEV_CS_BASE ((0xFFFFFFFF - BOOTDEV_CS_SIZE) + 1)
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#ifdef MV78200
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#define DEVICE_SPI_BASE DEVICE_CS2_BASE
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#define DEVICE_SPI_SIZE DEVICE_CS2_SIZE
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#else
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#define DEVICE_SPI_BASE DEVICE_CS3_BASE
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#define DEVICE_SPI_SIZE DEVICE_CS3_SIZE
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#endif
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#ifdef MV632X
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#undef DEVICE_SPI_BASE
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#undef DEVICE_SPI_SIZE
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#undef BOOTDEV_CS_BASE
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#ifdef MV_NAND_BOOT
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#define DEVICE_SPI_BASE DEVICE_CS2_BASE
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#define DEVICE_SPI_SIZE _8M
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#define BOOTDEV_CS_BASE ((0xFFFFFFFF - BOOTDEV_CS_SIZE) + 1)
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#else /*MV_NAND_BOOT*/
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#define DEVICE_SPI_BASE ((0xFFFFFFFF - _8M) + 1)
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#define DEVICE_SPI_SIZE _8M
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#define BOOTDEV_CS_BASE DEVICE_CS2_BASE
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#endif /*MV_NAND_BOOT*/
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#endif /* MV632X */
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#if defined(MV_NAND_BOOT)
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#define BOOTDEV_CS_SIZE _512K
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#elif defined(MV_BOOTSIZE_256K)
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#define BOOTDEV_CS_SIZE _256K
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#elif defined(MV_BOOTSIZE_512K)
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#define BOOTDEV_CS_SIZE _512K
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#elif defined(MV_BOOTSIZE_4M)
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#define BOOTDEV_CS_SIZE _4M
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#elif defined(MV_BOOTSIZE_8M)
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#define BOOTDEV_CS_SIZE _8M
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#elif defined(MV_BOOTSIZE_16M)
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#define BOOTDEV_CS_SIZE _16M
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#elif defined(MV_BOOTSIZE_32M)
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#define BOOTDEV_CS_SIZE _32M
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#elif defined(MV_BOOTSIZE_64M)
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#define BOOTDEV_CS_SIZE _64M
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#else
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#define Error MV_BOOTSIZE undefined
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#endif
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#if defined(MV632X)
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#undef MV_INC_BOARD_NOR_FLASH
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#endif
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#if !defined(MV_NAND_BOOT)
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#ifdef MV78200
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#ifdef RD_MV78XX0_AMC
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#define CFG_NAND_BASE DEVICE_CS2_BASE
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#elif defined(MV632X)
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#define CFG_NAND_BASE BOOTDEV_CS_BASE
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#else /*MV632X*/
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#define CFG_NAND_BASE DEVICE_CS3_BASE
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#endif
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#else /*MV78200*/
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#define CFG_NAND_BASE DEVICE_CS2_BASE
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#endif
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#else /*MV_NAND_BOOT*/
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#define CFG_NAND_BASE BOOTDEV_CS_BASE
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#endif /*MV_NAND_BOOT*/
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#if (defined(DB_MV78XX0) || defined(MV78200) || defined(RD_MV78XX0_PCAC)) && !defined(MV_SPI_BOOT)
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#define BOOT_FLASH_INDEX 0
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#define MAIN_FLASH_INDEX 1
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#else
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#define BOOT_FLASH_INDEX 1
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#define MAIN_FLASH_INDEX 0
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#endif
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/* DRAM detection stuff */
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#define MV_DRAM_AUTO_SIZE
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/* These addresses defines the place where global parameters will be placed */
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/* in case running from ROM. We Use SYS_MEM_TOP. See bootInit.c file */
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#define DRAM_DETECT_FLAG_ADDR 0x03000000
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#define DRAM_CONFIG_ROM_ADDR 0x03000004
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#ifdef RD_MV78XX0_AMC
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#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \
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/* base low base high size WinNum enable/disable */ \
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{{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, EN },/* 0 */ \
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{{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, EN },/* 1 */ \
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{{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, EN },/* 2 */ \
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{{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, EN },/* 3 */ \
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{{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE}, 10, EN },/* 4 */ \
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{{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE}, 11, EN },/* 5 */ \
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{{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE}, 12, DIS },/* 6 */ \
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{{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE}, 9, EN },/* 7 */ \
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{{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE}, 13, EN },/* 8 */ \
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{{DEVICE_SPI_BASE, 0, DEVICE_SPI_SIZE}, 12, EN },/* 7 */ \
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{{PCI0_IO_BASE , 0, PCI0_IO_SIZE }, 0, DIS },/* 9 */ \
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{{PCI0_MEM0_BASE , 0, PCI0_MEM0_SIZE }, 0, EN },/* 10 */ \
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{{PCI1_IO_BASE , 0, PCI1_IO_SIZE }, 1, DIS },/* 11 */ \
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{{PCI1_MEM0_BASE , 0, PCI1_MEM0_SIZE }, 1, EN },/* 12 */ \
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{{PCI2_IO_BASE , 0, PCI2_IO_SIZE }, 2, DIS},/* 13 */ \
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{{PCI2_MEM0_BASE , 0, PCI2_MEM0_SIZE }, 2, EN},/* 14 */ \
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{{PCI3_IO_BASE , 0, PCI3_IO_SIZE }, 3, DIS },/* 15 */ \
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{{PCI3_MEM0_BASE , 0, PCI3_MEM0_SIZE }, 3, EN },/* 16 */ \
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{{PCI4_IO_BASE , 0, PCI4_IO_SIZE }, 4, DIS },/* 17 */ \
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{{PCI4_MEM0_BASE , 0, PCI4_MEM0_SIZE }, 4, EN },/* 18 */ \
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{{PCI5_IO_BASE , 0, PCI5_IO_SIZE }, 5, DIS},/* 19 */ \
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{{PCI5_MEM0_BASE , 0, PCI5_MEM0_SIZE }, 5, EN},/* 20 */ \
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{{PCI6_IO_BASE , 0, PCI6_IO_SIZE }, 6, DIS},/* 21 */ \
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{{PCI6_MEM0_BASE , 0, PCI6_MEM0_SIZE }, 6, EN},/* 22 */ \
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{{PCI7_IO_BASE , 0, PCI7_IO_SIZE }, 7, DIS},/* 23 */ \
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{{PCI7_MEM0_BASE , 0, PCI7_MEM0_SIZE }, 7, EN},/* 24 */ \
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{{CRYPTO_BASE , 0, CRYPTO_SIZE }, 8, EN },/* 25 */ \
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{{INTER_REGS_BASE, 0, INTER_REGS_SIZE}, 14, EN },/* 26 */ \
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/* Table terminator */ \
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{{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM, TBL_TERM} \
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};
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#define MV_CPU_IF_ADDR_WIN_MON_EXT_MAP_TBL { \
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/* base low base high size WinNum enable/disable */ \
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{{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, EN },/* 0 */ \
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{{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, EN },/* 1 */ \
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{{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, EN },/* 2 */ \
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{{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, EN },/* 3 */ \
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{{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE}, 10, EN },/* 4 */ \
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{{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE}, 11, EN },/* 5 */ \
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{{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE}, 12, DIS },/* 6 */ \
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{{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE}, 9, EN },/* 7 */ \
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{{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE}, 13, EN },/* 8 */ \
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{{DEVICE_SPI_BASE, 0, DEVICE_SPI_SIZE}, 12, EN },/* 7 */ \
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{{PCI0_IO_BASE , 0, PCI0_IO_SIZE }, 0, DIS },/* 9 */ \
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{{PCI0_MEM0_ME_BASE, 0, PCI0_MEM0_ME_SIZE }, 0, EN },/* 10 */ \
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{{PCI1_IO_BASE , 0, PCI1_IO_SIZE }, 1, DIS },/* 11 */ \
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{{PCI1_MEM0_ME_BASE, 0, PCI1_MEM0_ME_SIZE }, 1, EN },/* 12 */ \
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{{PCI2_IO_BASE , 0, PCI2_IO_SIZE }, 2, DIS},/* 13 */ \
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{{PCI2_MEM0_ME_BASE, 0, PCI2_MEM0_ME_SIZE }, 2, EN},/* 14 */ \
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{{PCI3_IO_BASE , 0, PCI3_IO_SIZE }, 3, DIS },/* 15 */ \
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{{PCI3_MEM0_ME_BASE, 0, PCI3_MEM0_ME_SIZE }, 3, EN },/* 16 */ \
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{{PCI4_IO_BASE , 0, PCI4_IO_SIZE }, 4, DIS },/* 17 */ \
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{{PCI4_MEM0_ME_BASE, 0, PCI4_MEM0_ME_SIZE }, 4, EN },/* 18 */ \
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{{PCI5_IO_BASE , 0, PCI5_IO_SIZE }, 5, DIS},/* 19 */ \
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{{PCI5_MEM0_ME_BASE, 0, PCI5_MEM0_ME_SIZE }, 5, EN},/* 20 */ \
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{{PCI6_IO_BASE , 0, PCI6_IO_SIZE }, 6, DIS},/* 21 */ \
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{{PCI6_MEM0_ME_BASE, 0, PCI6_MEM0_ME_SIZE }, 6, EN},/* 22 */ \
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{{PCI7_IO_BASE , 0, PCI7_IO_SIZE }, 7, DIS},/* 23 */ \
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{{PCI7_MEM0_ME_BASE, 0, PCI7_MEM0_ME_SIZE }, 7, EN},/* 24 */ \
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{{CRYPTO_BASE , 0, CRYPTO_SIZE }, 8, EN },/* 25 */ \
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{{INTER_REGS_BASE, 0, INTER_REGS_SIZE}, 14, EN },/* 26 */ \
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/* Table terminator */ \
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{{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM, TBL_TERM} \
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};
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#elif defined(DB_MV88F632X)
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#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \
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/* base low base high size WinNum enable/disable */ \
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{{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, EN },/* 0 */ \
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{{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, EN },/* 1 */ \
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{{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, EN },/* 2 */ \
|
|
{{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, EN },/* 3 */ \
|
|
{{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE}, 10, DIS },/* 4 */ \
|
|
{{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE}, 11, DIS },/* 5 */ \
|
|
{{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE}, 12, DIS },/* 6 */ \
|
|
{{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE}, 9, DIS },/* 7 */ \
|
|
{{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE}, 13, EN },/* 8 */ \
|
|
{{DEVICE_SPI_BASE, 0, DEVICE_SPI_SIZE}, 12, EN },/* 7 */ \
|
|
{{PCI0_IO_BASE , 0, PCI0_IO_SIZE }, 0, EN },/* 9 */ \
|
|
{{PCI0_MEM0_BASE , 0, PCI0_MEM0_SIZE }, 1, EN },/* 10 */ \
|
|
{{PCI1_IO_BASE , 0, PCI1_IO_SIZE }, 2, DIS },/* 11 */ \
|
|
{{PCI1_MEM0_BASE , 0, PCI1_MEM0_SIZE }, 3, DIS },/* 12 */ \
|
|
{{PCI2_IO_BASE , 0, PCI2_IO_SIZE }, 4, DIS},/* 13 */ \
|
|
{{PCI2_MEM0_BASE , 0, PCI2_MEM0_SIZE }, 5, DIS},/* 14 */ \
|
|
{{PCI3_IO_BASE , 0, PCI3_IO_SIZE }, 4, DIS },/* 15 */ \
|
|
{{PCI3_MEM0_BASE , 0, PCI3_MEM0_SIZE }, 5, DIS },/* 16 */ \
|
|
{{PCI4_IO_BASE , 0, PCI4_IO_SIZE }, 6, EN },/* 17 */ \
|
|
{{PCI4_MEM0_BASE , 0, PCI4_MEM0_SIZE }, 7, EN },/* 18 */ \
|
|
{{PCI5_IO_BASE , 0, PCI5_IO_SIZE }, 5, DIS},/* 19 */ \
|
|
{{PCI5_MEM0_BASE , 0, PCI5_MEM0_SIZE }, 5, DIS},/* 20 */ \
|
|
{{PCI6_IO_BASE , 0, PCI6_IO_SIZE }, 6, DIS},/* 21 */ \
|
|
{{PCI6_MEM0_BASE , 0, PCI6_MEM0_SIZE }, 6, DIS},/* 22 */ \
|
|
{{PCI7_IO_BASE , 0, PCI7_IO_SIZE }, 7, DIS},/* 23 */ \
|
|
{{PCI7_MEM0_BASE , 0, PCI7_MEM0_SIZE }, 7, DIS},/* 24 */ \
|
|
{{CRYPTO_BASE , 0, CRYPTO_SIZE }, 8, EN },/* 25 */ \
|
|
{{INTER_REGS_BASE, 0, INTER_REGS_SIZE}, 14, EN },/* 26 */ \
|
|
/* Table terminator */ \
|
|
{{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM, TBL_TERM} \
|
|
};
|
|
|
|
#define MV_CPU_IF_ADDR_WIN_MON_EXT_MAP_TBL { \
|
|
/* base low base high size WinNum enable/disable */ \
|
|
{{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, EN },/* 0 */ \
|
|
{{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, EN },/* 1 */ \
|
|
{{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, EN },/* 2 */ \
|
|
{{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, EN },/* 3 */ \
|
|
{{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE}, 10, DIS },/* 4 */ \
|
|
{{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE}, 11, DIS },/* 5 */ \
|
|
{{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE}, 12, DIS },/* 6 */ \
|
|
{{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE}, 9, DIS },/* 7 */ \
|
|
{{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE}, 13, EN },/* 8 */ \
|
|
{{DEVICE_SPI_BASE, 0, DEVICE_SPI_SIZE}, 12, EN },/* 7 */ \
|
|
{{PCI0_IO_BASE , 0, PCI0_IO_SIZE }, 0, EN },/* 9 */ \
|
|
{{PCI0_MEM0_ME_BASE, 0, PCI0_MEM0_ME_SIZE }, 1, EN },/* 10 */ \
|
|
{{PCI1_IO_BASE , 0, PCI1_IO_SIZE }, 2, DIS },/* 11 */ \
|
|
{{PCI1_MEM0_ME_BASE, 0, PCI1_MEM0_ME_SIZE }, 3, DIS },/* 12 */ \
|
|
{{PCI2_IO_BASE , 0, PCI2_IO_SIZE }, 4, DIS},/* 13 */ \
|
|
{{PCI2_MEM0_BASE , 0, PCI2_MEM0_ME_SIZE }, 5, DIS},/* 14 */ \
|
|
{{PCI3_IO_BASE , 0, PCI3_IO_SIZE }, 4, DIS },/* 15 */ \
|
|
{{PCI3_MEM0_ME_BASE, 0, PCI3_MEM0_ME_SIZE }, 5, DIS },/* 16 */ \
|
|
{{PCI4_IO_BASE , 0, PCI4_IO_SIZE }, 6, EN },/* 17 */ \
|
|
{{PCI4_MEM0_ME_BASE, 0, PCI4_MEM0_ME_SIZE }, 7, EN },/* 18 */ \
|
|
{{PCI5_IO_BASE , 0, PCI5_IO_SIZE }, 5, DIS},/* 19 */ \
|
|
{{PCI5_MEM0_ME_BASE , 0, PCI5_MEM0_ME_SIZE }, 5, DIS},/* 20 */ \
|
|
{{PCI6_IO_BASE , 0, PCI6_IO_SIZE }, 6, DIS},/* 21 */ \
|
|
{{PCI6_MEM0_ME_BASE , 0, PCI6_MEM0_ME_SIZE }, 6, DIS},/* 22 */ \
|
|
{{PCI7_IO_BASE , 0, PCI7_IO_SIZE }, 7, DIS},/* 23 */ \
|
|
{{PCI7_MEM0_ME_BASE , 0, PCI7_MEM0_ME_SIZE }, 7, DIS},/* 24 */ \
|
|
{{CRYPTO_BASE , 0, CRYPTO_SIZE }, 8, EN },/* 25 */ \
|
|
{{INTER_REGS_BASE, 0, INTER_REGS_SIZE}, 14, EN },/* 26 */ \
|
|
/* Table terminator */ \
|
|
{{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM, TBL_TERM} \
|
|
};
|
|
#elif MV78200
|
|
#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \
|
|
/* base low base high size WinNum enable/disable */ \
|
|
{{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, EN },/* 0 */ \
|
|
{{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, EN },/* 1 */ \
|
|
{{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, EN },/* 2 */ \
|
|
{{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, EN },/* 3 */ \
|
|
{{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE}, 10, EN },/* 4 */ \
|
|
{{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE}, 11, EN },/* 5 */ \
|
|
{{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE}, 12, DIS },/* 6 */ \
|
|
{{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE}, 9, EN },/* 7 */ \
|
|
{{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE}, 13, EN },/* 8 */ \
|
|
{{DEVICE_SPI_BASE, 0, DEVICE_SPI_SIZE}, 12, EN },/* 7 */ \
|
|
{{PCI0_IO_BASE , 0, PCI0_IO_SIZE }, 0, EN },/* 9 */ \
|
|
{{PCI0_MEM0_BASE , 0, PCI0_MEM0_SIZE }, 1, EN },/* 10 */ \
|
|
{{PCI1_IO_BASE , 0, PCI1_IO_SIZE }, 2, EN },/* 11 */ \
|
|
{{PCI1_MEM0_BASE , 0, PCI1_MEM0_SIZE }, 3, EN },/* 12 */ \
|
|
{{PCI2_IO_BASE , 0, PCI2_IO_SIZE }, 4, DIS},/* 13 */ \
|
|
{{PCI2_MEM0_BASE , 0, PCI2_MEM0_SIZE }, 5, DIS},/* 14 */ \
|
|
{{PCI3_IO_BASE , 0, PCI3_IO_SIZE }, 4, EN },/* 15 */ \
|
|
{{PCI3_MEM0_BASE , 0, PCI3_MEM0_SIZE }, 5, EN },/* 16 */ \
|
|
{{PCI4_IO_BASE , 0, PCI4_IO_SIZE }, 6, EN },/* 17 */ \
|
|
{{PCI4_MEM0_BASE , 0, PCI4_MEM0_SIZE }, 7, EN },/* 18 */ \
|
|
{{PCI5_IO_BASE , 0, PCI5_IO_SIZE }, 5, DIS},/* 19 */ \
|
|
{{PCI5_MEM0_BASE , 0, PCI5_MEM0_SIZE }, 5, DIS},/* 20 */ \
|
|
{{PCI6_IO_BASE , 0, PCI6_IO_SIZE }, 6, DIS},/* 21 */ \
|
|
{{PCI6_MEM0_BASE , 0, PCI6_MEM0_SIZE }, 6, DIS},/* 22 */ \
|
|
{{PCI7_IO_BASE , 0, PCI7_IO_SIZE }, 7, DIS},/* 23 */ \
|
|
{{PCI7_MEM0_BASE , 0, PCI7_MEM0_SIZE }, 7, DIS},/* 24 */ \
|
|
{{CRYPTO_BASE , 0, CRYPTO_SIZE }, 8, EN },/* 25 */ \
|
|
{{INTER_REGS_BASE, 0, INTER_REGS_SIZE}, 14, EN },/* 26 */ \
|
|
/* Table terminator */ \
|
|
{{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM, TBL_TERM} \
|
|
};
|
|
|
|
#define MV_CPU_IF_ADDR_WIN_MON_EXT_MAP_TBL { \
|
|
/* base low base high size WinNum enable/disable */ \
|
|
{{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, EN },/* 0 */ \
|
|
{{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, EN },/* 1 */ \
|
|
{{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, EN },/* 2 */ \
|
|
{{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, EN },/* 3 */ \
|
|
{{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE}, 10, EN },/* 4 */ \
|
|
{{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE}, 11, EN },/* 5 */ \
|
|
{{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE}, 12, DIS },/* 6 */ \
|
|
{{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE}, 9, EN },/* 7 */ \
|
|
{{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE}, 13, EN },/* 8 */ \
|
|
{{DEVICE_SPI_BASE, 0, DEVICE_SPI_SIZE}, 12, EN },/* 7 */ \
|
|
{{PCI0_IO_BASE , 0, PCI0_IO_SIZE }, 0, EN },/* 9 */ \
|
|
{{PCI0_MEM0_ME_BASE, 0, PCI0_MEM0_ME_SIZE }, 1, EN },/* 10 */ \
|
|
{{PCI1_IO_BASE , 0, PCI1_IO_SIZE }, 2, EN },/* 11 */ \
|
|
{{PCI1_MEM0_ME_BASE, 0, PCI1_MEM0_ME_SIZE }, 3, EN },/* 12 */ \
|
|
{{PCI2_IO_BASE , 0, PCI2_IO_SIZE }, 4, DIS},/* 13 */ \
|
|
{{PCI2_MEM0_BASE , 0, PCI2_MEM0_ME_SIZE }, 5, DIS},/* 14 */ \
|
|
{{PCI3_IO_BASE , 0, PCI3_IO_SIZE }, 4, EN },/* 15 */ \
|
|
{{PCI3_MEM0_ME_BASE, 0, PCI3_MEM0_ME_SIZE }, 5, EN },/* 16 */ \
|
|
{{PCI4_IO_BASE , 0, PCI4_IO_SIZE }, 6, EN },/* 17 */ \
|
|
{{PCI4_MEM0_ME_BASE, 0, PCI4_MEM0_ME_SIZE }, 7, EN },/* 18 */ \
|
|
{{PCI5_IO_BASE , 0, PCI5_IO_SIZE }, 5, DIS},/* 19 */ \
|
|
{{PCI5_MEM0_ME_BASE , 0, PCI5_MEM0_ME_SIZE }, 5, DIS},/* 20 */ \
|
|
{{PCI6_IO_BASE , 0, PCI6_IO_SIZE }, 6, DIS},/* 21 */ \
|
|
{{PCI6_MEM0_ME_BASE , 0, PCI6_MEM0_ME_SIZE }, 6, DIS},/* 22 */ \
|
|
{{PCI7_IO_BASE , 0, PCI7_IO_SIZE }, 7, DIS},/* 23 */ \
|
|
{{PCI7_MEM0_ME_BASE , 0, PCI7_MEM0_ME_SIZE }, 7, DIS},/* 24 */ \
|
|
{{CRYPTO_BASE , 0, CRYPTO_SIZE }, 8, EN },/* 25 */ \
|
|
{{INTER_REGS_BASE, 0, INTER_REGS_SIZE}, 14, EN },/* 26 */ \
|
|
/* Table terminator */ \
|
|
{{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM, TBL_TERM} \
|
|
};
|
|
#else
|
|
#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \
|
|
/* base low base high size WinNum enable/disable */ \
|
|
{{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, EN },/* 0 */ \
|
|
{{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, EN },/* 1 */ \
|
|
{{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, EN },/* 2 */ \
|
|
{{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, EN },/* 3 */ \
|
|
{{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE}, 10, EN },/* 4 */ \
|
|
{{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE}, 11, EN },/* 5 */ \
|
|
{{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE}, 12, EN },/* 6 */ \
|
|
{{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE}, 9, DIS },/* 7 */ \
|
|
{{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE}, 13, EN },/* 8 */ \
|
|
{{DEVICE_SPI_BASE, 0, DEVICE_SPI_SIZE}, 9, EN },/* 7 */ \
|
|
{{PCI0_IO_BASE , 0, PCI0_IO_SIZE }, 0, EN },/* 9 */ \
|
|
{{PCI0_MEM0_BASE , 0, PCI0_MEM0_SIZE }, 1, EN },/* 10 */ \
|
|
{{PCI1_IO_BASE , 0, PCI1_IO_SIZE }, 2, EN },/* 11 */ \
|
|
{{PCI1_MEM0_BASE , 0, PCI1_MEM0_SIZE }, 3, EN },/* 12 */ \
|
|
{{PCI2_IO_BASE , 0, PCI2_IO_SIZE }, 4, DIS},/* 13 */ \
|
|
{{PCI2_MEM0_BASE , 0, PCI2_MEM0_SIZE }, 5, DIS},/* 14 */ \
|
|
{{PCI3_IO_BASE , 0, PCI3_IO_SIZE }, 4, EN },/* 15 */ \
|
|
{{PCI3_MEM0_BASE , 0, PCI3_MEM0_SIZE }, 5, EN },/* 16 */ \
|
|
{{PCI4_IO_BASE , 0, PCI4_IO_SIZE }, 6, EN },/* 17 */ \
|
|
{{PCI4_MEM0_BASE , 0, PCI4_MEM0_SIZE }, 7, EN },/* 18 */ \
|
|
{{PCI5_IO_BASE , 0, PCI5_IO_SIZE }, 5, DIS},/* 19 */ \
|
|
{{PCI5_MEM0_BASE , 0, PCI5_MEM0_SIZE }, 5, DIS},/* 20 */ \
|
|
{{PCI6_IO_BASE , 0, PCI6_IO_SIZE }, 6, DIS},/* 21 */ \
|
|
{{PCI6_MEM0_BASE , 0, PCI6_MEM0_SIZE }, 6, DIS},/* 22 */ \
|
|
{{PCI7_IO_BASE , 0, PCI7_IO_SIZE }, 7, DIS},/* 23 */ \
|
|
{{PCI7_MEM0_BASE , 0, PCI7_MEM0_SIZE }, 7, DIS},/* 24 */ \
|
|
{{CRYPTO_BASE , 0, CRYPTO_SIZE }, 8, EN },/* 25 */ \
|
|
{{INTER_REGS_BASE, 0, INTER_REGS_SIZE}, 14, EN },/* 26 */ \
|
|
/* Table terminator */ \
|
|
{{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM, TBL_TERM} \
|
|
};
|
|
|
|
#define MV_CPU_IF_ADDR_WIN_MON_EXT_MAP_TBL { \
|
|
/* base low base high size WinNum enable/disable */ \
|
|
{{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, EN },/* 0 */ \
|
|
{{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, EN },/* 1 */ \
|
|
{{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, EN },/* 2 */ \
|
|
{{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, EN },/* 3 */ \
|
|
{{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE}, 10, EN },/* 4 */ \
|
|
{{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE}, 11, EN },/* 5 */ \
|
|
{{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE}, 12, EN },/* 6 */ \
|
|
{{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE}, 9, DIS },/* 7 */ \
|
|
{{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE}, 13, EN },/* 8 */ \
|
|
{{DEVICE_SPI_BASE, 0, DEVICE_SPI_SIZE}, 9, EN },/* 7 */ \
|
|
{{PCI0_IO_BASE , 0, PCI0_IO_SIZE }, 0, EN },/* 9 */ \
|
|
{{PCI0_MEM0_ME_BASE, 0, PCI0_MEM0_ME_SIZE }, 1, EN },/* 10 */ \
|
|
{{PCI1_IO_BASE , 0, PCI1_IO_SIZE }, 2, EN },/* 11 */ \
|
|
{{PCI1_MEM0_ME_BASE, 0, PCI1_MEM0_ME_SIZE }, 3, EN },/* 12 */ \
|
|
{{PCI2_IO_BASE , 0, PCI2_IO_SIZE }, 4, DIS},/* 13 */ \
|
|
{{PCI2_MEM0_ME_BASE , 0, PCI2_MEM0_ME_SIZE }, 5, DIS},/* 14 */ \
|
|
{{PCI3_IO_BASE , 0, PCI3_IO_SIZE }, 4, EN },/* 15 */ \
|
|
{{PCI3_MEM0_ME_BASE, 0, PCI3_MEM0_ME_SIZE }, 5, EN },/* 16 */ \
|
|
{{PCI4_IO_BASE , 0, PCI4_IO_SIZE }, 6, EN },/* 17 */ \
|
|
{{PCI4_MEM0_ME_BASE, 0, PCI4_MEM0_ME_SIZE }, 7, EN },/* 18 */ \
|
|
{{PCI5_IO_BASE , 0, PCI5_IO_SIZE }, 5, DIS},/* 19 */ \
|
|
{{PCI5_MEM0_ME_BASE , 0, PCI5_MEM0_ME_SIZE }, 5, DIS},/* 20 */ \
|
|
{{PCI6_IO_BASE , 0, PCI6_IO_SIZE }, 6, DIS},/* 21 */ \
|
|
{{PCI6_MEM0_ME_BASE , 0, PCI6_MEM0_ME_SIZE }, 6, DIS},/* 22 */ \
|
|
{{PCI7_IO_BASE , 0, PCI7_IO_SIZE }, 7, DIS},/* 23 */ \
|
|
{{PCI7_MEM0_ME_BASE , 0, PCI7_MEM0_ME_SIZE }, 7, DIS},/* 24 */ \
|
|
{{CRYPTO_BASE , 0, CRYPTO_SIZE }, 8, EN },/* 25 */ \
|
|
{{INTER_REGS_BASE, 0, INTER_REGS_SIZE}, 14, EN },/* 26 */ \
|
|
/* Table terminator */ \
|
|
{{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM, TBL_TERM} \
|
|
};
|
|
#endif
|
|
|
|
/* We use the following registers to store DRAM interface pre configuration */
|
|
/* auto-detection results */
|
|
#define DRAM_BUF_REG0 0x60810 /* sdram bank 0 size */
|
|
#define DRAM_BUF_REG1 0x60814 /* sdram config */
|
|
#define DRAM_BUF_REG2 0x60818 /* sdram mode */
|
|
#define DRAM_BUF_REG3 0x6081c /* dunit control low */
|
|
#define DRAM_BUF_REG4 0x60820 /* sdram address control */
|
|
#define DRAM_BUF_REG5 0x60824 /* sdram timing control low */
|
|
#define DRAM_BUF_REG6 0x60828 /* sdram timing control high */
|
|
#define DRAM_BUF_REG7 0x6082c /* sdram ODT control low */
|
|
#define DRAM_BUF_REG8 0x60830 /* sdram ODT control high */
|
|
#define DRAM_BUF_REG9 0x60834 /* sdram Dunit ODT control */
|
|
#define DRAM_BUF_REG10 0x60838 /* sdram Extended Mode */
|
|
#define DRAM_BUF_REG11 0x6083c /* sdram Ddr2 Timing Low */
|
|
#define DRAM_BUF_REG12 0x60870 /* sdram Ddr2 Timing High */
|
|
#define DRAM_BUF_REG13 0x60874 /* dunit control high */
|
|
#define DRAM_BUF_REG14 0x60878 /* if == '1' second dimm exist */
|
|
|
|
/* HW cache coherency configuration */
|
|
#define DRAM_COHERENCY NO_COHERENCY
|
|
|
|
/* PCI stuff */
|
|
/* Local bus and device number of PCI0/1*/
|
|
#define PCI_HOST_BUS_NUM(pciIf) 0
|
|
#define PCI_HOST_DEV_NUM(pciIf) 0
|
|
#define PEX_HOST_BUS_NUM(pexIf) (1 * pexIf)
|
|
#define PEX_HOST_DEV_NUM(pexIf) 0
|
|
|
|
|
|
#define PCI_ARBITER_CTRL /* Use/unuse the Marvell integrated PCI arbiter */
|
|
#undef PCI_ARBITER_BOARD /* Use/unuse the PCI arbiter on board */
|
|
|
|
/* Check macro validity */
|
|
#if defined(PCI_ARBITER_CTRL) && defined (PCI_ARBITER_BOARD)
|
|
#error "Please select either integrated PCI arbiter or board arbiter"
|
|
#endif
|
|
|
|
/* Board clock detection */
|
|
#undef TCLK_AUTO_DETECT /* Use Tclk auto detection */
|
|
#undef SYSCLK_AUTO_DETECT /* Use SysClk auto detection */
|
|
|
|
/* Memory uncached, HW or SW cache coherency is not needed */
|
|
#define MV_UNCACHED 0
|
|
/* Memory cached, HW cache coherency supported in WriteThrough mode */
|
|
#define MV_CACHE_COHER_HW_WT 1
|
|
/* Memory cached, HW cache coherency supported in WriteBack mode */
|
|
#define MV_CACHE_COHER_HW_WB 2
|
|
/* Memory cached, No HW cache coherency, Cache coherency must be in SW */
|
|
#define MV_CACHE_COHER_SW 3
|
|
|
|
|
|
#if INTEG_SRAM_COHER == MV_CACHE_COHER_HW_WB
|
|
# define INTEG_SRAM_CONFIG_STR "MV_CACHE_COHER_HW_WB"
|
|
#elif INTEG_SRAM_COHER == MV_CACHE_COHER_HW_WT
|
|
# define INTEG_SRAM_CONFIG_STR "MV_CACHE_COHER_HW_WT"
|
|
#elif INTEG_SRAM_COHER == MV_CACHE_COHER_SW
|
|
# define INTEG_SRAM_CONFIG_STR "MV_CACHE_COHER_SW"
|
|
#elif INTEG_SRAM_COHER == MV_UNCACHED
|
|
# define INTEG_SRAM_CONFIG_STR "MV_UNCACHED"
|
|
#else
|
|
# error "Unexpected INTEG_SRAM_COHER value"
|
|
#endif /* INTEG_SRAM_COHER */
|
|
|
|
/************* Ethernet driver configuration ********************/
|
|
|
|
/*#define ETH_JUMBO_SUPPORT*/
|
|
#define ETH_DEF_TXQ 0
|
|
#define ETH_DEF_RXQ 0
|
|
#define MV_ETH_TX_Q_NUM 1
|
|
#define MV_ETH_RX_Q_NUM 1
|
|
#define ETH_NUM_OF_RX_DESCR 64
|
|
#define ETH_NUM_OF_TX_DESCR ETH_NUM_OF_RX_DESCR*2
|
|
|
|
#define ETH_DESCR_IN_SDRAM
|
|
#undef ETH_DESCR_IN_SRAM
|
|
|
|
#if defined(ETH_DESCR_IN_SRAM)
|
|
# define ETH_DESCR_CONFIG_STR "ETH_DESCR_IN_SRAM"
|
|
#elif defined(ETH_DESCR_IN_SDRAM)
|
|
# define ETH_DESCR_CONFIG_STR "ETH_DESCR_IN_SDRAM"
|
|
#else
|
|
# error "ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM must be defined"
|
|
#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/
|
|
|
|
#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB)
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# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WB"
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#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT)
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# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WT"
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#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW)
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# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_SW"
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#elif (ETHER_DRAM_COHER == MV_UNCACHED)
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# define ETH_SDRAM_CONFIG_STR "MV_UNCACHED"
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#else
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# error "Unexpected ETHER_DRAM_COHER value"
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#endif /* ETHER_DRAM_COHER */
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/*********** Idma default configuration ***********/
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#define UBOOT_CNTRL_DMA_DV (ICCLR_DST_BURST_LIM_8BYTE | \
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ICCLR_SRC_INC | \
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ICCLR_DST_INC | \
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|
ICCLR_SRC_BURST_LIM_8BYTE | \
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|
ICCLR_NON_CHAIN_MODE | \
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ICCLR_BLOCK_MODE )
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|
|
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#define MV_BRIDGE_REORDER_WA(param) \
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|
{ \
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volatile MV_U8 dummy = (MV_U8)param;\
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}
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|
|
|
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#endif /* __INCmvSysHwConfigh */
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