273 lines
8.3 KiB
ArmAsm
273 lines
8.3 KiB
ArmAsm
#define MV_ASMLANGUAGE
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#include "ddr2/mvDramIfRegs.h"
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#include "ddr2/mvDramIfConfig.h"
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#include "nBootstrap.h"
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#include "ctrlEnv/mvCtrlEnvSpec.h"
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/* #define NAND_DEBUG */
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#if !defined(MV_BOOTROM)
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.globl nbootStart
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nbootStart:
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/*
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* set the cpu to SVC32 mode, I and F disabled.
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*/
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mov r1, #0xd3
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msr cpsr,r1
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/*
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* flush v4 I/D caches
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*/
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mcr p15, 0, r1, c7, c7, 0 /* invalidate v3/v4 cache */
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r1, c1, c0, 0
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bic r1, r1, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
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bic r1, r1, #0x00000007 /* clear bits 2:0 (-CAM) */
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orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */
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/* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */
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mcr p15, 0, r1, c1, c0, 0
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/* Add nop commands for cache flush operations */
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nop
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nop
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nop
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nop
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nop
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/* here. MUST BE IN THE SAME CACHE LINE */
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mov r0, #0 /* We use r0 as always '0' */
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/* lock I-Cache */
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mrc p15, 0, r8, c9, c0, 1
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orr r8, r8, #0xf
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mcr p15, 0, r8, c9, c0, 1
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/* Start load code into I-Cache */
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mov r2, #0x500
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mov r8, pc
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.align 5
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bic r8, #0x1f
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add r8, r8, #32
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load_loop:
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mcr p15, 0, r8, c7, c13, 1
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add r8, r8, #32 /* 8 dwords * 4 bytes */
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sub r2, r2, #32 /* 8 dwords * 4 bytes */
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cmp r2, #0 /* check if we have read a full Page */
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bne load_loop
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#ifdef NAND_DEBUG
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/* GPP initialization */
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mov r2, #0xd0000000
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orr r2, r2, #0x10000
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mov r1, #0xf0ffffff
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MV_REG_WRITE_ASM(r1, r2, 0x104)
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mov r1, #0x1000000
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MV_REG_WRITE_ASM(r1, r2, 0x100)
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#endif
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/* DRAM memory initialization */
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/* Load SDRAM controller base address 0xd0001000 */
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mov r2, #0xd0000000
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orr r2, r2, #0x1000
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/* Write to SDRAM coniguration register */
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GPR_LOAD(r1, MV_32BIT_LE(SDRAM_CONFIG_REG_DV))
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MV_REG_WRITE_ASM(r1, r2, SDRAM_CONFIG_REG)
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/* Write Dunit control low register */
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GPR_LOAD(r1, MV_32BIT_LE(SDRAM_DUNIT_CTRL_REG_DV))
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MV_REG_WRITE_ASM(r1, r2, SDRAM_DUNIT_CTRL_REG)
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/* Write SDRAM address control register */
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GPR_LOAD(r1, MV_32BIT_LE(SDRAM_ADDR_CTRL_REG_DV))
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MV_REG_WRITE_ASM(r1, r2, SDRAM_ADDR_CTRL_REG)
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/* Write SDRAM timing Low register */
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GPR_LOAD(r1, MV_32BIT_LE(SDRAM_TIMING_CTRL_LOW_REG_DVAL))
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MV_REG_WRITE_ASM(r1, r2, SDRAM_TIMING_CTRL_LOW_REG)
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/* Write SDRAM timing High register */
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GPR_LOAD(r1, MV_32BIT_LE(SDRAM_TIMING_CTRL_HIGH_REG_DVAL))
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MV_REG_WRITE_ASM(r1, r2, SDRAM_TIMING_CTRL_HIGH_REG)
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/* Write SDRAM mode register */
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GPR_LOAD(r1, MV_32BIT_LE(SDRAM_MODE_REG_DV))
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MV_REG_WRITE_ASM(r1, r2, SDRAM_MODE_REG)
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/* Write SDRAM Extended mode register */
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GPR_LOAD(r1, MV_32BIT_LE(SDRAM_EXTENDED_MODE_REG_DV))
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MV_REG_WRITE_ASM(r1, r2, SDRAM_EXTENDED_MODE_REG)
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/* Config DDR2 On Die Termination (ODT) registers */
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GPR_LOAD(r1, MV_32BIT_LE(DDR2_SDRAM_ODT_CTRL_LOW_REG_DV))
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MV_REG_WRITE_ASM(r1, r2, DDR2_SDRAM_ODT_CTRL_LOW_REG)
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/* Write SDRAM DDR2 ODT control high register */
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GPR_LOAD(r1, MV_32BIT_LE(DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV))
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MV_REG_WRITE_ASM(r1, r2, DDR2_SDRAM_ODT_CTRL_HIGH_REG)
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/* Write SDRAM DDR2 Dunit ODT control register */
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GPR_LOAD(r1, MV_32BIT_LE(DDR2_DUNIT_ODT_CTRL_REG_DV))
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MV_REG_WRITE_ASM(r1, r2, DDR2_DUNIT_ODT_CONTROL_REG)
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mov r3, #MV_32BIT_LE(DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV)
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mov r4, #MV_32BIT_LE(DDR2_DATA_PAD_STRENGTH_TYPICAL_DV)
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b next
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next:
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/* DDR SDRAM Initialization Control Register. Init enable */
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mov r1, #MV_32BIT_LE(DSICR_INIT_EN)
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MV_REG_WRITE_ASM (r1, r2, DDR_SDRAM_INIT_CTRL_REG)
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#ifdef NAND_DEBUG
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/* GPP initialization */
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mov r2, #0xd0000000
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orr r2, r2, #0x10000
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mov r1, #0x2000000
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MV_REG_WRITE_ASM(r1, r2, 0x100)
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#endif
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ddrInitLoop:
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MV_REG_READ_ASM (r1, r2, DDR_SDRAM_INIT_CTRL_REG)
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cmp r1, #0
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bne ddrInitLoop
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/* Load back SDRAM controller base address 0xd0001000 */
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mov r2, #0xd0000000
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orr r2, r2, #0x1000
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/* Open SDRAM bank 0 size register */
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GPR_LOAD(r1, MV_32BIT_LE(SDRAM_SIZE_REG_DV))
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MV_REG_WRITE_ASM(r1, r2, SDRAM_SIZE_REG(0,0))
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/* Close SDRAM bank 1,2,3 */
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MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(0,1))
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MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(0,2))
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MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(0,3))
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/* Prepare the address where to find the nandBoot function pointer */
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mov lr, #BOOTER_BASE
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add lr, lr, #0x20
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#ifdef DEBUG
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/* GPP initialization */
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mov r2, #0xd0000000
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orr r2, r2, #0x10000
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mov r1, #0x2000000
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MV_REG_WRITE_ASM(r1, r2, 0x100)
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#endif
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/* init */
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mov r2, #0x1 /* start with page 1 */
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mov r3, #BOOTER_BASE /* start of DRAM buffer */
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GPR_LOAD(r5, NAND_FLASH_BASE)
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cp_page_loop:
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mov r0, #0
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mov r6, #CMD_READ
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mov r7, #CMD_START_READ
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mov r9, #CMD_RESET
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mov r4, #PAGE_SIZE /* Byte counter */
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startRead:
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/* issue reset command */
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strb r9, [r5, #NAND_CMD_PORT]
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mov r9, #0x1000000
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loop_delay1:
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sub r9, r9, #1
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cmp r9, #0
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bne loop_delay1
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/* issue read command */
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strb r6, [r5, #NAND_CMD_PORT]
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/* issue address */
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strb r0, [r5, #NAND_ADDR_PORT]
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strb r0, [r5, #NAND_ADDR_PORT]
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strb r2, [r5, #NAND_ADDR_PORT] /* page address */
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strb r0, [r5, #NAND_ADDR_PORT]
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strb r0, [r5, #NAND_ADDR_PORT]
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strb r7, [r5, #NAND_CMD_PORT]
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#ifdef NAND_DEBUG
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/* GPP initialization */
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mov r6, #0xd0000000
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orr r6, r6, #0x10000
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mov r1, #0x3000000
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MV_REG_WRITE_ASM(r1, r6, 0x100)
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#endif
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/* Delay of at least 25uSec (NAND flash tR) */
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mov r9, #0x1000000
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loop_delay3:
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sub r9, r9, #1
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cmp r9, #0
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bne loop_delay3
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#ifdef NAND_DEBUG
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/* GPP initialization */
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mov r6, #0xd0000000
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orr r6, r6, #0x10000
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mov r1, #0x4000000
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MV_REG_WRITE_ASM(r1, r6, 0x100)
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#endif
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/* now perform reading */
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mov r0, r5
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copy_loop1:
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sub r4, r4, #16 /* 4 dwords * 4 bytes */
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ldmia r0!, {r6-r9}
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stmia r3!, {r6-r9}
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cmp r4, #0 /* check if we have read a full Page */
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bne copy_loop1
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nextPage:
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add r2, r2, #1 /* increment page number */
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cmp r2, #BOOTER_PAGE_NUM
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bne cp_page_loop
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#ifdef NAND_DEBUG
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/* GPP initialization */
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mov r2, #0xd0000000
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orr r2, r2, #0x10000
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mov r1, #0x5000000
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MV_REG_WRITE_ASM(r1, r2, 0x100)
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#endif
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/* Set up the stack */
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stack_setup:
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mov r0, #BOOTER_BASE
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sub sp, r0, #12 /* leave 3 words for abort-stack */
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/* jump to new code */
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mov pc, lr
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.align 10
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/* This is known to be address (BOOTER_BASE + 2 * PAGE_SIZE) */
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_nandBootPtr:
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.word nand_boot
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#else /* MV_BOOTROM */
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.globl nbootStart
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nbootStart:
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/* Enable I-Cache */
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mrc p15, 0, r1, c1, c0, 0
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orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */
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/* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */
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mcr p15, 0, r1, c1, c0, 0
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/* Set up the stack */
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mov r0, #BOOTER_BASE
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sub sp, r0, #12 /* leave 3 words for abort-stack */
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/* jump to new code */
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ldr lr, =nandBoot
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mov pc, lr
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#endif /* !defined(MV_BOOTROM) */
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