179 lines
5.2 KiB
ArmAsm
179 lines
5.2 KiB
ArmAsm
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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*******************************************************************************/
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#define MV_ASMLANGUAGE
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#include "mvOsAsm.h"
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#include <config.h>
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#include <version.h>
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#include "mvBoardEnvSpec.h"
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#include "mvCtrlEnvSpec.h"
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#include "mvCpuIfConfig.h"
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#include "pci/mvPciRegs.h"
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#include "pex/mvPexRegs.h"
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#include "ddr2/mvDramIfRegs.h"
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#include "mvCtrlEnvAsm.h"
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#include "mvAhbToMbusRegs.h"
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#if defined(MV_INC_BOARD_SPI_FLASH)
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#include "spi/mvSpiSpec.h"
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#endif
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.globl lowlevel_init
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/************************************************/
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/* lowlevel_init *
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/************************************************/
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lowlevel_init:
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mov r2, lr
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#if defined(MV78200)
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mov r0, #0
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mrc p15, 1, r0, c15, c1, 0
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/* Check if we are CPU0 or CPU1 */
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and r0, r0, #0x4000
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cmp r0, #0x4000
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bne cpu0_reg_offset
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b done_cpu1
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#endif
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/* change CPU0 reg base to 0xf1000000 */
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cpu0_reg_offset:
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ldr r4, =CFG_MV_REGS
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MV_DV_REG_WRITE_ASM(r4, r1, (AHB_TO_MBUS_WIN_INTEREG_REG(0)))
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ldr r4, =CFG_MV_REGS
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MV_REG_WRITE_ASM (r4, r1, (AHB_TO_MBUS_WIN_INTEREG_REG(1)))
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#if defined(MV_INC_BOARD_SPI_FLASH)
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/* configure the Prescale of SPI clk Tclk = 200MHz */
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MV_REG_READ_ASM (r6, r1, MV_SPI_IF_CONFIG_REG)
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and r6, r6, #~MV_SPI_CLK_PRESCALE_MASK
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orr r6, r6, #0x15
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orr r6, r6, #0x4000
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MV_REG_WRITE_ASM (r6, r1, MV_SPI_IF_CONFIG_REG)
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#endif
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#if 0
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/* Set CPU_2_AHB_TICK_DRV and CCR_CPU_2_AHB_TICK_SMPL tiks */
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MV_REG_READ_ASM (r6, r1, CPU_RESET_SAMPLE_L_REG)
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and r6, r6 , #MSAR_SYSCLK2CPU_MASK0
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mov r6, r6, LSR #MSAR_SYSCLK2CPU_OFFS0
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ldr r4, = ((1 << CCR_CPU_2_AHB_TICK_SMPL_OFFS) | (0 << CCR_CPU_2_AHB_TICK_DRV_OFFS))
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cmp r6, #0x2
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beq set_cpu_config
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ldr r4, = ((1 << CCR_CPU_2_AHB_TICK_SMPL_OFFS) | (1 << CCR_CPU_2_AHB_TICK_DRV_OFFS))
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cmp r6, #0x4
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beq set_cpu_config
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ldr r4, = ((1 << CCR_CPU_2_AHB_TICK_SMPL_OFFS) | (2 << CCR_CPU_2_AHB_TICK_DRV_OFFS))
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cmp r6, #0x6
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beq set_cpu_config
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ldr r4, =0
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set_cpu_config:
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/* Don't change R4 !!! use for Second CPU as well */
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MV_REG_READ_ASM (r6, r1, CPU_CONFIG_REG(MASTER_CPU))
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orr r6, r6, r4
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MV_REG_WRITE_ASM (r6, r1, CPU_CONFIG_REG(MASTER_CPU))
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MV_REG_READ_ASM (r6, r1, CPU_RESET_SAMPLE_L_REG)
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and r6, r6 , #MSAR_SYSCLK2CPU_MASK1
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mov r6, r6, LSR #MSAR_SYSCLK2CPU_OFFS1
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ldr r4, = ((1 << CCR_CPU_2_AHB_TICK_SMPL_OFFS) | (0 << CCR_CPU_2_AHB_TICK_DRV_OFFS))
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cmp r6, #0x2
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beq set_cpu1_config
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ldr r4, = ((1 << CCR_CPU_2_AHB_TICK_SMPL_OFFS) | (1 << CCR_CPU_2_AHB_TICK_DRV_OFFS))
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cmp r6, #0x4
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beq set_cpu1_config
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ldr r4, = ((1 << CCR_CPU_2_AHB_TICK_SMPL_OFFS) | (2 << CCR_CPU_2_AHB_TICK_DRV_OFFS))
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cmp r6, #0x6
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beq set_cpu1_config
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ldr r4, =0
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set_cpu1_config:
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MV_REG_READ_ASM (r6, r1, CPU_CONFIG_REG(SLAVE_CPU))
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orr r6, r6, r4
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MV_REG_WRITE_ASM (r6, r1, CPU_CONFIG_REG(SLAVE_CPU))
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#endif
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/* init MPP */
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ldr r6, =DB_78XX0_MPP0_7
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MV_REG_WRITE_ASM (r6, r1, 0x10000)
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ldr r6, =DB_78XX0_MPP8_15
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/* Clear SATA_ACT for load indication */
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and r6, r6 ,#0xffffff
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MV_REG_WRITE_ASM (r6, r1, 0x10004)
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#if defined(DB_MV78XX0) && defined(MV_NAND_BOOT)
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ldr r6, =DB_78XX0_MPP16_23_NAND
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#else
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ldr r6, =DB_78XX0_MPP16_23
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MV_REG_WRITE_ASM (r6, r1, 0x10008)
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#endif
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/* init GPP , Out enable */
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MV_REG_READ_ASM(r6, r1, 0x10104);
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bic r6, #(0x3 << 14)
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MV_REG_WRITE_ASM(r6, r1, 0x10104);
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ldr r6, =(0x1 << 15)
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MV_REG_WRITE_ASM(r6, r1, 0x10120);
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ldr r6, =(0x1 << 14)
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MV_REG_WRITE_ASM(r6, r1, 0x10124);
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#if defined(RD_MV78XX0_AMC)
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/* init MPP */
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ldr r6, =RD_AMC_MPP0_7
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MV_REG_WRITE_ASM (r6, r1, 0x10000)
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ldr r6, =RD_AMC_MPP8_15
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MV_REG_WRITE_ASM (r6, r1, 0x10004)
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ldr r6, =RD_AMC_MPP16_23
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MV_REG_WRITE_ASM (r6, r1, 0x10008)
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/* init GPP , Out enable */
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#endif
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#if defined(RD_MV78XX0_MASA)
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/* init MPP */
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ldr r6, =RD_MASA_MPP0_7
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MV_REG_WRITE_ASM (r6, r1, 0x10000)
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ldr r6, =RD_MASA_MPP8_15
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MV_REG_WRITE_ASM (r6, r1, 0x10004)
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ldr r6, =RD_MASA_MPP16_23
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MV_REG_WRITE_ASM (r6, r1, 0x10008)
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/* init GPP , Out enable, blink */
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ldr r6, = (1 << RD_MASA_LED_GPP_PIN(0));
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MV_REG_WRITE_ASM(r6, r1, 0x10108);
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MV_REG_WRITE_ASM(r6, r1, 0x10128);
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MV_REG_WRITE_ASM(r6, r1, 0x10124);
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#endif
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#if defined(MV_STATIC_DRAM_ON_BOARD)
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bl _mvDramIfStaticInit
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#else
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bl _mvDramIfBasicInit
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/* SATA LEDs */
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ldr r6, =(0x1 << 14)
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MV_REG_WRITE_ASM(r6, r1, 0x10120);
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ldr r6, =(0x1 << 15)
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MV_REG_WRITE_ASM(r6, r1, 0x10124);
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#endif
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done:
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mov lr, r2
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done_cpu1:
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mov pc, lr
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