863 lines
24 KiB
C
863 lines
24 KiB
C
#if defined(__KERNEL__) && !defined(MV_UBOOT)
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/* include file on kernel */
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#include <linux/version.h>
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#include <linux/if_ether.h>
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#include "BuffaloGpio.h"
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#include "eth-phy/mvEthPhy.h"
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#include "eth-phy/mvEthPhyRegs.h"
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#include "eth/mvEth.h"
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#include "eth/gbe/mvEthGbe.h"
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#include "eth/gbe/mvEthRegs.h"
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#include "BuffaloWol.h"
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#else
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/* include file on u-boot */
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#include "eth-phy/mvEthPhy.h"
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#include "eth-phy/mvEthPhyRegs.h"
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#include "boardEnv/mvBoardEnvLib.h"
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#include "eth/mvEth.h"
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#include "eth/gbe/mvEthGbe.h"
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#include "eth/gbe/mvEthRegs.h"
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#include "BuffaloWol.h"
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#include <net.h>
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#endif
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#if defined(__KERNEL__) && !defined(MV_UBOOT)
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#define DEBUG(fmt, args...) printk(fmt, ##args)
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typedef unsigned char uchar;
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/*
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* Ethernet header
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*/
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typedef struct {
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uchar et_dest[6]; /* Destination node */
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uchar et_src[6]; /* Source node */
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ushort et_protlen; /* Protocol or length */
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uchar et_dsap; /* 802 DSAP */
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uchar et_ssap; /* 802 SSAP */
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uchar et_ctl; /* 802 control */
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uchar et_snap1; /* SNAP */
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uchar et_snap2;
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uchar et_snap3;
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ushort et_prot; /* 802 protocol */
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} Ethernet_t;
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#define ETHER_HDR_SIZE 14 /* Ethernet header size */
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#define E802_HDR_SIZE 22 /* 802 ethernet header size */
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typedef ulong IPaddr_t;
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/*
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* Internet Protocol (IP) header.
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*/
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typedef struct {
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uchar ip_hl_v; /* header length and version */
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uchar ip_tos; /* type of service */
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ushort ip_len; /* total length */
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ushort ip_id; /* identification */
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ushort ip_off; /* fragment offset field */
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uchar ip_ttl; /* time to live */
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uchar ip_p; /* protocol */
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ushort ip_sum; /* checksum */
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IPaddr_t ip_src; /* Source IP address */
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IPaddr_t ip_dst; /* Destination IP address */
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ushort udp_src; /* UDP source port */
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ushort udp_dst; /* UDP destination port */
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ushort udp_len; /* Length of UDP packet */
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ushort udp_xsum; /* Checksum */
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} IP_t;
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#define IP_HDR_SIZE_NO_UDP (sizeof (IP_t) - 8)
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#define IP_HDR_SIZE (sizeof (IP_t))
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#else
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#define DEBUG(fmt, args...) printf(fmt, ##args)
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#endif
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#define FLAG_BUFFALO_WOL_UCAST (0 << 0)
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#define FLAG_BUFFALO_WOL_BCAST (1 << 0)
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#define FLAG_BUFFALO_WITH_UDP_H (0 << 1)
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#define FLAG_BUFFALO_WITHOUT_UDP_H (1 << 1)
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#define FLAG_BUFFALO_DISACTIVE_PACKET (0 << 2)
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#define FLAG_BUFFALO_ACTIVE_PACKET (1 << 2)
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struct bfWolSupportPhyList_st {
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MV_U32 OUI;
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MV_U16 ModelNumber;
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};
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struct bfWolInfo_st{
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char name[32];
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MV_U8 packet_type;
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MV_U16 port_num;
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};
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static const struct bfWolSupportPhyList_st bfWolSupportPhyList[] = {
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{0x005043, 0x29}, /* Marvell, 1318 */
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};
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static const struct bfWolInfo_st bfWolPacketType[] = {
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{"active", (FLAG_BUFFALO_ACTIVE_PACKET | FLAG_BUFFALO_WOL_BCAST), 0x0009}, /* broadcast active packet */
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{"active", (FLAG_BUFFALO_ACTIVE_PACKET), 0x0009}, /* unicast active packet */
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{"wol", (FLAG_BUFFALO_ACTIVE_PACKET | FLAG_BUFFALO_WOL_BCAST), 0x0900}, /* broadcast wol packet */
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{"wol", (FLAG_BUFFALO_ACTIVE_PACKET), 0x0900}, /* unicast wol packet */
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{"wol", (FLAG_BUFFALO_ACTIVE_PACKET | FLAG_BUFFALO_WITHOUT_UDP_H), 0}, /* unicast udp header less wol packet */
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{"wol", (FLAG_BUFFALO_ACTIVE_PACKET | FLAG_BUFFALO_WOL_BCAST | FLAG_BUFFALO_WITHOUT_UDP_H), 0}, /* broadcast udp header less wol packet */
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};
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#define MAX_WOL_PHY_LIST ((sizeof(bfWolSupportPhyList)) / (sizeof(bfWolSupportPhyList[0])))
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#define MAX_WOL_TYPE ((sizeof(bfWolPacketType)) / (sizeof(bfWolPacketType[0])))
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/* used for return buffer of bfGetWolPatternString */
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static char bfWolPatternString[128];
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#if defined(__KERNEL__) && !defined(MV_UBOOT)
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/*******************************************************************************
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* mvEthPhyDisableAN - Disable Phy Auto-Negotiation and set forced Speed and Duplex
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*
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* DESCRIPTION:
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* This function disable AN and set duplex and speed.
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*
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* INPUT:
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* phyAddr - Phy address.
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* speed - port speed. 0 - 10 Mbps, 1-100 Mbps, 2 - 1000 Mbps
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* duplex - port duplex. 0 - Half duplex, 1 - Full duplex
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*
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* OUTPUT:
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* None.
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*
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* RETURN: MV_OK - Success
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* MV_FAIL - Failure
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*
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*******************************************************************************/
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MV_STATUS mvEthPhyDisableAN(MV_U32 phyAddr, int speed, int duplex)
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{
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MV_U16 phyRegData;
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if(mvEthPhyRegRead (phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK)
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return MV_FAIL;
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switch(speed)
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{
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case 0: /* 10 Mbps */
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phyRegData &= ~ETH_PHY_CTRL_SPEED_LSB_MASK;
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phyRegData &= ~ETH_PHY_CTRL_SPEED_MSB_MASK;
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break;
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case 1: /* 100 Mbps */
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phyRegData |= ETH_PHY_CTRL_SPEED_LSB_MASK;
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phyRegData &= ~ETH_PHY_CTRL_SPEED_MSB_MASK;
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break;
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case 2: /* 1000 Mbps */
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phyRegData &= ~ETH_PHY_CTRL_SPEED_LSB_MASK;
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phyRegData |= ETH_PHY_CTRL_SPEED_MSB_MASK;
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break;
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default:
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mvOsOutput("Unexpected speed = %d\n", speed);
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return MV_FAIL;
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}
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switch(duplex)
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{
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case 0: /* half duplex */
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phyRegData &= ~ETH_PHY_CTRL_DUPLEX_MASK;
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break;
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case 1: /* full duplex */
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phyRegData |= ETH_PHY_CTRL_DUPLEX_MASK;
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break;
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default:
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mvOsOutput("Unexpected duplex = %d\n", duplex);
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}
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/* Clear bit 12 to Disable autonegotiation of the PHY */
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phyRegData &= ~ETH_PHY_CTRL_AN_ENABLE_MASK;
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/* Clear bit 9 to DISABLE, Restart autonegotiation of the PHY */
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phyRegData &= ~ETH_PHY_CTRL_AN_RESTART_MASK;
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mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, phyRegData);
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return MV_OK;
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}
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#endif
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/*******************************************************************************
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* bfIsSupportWol
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*
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* DESCRIPTION:
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* Check specified ethPortNum support WOL or not.
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*
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* INPUT:
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* ethPortNum : port No. to check.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* MV_TRUE : Specified eth port suports WOL function.
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* MV_FALSE : Specified eth port doesn't support WOL function.
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*
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*******************************************************************************/
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MV_BOOL
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bfIsSupportWol(MV_U32 ethPortNum)
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{
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MV_U8 i = 0;
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MV_U16 old_page;
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MV_U16 reg;
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MV_U32 OUI = 0;
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MV_U16 ModelNumber = 0;
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mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 22, &old_page);
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 0);
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mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 2, ®);
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OUI |= (MV_U32)(reg << 6);
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mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 3, ®);
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OUI |= ((reg & 0xFC00) >> 10);
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ModelNumber = ((reg & 0x03F0) >> 4);
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, old_page);
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for(i = 0; i < MAX_WOL_PHY_LIST; i++)
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{
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if(bfWolSupportPhyList[i].OUI == OUI && bfWolSupportPhyList[i].ModelNumber == ModelNumber)
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return MV_TRUE;
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}
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return MV_FALSE;
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}
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/*******************************************************************************
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* bfResetEthPhy
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*
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* DESCRIPTION:
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* Do reset eth phy.
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*
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* INPUT:
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* ethPortNum : port No. to to reset.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* None.
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*
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*******************************************************************************/
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void
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bfResetEthPhy(MV_U32 ethPortNum)
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{
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DEBUG("Resetting EthPhy\n");
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mvEthPhyReset(mvBoardPhyAddrGet(ethPortNum), 1000);
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}
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/*******************************************************************************
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* bfControlWolInterrupt
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*
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* DESCRIPTION:
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* Control WOL interrupt status (to Enable / Disable).
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*
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* INPUT:
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* ethPortNum : port No. to control interrupt status.
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* ope : specify operation mode to do.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* None.
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*
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*******************************************************************************/
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void
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bfControlWolInterrupt(MV_U32 ethPortNum, MV_U8 ope)
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{
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MV_U16 reg;
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MV_U16 old_page;
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mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 22, &old_page); /* backup present page information */
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,3); /* change to Page 3 */
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if(ope == FLAG_BUFFALO_WOL_INTERRUPT_ENABLE)
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{
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mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16, ®);
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reg &= ~0x0fff;
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reg |= 0x08AA;
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16, reg); /* change led[0][1] off (force Hi-Z)*/
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mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),18, ®);
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reg |= 0x0880;
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),18, reg); /* change led[2] to intn pin */
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}
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else
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{
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mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16, ®);
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reg &= ~0x0fff;
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reg |= 0x0911;
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 16, reg);
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mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),18, ®);
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reg &= ~0x0880;
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 18, reg);
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}
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/* change to Page 0*/
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x0);
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/*WOL Interrupt Enable*/
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mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),18, ®);
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if(ope == FLAG_BUFFALO_WOL_INTERRUPT_ENABLE)
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reg |= 0x80 ;
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else
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reg &= ~(0x80);
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),18,reg);
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if(ope == FLAG_BUFFALO_WOL_INTERRUPT_ENABLE)
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mvEthPhyDisableAN(mvBoardPhyAddrGet(ethPortNum), 0, 0);
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else
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mvEthPhyRestartAN(mvBoardPhyAddrGet(ethPortNum), 1000);
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, old_page); /* restore previous page */
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}
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/*******************************************************************************
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* bfSetPowerSaveMode
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*
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* DESCRIPTION:
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* Do settings to reduce power consumption during WOL mode.
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*
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* INPUT:
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* ethPortNum : port No. to set to WOL mode.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* None.
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*
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*******************************************************************************/
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void
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bfSetPowerSaveMode(MV_U32 ethPortNum)
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{
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MV_U16 reg;
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/*RGMII BUS treansistor OFF*/
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x2); /* change to Page 2 */
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mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),24, ®);
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reg &= ~(BIT8 | BIT9 | BIT10 | BIT2 | BIT1 | BIT0);
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reg |= BIT6 ;
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),24,reg);
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/*STOP CLK125 OUTPUT */
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mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 16, ®);
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reg |= ( BIT2 | BIT1 | BIT11| BIT12);
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reg &= ~BIT3 ;
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 16, reg);
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/* change to Page 0*/
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 0);
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#if defined(energy_detect)
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/*RGMII STOP for Power Saving */
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mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 16, ®);
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reg |= (BIT2 | BIT8 | BIT9) ;
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 16, reg);
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#endif
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}
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/*******************************************************************************
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* bfSetWolMagicWaitMode
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*
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* DESCRIPTION:
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* Set specified ethernet port to Wake on Lan waiting mode.
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*
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* INPUT:
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* ethPortNum : port No. to set to WOL mode.
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* phyAddr : Phy address.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* None.
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*
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*******************************************************************************/
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MV_BOOL
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bfSetWolMagicWaitMode(MV_U32 ethPortNum)
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{
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MV_U16 reg ;
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unsigned char MacAddr[6];
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if(bfIsSupportWol(ethPortNum) == MV_FALSE)
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return MV_FALSE;
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memset(MacAddr, 0, sizeof(MacAddr));
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mvEthMacAddrGet(ethPortNum, MacAddr);
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/* Set WOL mode */
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,17); /* change to Page 17 */
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,0x5500); /* 0101 0101 0000 0000 */
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/* set wol mac address from env data */
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reg = (MacAddr[4]) | (MacAddr[5] << 8) ;
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),23,reg);
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reg = (MacAddr[2]) | (MacAddr[3] << 8) ;
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),24,reg);
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reg = (MacAddr[0]) | (MacAddr[1] << 8) ;
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),25,reg);
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/*Enable Magic Packet*/
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mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,0x5500);
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bfControlWolInterrupt(ethPortNum, FLAG_BUFFALO_WOL_INTERRUPT_ENABLE);
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bfSetPowerSaveMode(ethPortNum);
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return MV_TRUE;
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}
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/*******************************************************************************
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* bfSetFrameEventWol
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*
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* DESCRIPTION:
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* generate frame pattern used to matching.
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*
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* INPUT:
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* frame : buffer to store generated frame pattern.
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* mask : buffer to stora generated mask pattern.
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* pmacAddr : MAC address to generate frame pattern.
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* bfWPT : flags to generate frame pattern.
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* debug : debug flag.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* None.
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*
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*******************************************************************************/
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static MV_U8
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bfSetFrameEventWol(MV_U8 *frame, MV_U8 *mask, MV_U8 *pMacAddr, const struct bfWolInfo_st *bfWPT, int debug)
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{
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MV_U8 i;
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MV_U8 magic_len = 0;
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MV_U8 frame_match_len = 0;
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Ethernet_t *eth_h = (Ethernet_t *)&frame[0];
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Ethernet_t *eth_h_mask = (Ethernet_t *)&mask[0];
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IP_t *ip_h = (IP_t *)&frame[ETHER_HDR_SIZE];
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IP_t *ip_h_mask = (IP_t *)&mask[ETHER_HDR_SIZE];
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MV_U8 *data = NULL;
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MV_U8 *data_mask = NULL;
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for(i = 0; i < 6; i++)
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{
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if(bfWPT->packet_type & FLAG_BUFFALO_WOL_BCAST)
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eth_h->et_dest[i] = 0xFF;
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else
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eth_h->et_dest[i] = pMacAddr[i];
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memset(&(eth_h_mask->et_dest[i]), 0xFF, sizeof(eth_h_mask->et_dest[i]));
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}
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if(bfWPT->packet_type & FLAG_BUFFALO_WITHOUT_UDP_H)
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{
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data = &frame[ETHER_HDR_SIZE];
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data_mask = &mask[ETHER_HDR_SIZE];
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magic_len = 128 - ETHER_HDR_SIZE;
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frame_match_len = ETHER_HDR_SIZE;
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}
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else
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{
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data = &frame[ETHER_HDR_SIZE + IP_HDR_SIZE];
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data_mask = &mask[ETHER_HDR_SIZE + IP_HDR_SIZE];
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ip_h->udp_dst = htons(bfWPT->port_num);
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memset(&(ip_h_mask->udp_dst), 0xFF, sizeof(ip_h_mask->udp_dst));
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magic_len = 128 - ETHER_HDR_SIZE - IP_HDR_SIZE;
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frame_match_len = ETHER_HDR_SIZE + IP_HDR_SIZE;
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}
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if(magic_len > 6 * 17) magic_len = 6*17;
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frame_match_len += magic_len - 1;
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if(debug) DEBUG("matching len = %d\n", magic_len);
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for(i = 0; i < magic_len ; i ++)
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{
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if((i < 6) && (bfWPT->packet_type & FLAG_BUFFALO_ACTIVE_PACKET))
|
|
data[i] = 0xFF;
|
|
else
|
|
data[i] = pMacAddr[i % 6];
|
|
memset(&(data_mask[i]), -1, sizeof(data_mask[i]));
|
|
}
|
|
|
|
return frame_match_len;
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* bfDumpSramData
|
|
*
|
|
* DESCRIPTION:
|
|
* Set matching frame pattern and mask information to SRAM of EthPhy.
|
|
*
|
|
* INPUT:
|
|
* ethPortNum : No. of target ethernet port.
|
|
* num_frame_pattern: No. of frame pattern to display dump result.
|
|
*
|
|
* OUTPUT:
|
|
* SRAM dump result.
|
|
*
|
|
* RETURN:
|
|
* None.
|
|
*
|
|
*******************************************************************************/
|
|
void
|
|
bfDumpSramData(MV_U32 ethPortNum, MV_U8 num_frame_pattern)
|
|
{
|
|
MV_U8 i;
|
|
MV_U16 old_page;
|
|
MV_U16 reg;
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 22, &old_page); /* backup present page status */
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,17); /* change to Page 17 */
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 16, ®);
|
|
|
|
DEBUG("verifying SRAM value. pattern=%d\n", num_frame_pattern);
|
|
if(reg & (1 << num_frame_pattern))
|
|
DEBUG("patern %d is Enabled\n", num_frame_pattern);
|
|
else
|
|
DEBUG("patern %d is Disabled\n", num_frame_pattern);
|
|
|
|
switch(num_frame_pattern)
|
|
{
|
|
case 0:
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 21, ®);
|
|
break;
|
|
case 1:
|
|
case 2:
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 20, ®);
|
|
break;
|
|
case 3:
|
|
case 4:
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 19, ®);
|
|
break;
|
|
case 5:
|
|
case 6:
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 18, ®);
|
|
break;
|
|
default:
|
|
return ;
|
|
}
|
|
if(num_frame_pattern == 0 || num_frame_pattern == 1 || num_frame_pattern == 3 || num_frame_pattern == 5)
|
|
DEBUG("Matching frame pattern length = %d Bytes\n", (reg & 0x007F) + 1);
|
|
else if(num_frame_pattern == 2 || num_frame_pattern == 4 || num_frame_pattern == 6)
|
|
DEBUG("Matching frame pattern length = %d Bytes\n", (((reg >> 7) & 0x007F) + 1));
|
|
|
|
for(i = 0; i < 128; i++)
|
|
{
|
|
if((i!= 0) && ((i % 0x10) == 0))
|
|
DEBUG("\n0x%02x : ", (i / 0x10) * 0x10);
|
|
else if (((i % 0x10) != 0) && ((i % 0x08) ==0))
|
|
DEBUG(" ");
|
|
else if(i == 0)
|
|
DEBUG("\n0x%02x : ", 0);
|
|
|
|
/* read data from SRAM */
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 26, 0x0800 | i | (num_frame_pattern << 7)); /* 0000 0100 0000 0000 | i */
|
|
|
|
/* read value recorded in SRAM */
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 28, ®);
|
|
if(reg & 0x0100)
|
|
{
|
|
DEBUG("%02x ", reg & 0xFF);
|
|
}
|
|
else
|
|
{
|
|
DEBUG("-- ");
|
|
}
|
|
}
|
|
DEBUG("\n");
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, old_page); /* restore previous page status */
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* bfWriteFramePaternToSram
|
|
*
|
|
* DESCRIPTION:
|
|
* Set matching frame pattern and mask information to SRAM of EthPhy.
|
|
*
|
|
* INPUT:
|
|
* ethPortNum : No. of target ethernet port.
|
|
* frame : 128 byte frame pattern
|
|
* mask : 128 byte mask information. which frame byte is used to matching.
|
|
* num_frame_pattern: No. of frame pattern to set frame pattern.
|
|
*
|
|
* OUTPUT:
|
|
* None.
|
|
*
|
|
* RETURN:
|
|
* None.
|
|
*
|
|
*******************************************************************************/
|
|
static void
|
|
bfWriteFramePaternToSram(MV_U32 ethPortNum, MV_U8 *frame, MV_U8 *mask, MV_U8 num_frame_pattern)
|
|
{
|
|
MV_U16 i;
|
|
MV_U16 reg;
|
|
MV_U16 old_page;
|
|
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 22, &old_page);
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 17);
|
|
|
|
for(i = 0; i < 128; i++)
|
|
{
|
|
/* set value to 17.27 */
|
|
reg = ((mask[i] > 0)? 1:0) << 8 | frame[i];
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 27, reg);
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 26, 0x0400 | i | (num_frame_pattern << 7)); /* 0000 0100 0000 0000 | i */
|
|
}
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, old_page);
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* bfWriteWolFrameMatchingLen
|
|
*
|
|
* DESCRIPTION:
|
|
* Set wol frame matching length to 17.18, 17.19, 17.20 or 17.21
|
|
*
|
|
* INPUT:
|
|
* ethPortNum : No. of target ethernet port.
|
|
* num_frame_patern : No. of frame patern to set matching length.
|
|
* matching_len : matching length to set.
|
|
*
|
|
* OUTPUT:
|
|
* None.
|
|
*
|
|
* RETURN:
|
|
* None.
|
|
*
|
|
*******************************************************************************/
|
|
void
|
|
bfWriteWolFrameMatchingLen(MV_U32 ethPortNum, MV_U8 num_frame_pattern, MV_U8 matching_len)
|
|
{
|
|
MV_U16 reg;
|
|
MV_U16 old_page;
|
|
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 22, &old_page);
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 17);
|
|
|
|
switch(num_frame_pattern)
|
|
{
|
|
case 0:
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 21, matching_len);
|
|
break;
|
|
case 1:
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 20, ®);
|
|
reg &= ~(0x007F);
|
|
reg |= matching_len;
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 20, reg);
|
|
break;
|
|
case 2:
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 20, ®);
|
|
reg &= ~(0x3F80);
|
|
reg |= (matching_len << 7);
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 20, reg);
|
|
break;
|
|
case 3:
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 19, ®);
|
|
reg &= ~(0x007F);
|
|
reg |= matching_len;
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 19, reg);
|
|
break;
|
|
case 4:
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 19, ®);
|
|
reg &= ~(0x3F80);
|
|
reg |= (matching_len << 7);
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 19, reg);
|
|
break;
|
|
case 5:
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 18, ®);
|
|
reg &= ~(0x007F);
|
|
reg |= matching_len;
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 18, reg);
|
|
break;
|
|
case 6:
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 18, ®);
|
|
reg &= ~(0x3F80);
|
|
reg |= (matching_len << 7);
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 18, reg);
|
|
break;
|
|
}
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, old_page);
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* bfSetWolFrameWaitMode
|
|
*
|
|
* DESCRIPTION:
|
|
* Set wol frame wait mode.
|
|
*
|
|
* INPUT:
|
|
* ethPortNum : No. of target ethernet port.
|
|
* pMacAddr : MAC address to set.
|
|
* debug : debug flag(for verbose output)
|
|
*
|
|
* OUTPUT:
|
|
* None.
|
|
*
|
|
* RETURN:
|
|
* MV_TRUE : success to set wol mode.
|
|
* MV_FALSE : failed to set wol mode.
|
|
*
|
|
*******************************************************************************/
|
|
MV_BOOL
|
|
bfSetWolFrameWaitMode(MV_U32 ethPortNum, int debug)
|
|
{
|
|
MV_U16 old_page;
|
|
MV_U16 reg;
|
|
MV_U16 enabling_pattern = 0;
|
|
MV_U8 i;
|
|
MV_U8 frame[128];
|
|
MV_U8 mask[128];
|
|
MV_U8 matching_len = 128;
|
|
unsigned char MacAddr[6];
|
|
|
|
if(bfIsSupportWol(ethPortNum) == MV_FALSE)
|
|
return MV_FALSE;
|
|
|
|
#if defined(__KERNEL__) && !defined(MV_UBOOT)
|
|
DEBUG("Setting WOL ... ");
|
|
if(!bfGppInRegBitTest(BIT_PWRAUTO_SW))
|
|
{
|
|
DEBUG("Switch status is not AUTO\n");
|
|
return MV_FALSE;
|
|
}
|
|
#endif
|
|
|
|
memset(MacAddr, 0, sizeof(MacAddr));
|
|
mvEthMacAddrGet(ethPortNum, MacAddr);
|
|
|
|
bfControlWolInterrupt(ethPortNum, FLAG_BUFFALO_WOL_INTERRUPT_DISABLE);
|
|
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 22, &old_page); /* backup present page status */
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 17); /* change to Page 17 */
|
|
/* Disabling WOL Match Enable flags */
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 16, ®);
|
|
reg &= ~(0xC07F);
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 16, reg);
|
|
|
|
for(i = 0; i < MAX_WOL_TYPE; i++)
|
|
{
|
|
memset(frame, 0, sizeof(frame));
|
|
memset(mask, 0, sizeof(mask));
|
|
matching_len = bfSetFrameEventWol(frame, mask, MacAddr, &(bfWolPacketType[i]), debug);
|
|
bfWriteFramePaternToSram(ethPortNum, frame, mask, i);
|
|
bfWriteWolFrameMatchingLen(ethPortNum, i, matching_len);
|
|
enabling_pattern |= (1 << i);
|
|
}
|
|
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 16, enabling_pattern); /* 1001 0000 0000 0011 */
|
|
|
|
if(debug)
|
|
for (i = 0; i < 7; i++)
|
|
bfDumpSramData(ethPortNum, i);
|
|
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 16, 0x9000 | enabling_pattern); /* 1001 0000 0000 0011 */
|
|
|
|
bfControlWolInterrupt(ethPortNum, FLAG_BUFFALO_WOL_INTERRUPT_ENABLE);
|
|
bfSetPowerSaveMode(ethPortNum);
|
|
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, old_page); /* restore previous page status */
|
|
#if defined(__KERNEL__) && !defined(MV_UBOOT)
|
|
DEBUG("Success\n");
|
|
#endif
|
|
return MV_TRUE;
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* bfGetWolPatternString
|
|
*
|
|
* DESCRIPTION:
|
|
* generate string to send kernel from the information of which frame pattern matched.
|
|
*
|
|
* INPUT:
|
|
* wol_stat : register value of 17.17
|
|
*
|
|
* OUTPUT:
|
|
* None.
|
|
*
|
|
* RETURN:
|
|
* pointer to string.
|
|
*
|
|
*******************************************************************************/
|
|
char *bfGetWolPatternString(MV_U16 wol_stat)
|
|
{
|
|
MV_U8 i;
|
|
|
|
memset(bfWolPatternString, 0, sizeof(bfWolPatternString));
|
|
for(i = 0; i < MAX_WOL_TYPE; i++)
|
|
{
|
|
if(wol_stat & (1 << i) && (strstr(bfWolPatternString, bfWolPacketType[i].name) == 0)) {
|
|
if(strlen(bfWolPatternString) == 0)
|
|
sprintf(bfWolPatternString, "%s", bfWolPacketType[i].name);
|
|
else
|
|
sprintf(bfWolPatternString, ",%s", bfWolPacketType[i].name);
|
|
}
|
|
}
|
|
|
|
return (bfWolPatternString[0])? bfWolPatternString : NULL;
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* bfGetWolInterruptStatus
|
|
*
|
|
* DESCRIPTION:
|
|
* Get interrupt status
|
|
*
|
|
* INPUT:
|
|
* ethPortNum : No. of target ethernet port.
|
|
*
|
|
* OUTPUT:
|
|
* None.
|
|
*
|
|
* RETURN:
|
|
* register value of 17.17(which frame pattern received)
|
|
*
|
|
*******************************************************************************/
|
|
MV_U16 bfGetWolInterruptStatus(MV_U32 ethPortNum, int debug)
|
|
{
|
|
MV_U16 old_page;
|
|
MV_U16 reg;
|
|
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 22, &old_page); /* backup present page status */
|
|
|
|
if(debug)
|
|
{
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 17);
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 17, ®);
|
|
DEBUG("WOL status(17.17)=0x%04x\n", reg);
|
|
}
|
|
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 0);
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 19, ®);
|
|
if(debug)
|
|
{
|
|
DEBUG("WOL status(0.19)=0x%04x\n", reg);
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 23, ®);
|
|
DEBUG("Global Interrupt Status(0.23)=0x%04x\n", reg);
|
|
}
|
|
|
|
if(reg & 0x0080)
|
|
{
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 17);
|
|
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 17, ®);
|
|
}
|
|
else
|
|
{
|
|
reg = 0;
|
|
}
|
|
|
|
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, old_page); /* restore previous page status */
|
|
|
|
return (reg & 0x003F);
|
|
}
|
|
|
|
|