179 lines
9.2 KiB
C
179 lines
9.2 KiB
C
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __INCmvPMFlashSpecH
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#define __INCmvPMFlashSpecH
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#include "mvMFlashSpec.h"
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/* default values for the timing registers */
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#define MV_PMFLASH_T1 0x7 /* Read Access Time T1 <20> sunol2 default */
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#define MV_PMFLASH_T2 0x7 /* Read Access Time T2 <20> sunol2 default */
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#define MV_PMFLASH_T7 0x29 /* Divider Number for T7 <20> sunol2 default */
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#define MV_PMFLASH_PCLK_OUT 0x0 /* Hold Time between reference clock and PCLK */
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#define MV_PMFLASH_SLEW_0_1 0x2 /* slew rate for PCLK_OUT bits 0-1 */
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#define MV_PMFLASH_SLEW_2_3 0x3 /* slew rate for PCLK_OUT bits 2-3 */
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/* Programming allignment mask */
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#define MV_PMFLASH_PROG_WORDS_PER_CHUNK (MV_MFLASH_PROG_CHUNK_SIZE / 2)
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/* IRead Allignmet definitions */
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#define MV_PMFLASH_IREAD_ALIGN_MASK 0x0007 /* IREAD should be alligned to 8bytes */
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#define MV_PMFLASH_IREAD_CHUNK_SIZE (MV_PMFLASH_IREAD_ALIGN_MASK + 1)
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/* wrod count for the Indirect read commands (IREAD and READ ID) */
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#define MV_PMFLASH_IREAD_16BIT_COUNT 0x4 /* 8 bytes per IREAD command */
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#define MV_PMFLASH_READ_ID_16BIT_COUNT 0x3 /* 6 bytes = 4 manf ID + 2 Dev ID */
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/* MFlash command opcodes */
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#define MV_PMFLASH_OPCD_PROGRAM 0x02
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#define MV_PMFLASH_OPCD_PRG_CMP 0x07
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#define MV_PMFLASH_OPCD_IPROGRAM 0x82
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#define MV_PMFLASH_OPCD_IPRG_CMP 0x87
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#define MV_PMFLASH_OPCD_PAGE_ERASE 0x52
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#define MV_PMFLASH_OPCD_IPAGE_ERASE 0xD2
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#define MV_PMFLASH_OPCD_CHIP_ERASE 0xE2
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#define MV_PMFLASH_OPCD_MAIN_ERASE 0x62
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#define MV_PMFLASH_OPCD_RDSR 0x05
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#define MV_PMFLASH_OPCD_IREAD 0x83
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#define MV_PMFLASH_OPCD_SET_CFG1 0xB0
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#define MV_PMFLASH_OPCD_SET_CFG2 0xB1
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#define MV_PMFLASH_OPCD_SET_CFG3 0xB2
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#define MV_PMFLASH_OPCD_SET_CFG4 0xB3
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#define MV_PMFLASH_OPCD_READ_CFG1 0xB4
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#define MV_PMFLASH_OPCD_READ_CFG2 0xB5
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#define MV_PMFLASH_OPCD_READ_CFG3 0xB6
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#define MV_PMFLASH_OPCD_READ_CFG4 0xB7
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#define MV_PMFLASH_OPCD_SHUTDOWN 0xA4
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#define MV_PMFLASH_OPCD_SET_SLEW 0xA5
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#define MV_PMFLASH_OPCD_READ_ID 0x15
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/* Marvell Flash Device Controller Registers */
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#define MV_PMFLASH_CTRLR_OFST 0x10500
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#define MV_PMFLASH_IF_CTRL_REG (MV_PMFLASH_CTRLR_OFST + 0x00)
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#define MV_PMFLASH_IF_CFG_REG (MV_PMFLASH_CTRLR_OFST + 0x04)
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#define MV_PMFLASH_ADDR_LOW_REG (MV_PMFLASH_CTRLR_OFST + 0x08)
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#define MV_PMFLASH_ADDR_HI_REG (MV_PMFLASH_CTRLR_OFST + 0x0c)
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#define MV_PMFLASH_CMD_OPCODE_REG (MV_PMFLASH_CTRLR_OFST + 0x10)
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#define MV_PMFLASH_IF_STATUS_REG (MV_PMFLASH_CTRLR_OFST + 0x14)
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#define MV_PMFLASH_STATUS_REG (MV_PMFLASH_CTRLR_OFST + 0x18)
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#define MV_PMFLASH_DATA_REG (MV_PMFLASH_CTRLR_OFST + 0x20)
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/* Flash Interface configuration */
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#define MV_PMFLASH_SERIAL_MODE_OFFSET 0 /* bit 0 */
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#define MV_PMFLASH_RESET_OFFSET 4 /* bit 4 */
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#define MV_PMFLASH_IF_RESET_OFFSET 5 /* bit 5 */
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#define MV_PMFLASH_WP_PROTECT_OFFSET 6 /* bit 6 */
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#define MV_PMFLASH_EXT_FLASH_OFFSET 12 /* bit 12 */
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#define MV_PMFLASH_EXT_PROGRAMMER_OFFSET 13 /* bit 13 */
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#define MV_PMFLASH_SERIAL_MODE_MASK (0x1 << MV_PMFLASH_SERIAL_MODE_OFFSET)
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#define MV_PMFLASH_RESET_MASK (0x1 << MV_PMFLASH_RESET_OFFSET)
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#define MV_PMFLASH_IF_RESET_MASK (0x1 << MV_PMFLASH_IF_RESET_OFFSET)
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#define MV_PMFLASH_WP_PROTECT_MASK (0x1 << MV_PMFLASH_WP_PROTECT_OFFSET)
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#define MV_PMFLASH_EXT_FLASH_MASK (0x1 << MV_PMFLASH_EXT_FLASH_OFFSET)
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#define MV_PMFLASH_EXT_PROGRAMMER_MASK (0x1 << MV_PMFLASH_EXT_PROGRAMMER_OFFSET)
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#define MV_PMFLASH_SPI_BUS_MODE_MASK (MV_PMFLASH_SERIAL_MODE_MASK | MV_PMFLASH_EXT_FLASH_MASK | MV_PMFLASH_EXT_PROGRAMMER_MASK)
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#define MV_PMFLASH_SPI_BUS_TO_MFLASH 0x1001
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#define MV_PMFLASH_SPI_BUS_TO_EXT_SFLASH 0x0000
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#define MV_PMFLASH_SPI_BUS_EXT_PROGRAMER 0x2001
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/* Command Opcode Register Masks */
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#define MV_PMFLASH_CMD_OPCD_OFFSET 0 /* bits 0-7 */
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#define MV_PMFLASH_EAD9_8_OFFSET 8 /* bit 8 */
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#define MV_PMFLASH_WR_OPER_STRT_OFFSET 12 /* bit 12 */
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#define MV_PMFLASH_ERASE_STRT_OFFSET 13 /* bit 13 */
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#define MV_PMFLASH_RDSR_SET_OFFSET 14 /* bit 14 */
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#define MV_PMFLASH_INF_READ_STRT_OFFSET 15 /* bit 15 */
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#define MV_PMFLASH_EAD9_8_MASK (0x3 << MV_PMFLASH_EAD9_8_OFFSET)
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#define MV_PMFLASH_CMD_OPCD_MASK (0xFF << MV_PMFLASH_CMD_OPCD_OFFSET)
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#define MV_PMFLASH_WR_OPER_STRT_MASK (0x1 << MV_PMFLASH_WR_OPER_STRT_OFFSET)
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#define MV_PMFLASH_ERASE_STRT_MASK (0x1 << MV_PMFLASH_ERASE_STRT_OFFSET)
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#define MV_PMFLASH_RDSR_SET_MASK (0x1 << MV_PMFLASH_RDSR_SET_OFFSET)
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#define MV_PMFLASH_INF_READ_STRT_MASK (0x1 << MV_PMFLASH_INF_READ_STRT_OFFSET)
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/* Flash Interface Status Register Masks */
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#define MV_PMFLASH_CMD_DONE_OFFSET 0 /* bit 0 */
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#define MV_PMFLASH_CMD_DONE_MASK (0x1 << MV_PMFLASH_CMD_DONE_OFFSET)
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/* Flash Status Register Masks */
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#define MV_PMFLASH_STATUS_OFFSET 0 /* bits 0-7 */
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#define MV_PMFLASH_STAT_WIP_OFFSET 0 /* bit 0 */
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#define MV_PMFLASH_STAT_CMP_OFFSET 6 /* bit 6 */
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#define MV_PMFLASH_STATUS_MASK (0xFF << MV_PMFLASH_STATUS_OFFSET)
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#define MV_PMFLASH_STAT_WIP_MASK (0x1 << MV_PMFLASH_STAT_WIP_OFFSET)
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#define MV_PMFLASH_STAT_CMP_MASK (0x1 << MV_PMFLASH_STAT_CMP_OFFSET)
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/* MFlash CONFIG4 register bit Masks */
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#define MV_PMFLASH_CFG4_PG_SZ_OFFSET 0 /* bit 0 */
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#define MV_PMFLASH_CFG4_WP_OFFSET 7 /* bit 7 */
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#define MV_PMFLASH_CFG4_PG_SZ_MASK (0x1 << MV_PMFLASH_CFG4_PG_SZ_OFFSET)
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#define MV_PMFLASH_CFG4_WP_MASK (0x1 << MV_PMFLASH_CFG4_WP_OFFSET)
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/* MFlash CONFIG2 register bit Masks */
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#define MV_PMFLASH_CFG2_PRFTCH_OFFSET 7 /* bit 7 */
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#define MV_PMFLASH_CFG2_PRFTCH_MASK (0x1 << MV_PMFLASH_CFG2_PRFTCH_OFFSET)
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#endif /* __INCmvPMFlashSpecH */
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