120 lines
6.9 KiB
C
120 lines
6.9 KiB
C
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __INCmvSMFlashSpecH
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#define __INCmvSMFlashSpecH
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/* Constants */
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#define MV_SMFLASH_PAGE_ALLIGN_MASK 0x3F
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#define MV_SMFLASH_PAGE_SIZE (MV_SMFLASH_PAGE_ALLIGN_MASK+1) /* 64 byte */
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#define MV_SMFLASH_WREN_CMND_OPCD 0x06 /* Write Enable */
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#define MV_SMFLASH_WRDI_CMND_OPCD 0x04 /* Write Disable */
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#define MV_SMFLASH_RDSR_CMND_OPCD 0x05 /* Read Status Register */
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#define MV_SMFLASH_READ_CMND_OPCD 0x03 /* Sequential Read */
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#define MV_SMFLASH_PRGRM_CMND_OPCD 0x02 /* Page Program */
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#define MV_SMFLASH_PRGRM_CMP_CMND_OPCD 0x07 /* Page Program and compare */
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#define MV_SMFLASH_PAGE_ERASE_CMND_OPCD 0x42 /* Sector Erase */
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#define MV_SMFLASH_MAIN_ERASE_CMND_OPCD 0x62 /* Main region Erase */
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#define MV_SMFLASH_RDID_CMND_OPCD 0x15 /* Read ID */
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#define MV_SMFLASH_IREAD_CMND_OPCD 0x83 /* Read from Information region */
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#define MV_SMFLASH_IPRGRM_CMND_OPCD 0x82 /* Program the information region */
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#define MV_SMFLASH_IPRGRM_CMP_CMND_OPCD 0x87 /* Program and compare information region */
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#define MV_SMFLASH_SET_CFG_3_CMND_OPCD 0xB2 /* Set configuration register 3 */
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#define MV_SMFLASH_SET_CFG_4_CMND_OPCD 0xB3 /* Set configuration register 4 */
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#define MV_SMFLASH_READ_CFG_3_CMND_OPCD 0xB6 /* Read configuration register 3 */
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#define MV_SMFLASH_READ_CFG_4_CMND_OPCD 0xB7 /* Read configuration register 4 */
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#define MV_SMFLASH_IPG_ERASE_CMND_OPCD 0xC2 /* Erase the information page */
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#define MV_SMFLASH_CHIP_ERASE_CMND_OPCD 0xE2 /* Chip erase (main + information) */
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#define MV_SMFLASH_SHUTDOWN_CMND_OPCD 0xF0 /* Set flash in power down mode */
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#define MV_SMFLASH_PAGE_ERASE_CMND_LEN 4 /* 1B opcode + 3B address */
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#define MV_SMFLASH_PRGRM_CMND_LEN 4 /* 1B opcode + 3B address */
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#define MV_SMFLASH_PRGRM_CMP_CMND_LEN 4 /* 1B opcode + 3B address */
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#define MV_SMFLASH_IPRGRM_CMND_LEN 4 /* 1B opcode + 3B address */
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#define MV_SMFLASH_IPRGRM_CMP_CMND_LEN 4 /* 1B opcode + 3B address */
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#define MV_SMFLASH_READ_CMND_LEN 4 /* 1B opcode + 3B address */
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#define MV_SMFLASH_IREAD_CMND_LEN 4 /* 1B opcode + 3B address */
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#define MV_SMFLASH_RDID_CMND_LEN 1 /* 1B opcode */
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#define MV_SMFLASH_RDID_RPLY_LEN 6 /* 4B manuf ID + 2B device ID */
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/* Status Register Bit Masks */
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#define MV_SMFLASH_STATUS_REG_WIP_OFFSET 0 /* bit 0 - Write in Progress */
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#define MV_SMFLASH_STATUS_REG_WEL_OFFSET 1 /* bit 1 - Write enable Latch */
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#define MV_SMFLASH_STATUS_REG_CMP_OFFSET 6 /* bit 6 - Compare status */
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#define MV_SMFLASH_STATUS_REG_WP_OFFSET 7 /* bit 7 - Write protect status */
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#define MV_SMFLASH_STATUS_REG_WIP_MASK (0x1 << MV_SMFLASH_STATUS_REG_WIP_OFFSET)
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#define MV_SMFLASH_STATUS_REG_WEL_MASK (0x1 << MV_SMFLASH_STATUS_REG_WEL_OFFSET)
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#define MV_SMFLASH_STATUS_REG_CMP_MASK (0x1 << MV_SMFLASH_STATUS_REG_CMP_OFFSET)
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#define MV_SMFLASH_STATUS_REG_WP_MASK (0x1 << MV_SMFLASH_STATUS_REG_WP_OFFSET)
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/* Serial Interface Configuration 4 Masks */
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#define MV_SMFLASH_SRL_CFG4_PG_SIZE_OFFSET 0 /* bit 0 - Page size */
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#define MV_SMFLASH_SRL_CFG4_WP_OFFSET 7 /* bit 7 - Write protection */
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#define MV_SMFLASH_SRL_CFG4_PG_SIZE_MASK (0x1 << MV_SMFLASH_SRL_CFG4_PG_SIZE_OFFSET)
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#define MV_SMFLASH_SRL_CFG4_WP_MASK (0x1 << MV_SMFLASH_SRL_CFG4_WP_OFFSET)
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#endif /* __INCmvSMFlashSpecH */
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