Compare commits

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9 Commits

  1. 1
      AUTHORS
  2. 340
      COPYING
  3. 6
      Makefile
  4. 11
      README
  5. 137
      blmc.c
  6. 17
      blmc.h
  7. BIN
      eagle/blmc-v2-bot.png
  8. BIN
      eagle/blmc-v2-sch.png
  9. BIN
      eagle/blmc-v2-top.png
  10. BIN
      eagle/blmc.brd
  11. BIN
      eagle/blmc.sch
  12. 10
      eeprom.c
  13. 9
      eeprom.h
  14. 156
      i2c-slave.c
  15. 65
      main.c
  16. 19
      main.h

1
AUTHORS

@ -0,0 +1 @@
Olaf Rempel <razzor AT kopf MINUS tisch DOT de>

340
COPYING

@ -0,0 +1,340 @@
GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
The licenses for most software are designed to take away your
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When we speak of free software, we are referring to freedom, not
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this
when it starts in an interactive mode:
Gnomovision version 69, Copyright (C) year name of author
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, the commands you use may
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mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your
school, if any, to sign a "copyright disclaimer" for the program, if
necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
`Gnomovision' (which makes passes at compilers) written by James Hacker.
<signature of Ty Coon>, 1 April 1989
Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Library General
Public License instead of this License.

6
Makefile

@ -1,6 +1,6 @@
PRG = bl_test
PRG = blmc
OBJ = blmc.o eeprom.o i2c-slave.o main.o
MCU_TARGET = atmega8
MCU_TARGET = atmega88
OPTIMIZE = -Os
DEFS =
@ -61,4 +61,4 @@ ebin: $(PRG)_eeprom.bin
install: text
# uisp -dprog=avr910 -dserial=/dev/ttyS0 -dspeed=115200 -dpart=M8 --erase --upload if=$(PRG).hex
avrdude -p m8 -c butterfly -b 115200 -P /dev/ttyUSB1 -u -e -V -U flash:w:$(PRG).hex
avrdude -p m88 -c butterfly -b 115200 -u -e -V -U flash:w:$(PRG).hex

11
README

@ -0,0 +1,11 @@
blmc v2
=======
An AVR mega88/168 based brushless motor controller.
- must run with TWIBOOT as bootloader to get own i2c address
- spinup parameters in EEPROM
- extended i2c protocol
TODO:
- remove C1/C3/C6 and do "timed" commutation
- replace C11 with smaller value / remove it

137
blmc.c

@ -31,67 +31,86 @@ static uint8_t next_sense;
void trigger_adc(uint8_t channel)
{
/* Disable Analog Comperator */
ACSR &= ~(1<<ACIE);
/* set channel (Internal reference, 2.56V) */
ADMUX = (1<<REFS1) | (1<<REFS0) | channel;
/* turn on ADC with interrupts, start conversion with 1/32 of F_CPU */
ADCSRA = (1<<ADEN) | (1<<ADSC) | (1<<ADIE) | (1<<ADIF)| (1<<ADPS2) | (1<<ADPS0);
/* Disable Analog Comperator Interrupt */
TIMSK1 &= ~(1<<ICIE1);
/* set channel (external reference, 5V) */
ADMUX = (0<<REFS1) | (0<<REFS0) | channel;
/*
* turn on ADC with interrupts
* start conversion with 1/32 of F_CPU
* 1/250kHz * 25 => 100us conversion time
*/
ADCSRA = (1<<ADEN) | (1<<ADSC) | (1<<ADIE) | (1<<ADIF)| (1<<ADPS2) | (0<<ADPS0);
}
void next_phase(void)
static void next_phase(void)
{
static uint8_t phase;
static uint8_t phase_adc;
/* Disable Analog Comperator */
ACSR &= ~(1<<ACIE);
TCNT1 = 0x00;
TCNT2 = 0x00;
/* Disable Analog Comperator Interrupt */
TIMSK1 &= ~(1<<ICIE1);
switch (phase) {
case 0: PORTD = (PORTD & ~PHASE_L_MASK) | PHASE_B_L;
TCCR1A = (TCCR1A & ~(1<<COM1B1)) | (1<<COM1A1);
TCCR2 &= ~(1<<COM21);
ACSR = (1<<ACIS1);
case 0: /* A: PWM, B: LOW, C: SENSE => disable EN_C, disable PWM_B, enable EN_B */
PORTD &= ~PHASE_C_EN;
TCCR0A &= ~PHASE_B_OC;
PORTD |= PHASE_B_EN;
/* C: falling edge */
TCCR1B &= ~(1<<ICES1);
next_sense = SENSE_C;
break;
case 1: PORTD = (PORTD & ~PHASE_L_MASK) | PHASE_B_L;
TCCR1A &= ~((1<<COM1A1) | (1<<COM1B1));
TCCR2 |= (1<<COM21);
ACSR = (1<<ACIS1) | (1<<ACIS0);
case 1: /* A: SENSE, B: LOW, C: PWM => disable EN_A, enable PWM_C, enable EN_C */
PORTB &= ~PHASE_A_EN;
TCCR2A |= PHASE_C_OC;
PORTD |= PHASE_C_EN;
/* A: rising edge */
TCCR1B |= (1<<ICES1);
next_sense = SENSE_A;
break;
case 2: PORTD = (PORTD & ~PHASE_L_MASK) | PHASE_A_L;
TCCR1A &= ~((1<<COM1A1) | (1<<COM1B1));
TCCR2 |= (1<<COM21);
ACSR = (1<<ACIS1);
case 2: /* A: LOW, B: SENSE, C: PWM => disable EN_B, disable PWM_A, enable EN_A */
PORTD &= ~PHASE_B_EN;
TCCR2A &= ~PHASE_A_OC;
PORTB |= PHASE_A_EN;
/* B: falling edge */
TCCR1B &= ~(1<<ICES1);
next_sense = SENSE_B;
break;
case 3: PORTD = (PORTD & ~PHASE_L_MASK) | PHASE_A_L;
TCCR1A = (TCCR1A & ~(1<<COM1A1)) | (1<<COM1B1);
TCCR2 &= ~(1<<COM21);
ACSR = (1<<ACIS1) | (1<<ACIS0);
case 3: /* A: LOW, B: PWM, C: SENSE => disable EN_C, enable PWM_B, enable EN_B */
PORTD &= ~PHASE_C_EN;
TCCR0A |= PHASE_B_OC;
PORTD |= PHASE_B_EN;
/* C: rising edge */
TCCR1B |= (1<<ICES1);
next_sense = SENSE_C;
break;
case 4: PORTD = (PORTD & ~PHASE_L_MASK) | PHASE_C_L;
TCCR1A = (TCCR1A & ~(1<<COM1A1)) | (1<<COM1B1);
TCCR2 &= ~(1<<COM21);
ACSR = (1<<ACIS1);
case 4: /* A: SENSE, B: PWM, C: LOW => disable EN_A, disable PWM_C, enable EN_C */
PORTB &= ~PHASE_A_EN;
TCCR2A &= ~PHASE_C_OC;
PORTD |= PHASE_C_EN;
/* A: falling edge */
TCCR1B &= ~(1<<ICES1);
next_sense = SENSE_A;
break;
case 5: PORTD = (PORTD & ~PHASE_L_MASK) | PHASE_C_L;
TCCR1A = (TCCR1A & ~(1<<COM1B1)) | (1<<COM1A1);
TCCR2 &= ~(1<<COM21);
ACSR = (1<<ACIS1) | (1<<ACIS0);
case 5: /* A: PWM, B: SENSE, C: LOW => disable EN_B, enable PWM_A, enable EN_A */
PORTD &= ~PHASE_B_EN;
TCCR2A |= PHASE_A_OC;
PORTB |= PHASE_A_EN;
/* B: rising edge */
TCCR1B |= (1<<ICES1);
next_sense = SENSE_B;
break;
}
@ -114,8 +133,10 @@ void next_phase(void)
ADMUX = next_sense;
/* enable Analog Comparator with Interrupts */
if (blmc.flags & FLAG_COM_NORMAL)
ACSR |= (1<<ACIE) | (1<<ACI);
if (blmc.flags & FLAG_COM_NORMAL) {
TIFR1 |= (1<<ICF1);
TIMSK1 |= (1<<ICIE1);
}
}
phase++;
@ -183,19 +204,18 @@ void setpwm(uint8_t pwm)
if (blmc.flags & FLAG_PWM_SPINUP)
pwm = params.spinup_pwm;
/* raise current-limit */
if (blmc.current > params.current_limit)
/* raise current-limit, set flag */
if (blmc.current > params.current_limit) {
blmc.flags |= FLAG_CURRENT_LIMIT;
blmc.pwm_limit++;
/* lower current-limit */
else if (blmc.pwm_limit > 0)
} else if (blmc.pwm_limit > 0) {
blmc.pwm_limit--;
/* set current-limit flag */
if (blmc.pwm_limit)
blmc.flags |= FLAG_CURRENT_LIMIT;
else
} else if (blmc.pwm_limit == 0) {
blmc.flags &= ~FLAG_CURRENT_LIMIT;
}
/* prevent overflow */
if (blmc.pwm_limit > pwm)
@ -208,12 +228,21 @@ void setpwm(uint8_t pwm)
if (pwm > params.pwm_max)
pwm = params.pwm_max;
OCR1A = pwm;
OCR1B = pwm;
OCR2 = pwm;
OCR0B = pwm;
OCR2A = pwm;
OCR2B = pwm;
/* disable PWM signales, enable all drivers -> brake */
if (pwm == 0) {
TCCR0A &= ~PHASE_B_OC;
TCCR2A &= ~(PHASE_A_OC | PHASE_C_OC);
PORTB |= PHASE_A_EN;
PORTD |= (PHASE_B_EN | PHASE_C_EN);
}
}
ISR(ANA_COMP_vect)
ISR(TIMER1_CAPT_vect)
{
next_phase();
}
@ -233,8 +262,10 @@ ISR(ADC_vect)
ADCSRA = 0x00;
/* enable Analog Comparator with Interrupts */
if (blmc.flags & FLAG_COM_NORMAL)
ACSR |= (1<<ACIE) | (1<<ACI);
if (blmc.flags & FLAG_COM_NORMAL) {
TIFR1 |= (1<<ICF1);
TIMSK1 |= (1<<ICIE1);
}
if (channel == SENSE_CURRENT) {
current_tmp += value;

17
blmc.h

@ -3,23 +3,6 @@
#include <avr/io.h>
#define PHASE_A_H (1<<PORTB1)
#define PHASE_B_H (1<<PORTB2)
#define PHASE_C_H (1<<PORTB3)
#define PHASE_H_MASK (PHASE_A_H | PHASE_B_H | PHASE_C_H)
#define PHASE_A_L (1<<PORTD4)
#define PHASE_B_L (1<<PORTD3)
#define PHASE_C_L (1<<PORTD2)
#define PHASE_L_MASK (PHASE_A_L | PHASE_B_L | PHASE_C_L)
#define SENSE_A 0
#define SENSE_B 1
#define SENSE_C 2
#define SENSE_VOLTAGE 3
#define SENSE_CURRENT 6
#define FLAG_RUN_MASK 0x00F
#define FLAG_PWM_SPINUP 0x001
#define FLAG_PWM_NORMAL 0x002

BIN
eagle/blmc-v2-bot.png

After

Width: 755  |  Height: 322  |  Size: 19 KiB

BIN
eagle/blmc-v2-sch.png

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Width: 1482  |  Height: 925  |  Size: 45 KiB

BIN
eagle/blmc-v2-top.png

After

Width: 755  |  Height: 322  |  Size: 19 KiB

BIN
eagle/blmc.brd

BIN
eagle/blmc.sch

10
eeprom.c

@ -16,11 +16,12 @@
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#include <avr/pgmspace.h>
#include <avr/eeprom.h>
#include <util/crc16.h>
#include "eeprom.h"
static const struct ee_param defaults = DEFAULT_PARAMETERS;
static struct ee_param defaults PROGMEM = DEFAULT_PARAMETERS;
struct ee_param params;
struct ee_param params_in_eeprom EEMEM = DEFAULT_PARAMETERS;
@ -48,12 +49,7 @@ uint8_t read_parameters(void)
crc = _crc_ccitt_update(crc, *tmp++);
if (crc != 0x0000) {
i = sizeof(struct ee_param);
uint8_t *src = (uint8_t *)&defaults;
uint8_t *dst = (uint8_t *)&params;
while (i--)
*dst++ = *src++;
memcpy_P(&params, &defaults, sizeof(struct ee_param));
write_parameters();
return 1;
}

9
eeprom.h

@ -22,16 +22,17 @@ struct ee_param {
};
#define DEFAULT_PARAMETERS { \
.spinup_ticks = 1000, \
.spinup_tick = 25, \
.spinup_step = 24, \
.spinup_ticks = 2000, \
.spinup_tick = 24, \
.spinup_step = 4, \
.spinup_wait = 10, \
.spinup_pwm = 0x0f, \
.spinup_pwm = 25, \
.pwm_min = 0x08, \
.pwm_max = 0xff, \
.current_limit = 120, \
.current_max = 0x3ff, \
.voltage_min = 0x000, \
.crc16 = 0xDB76, \
};
uint8_t read_parameters(void);

156
i2c-slave.c

@ -27,67 +27,117 @@
extern struct blmc_ blmc;
extern struct ee_param params;
/* SLA+R */
#define CMD_WAIT 0x00
#define CMD_GET_INFO 0x10
#define CMD_SET_PWM 0x21
#define CMD_GET_STATUS 0x22
#define CMD_SET_PARAM 0x23
#define CMD_GET_PARAM 0x24
#define CMD_BOOT_LOADER 0x2F
#define CMD_READ_VERSION 0x01
#define CMD_READ_MEMORY 0x02
/* internal mappings */
#define CMD_READ_CHIPINFO (0x10 | CMD_READ_MEMORY)
#define CMD_READ_FLASH (0x20 | CMD_READ_MEMORY)
#define CMD_READ_EEPROM (0x30 | CMD_READ_MEMORY)
#define CMD_READ_PARAMETERS (0x40 | CMD_READ_MEMORY) /* only in APP */
const static uint8_t info[16] = "blctrl m8-v1.2";
/* SLA+W */
#define CMD_SWITCH_APPLICATION CMD_READ_VERSION
#define CMD_WRITE_MEMORY CMD_READ_MEMORY
/* internal mappings */
#define CMD_BOOT_BOOTLOADER (0x10 | CMD_SWITCH_APPLICATION) /* only in APP */
#define CMD_BOOT_APPLICATION (0x20 | CMD_SWITCH_APPLICATION)
#define CMD_WRITE_CHIPINFO (0x10 | CMD_WRITE_MEMORY) /* invalid */
#define CMD_WRITE_FLASH (0x20 | CMD_WRITE_MEMORY)
#define CMD_WRITE_EEPROM (0x30 | CMD_WRITE_MEMORY)
#define CMD_WRITE_PARAMETERS (0x40 | CMD_WRITE_MEMORY) /* only in APP */
/* CMD_SWITCH_APPLICATION parameter */
#define BOOTTYPE_BOOTLOADER 0x00 /* only in APP */
#define BOOTTYPE_APPLICATION 0x80
/* CMD_{READ|WRITE}_* parameter */
#define MEMTYPE_CHIPINFO 0x00
#define MEMTYPE_FLASH 0x01
#define MEMTYPE_EEPROM 0x02
#define MEMTYPE_PARAMETERS 0x03 /* only in APP */
const static uint8_t info[16] = "blctrl m88-v2.0";
ISR(TWI_vect)
{
static uint8_t cmd;
static uint8_t bcnt;
uint8_t data;
switch (TWSR & 0xF8) {
/* SLA + W received, ACK returned -> receive Data and ACK */
case 0x60:
bcnt = 0;
TWCR |= (1<<TWINT) | (1<<TWEA);
TWCR = (1<<TWEN) | (1<<TWIE) | (1<<TWINT) | (1<<TWEA);
break;
/* prev. SLA + W, data received, ACK returned -> receive Data and ACK */
case 0x80:
if (bcnt == 0) {
cmd = TWDR;
switch (cmd) {
case CMD_BOOT_LOADER:
wdt_enable(WDTO_15MS);
case CMD_GET_INFO:
case CMD_SET_PWM:
case CMD_GET_STATUS:
case CMD_SET_PARAM:
case CMD_GET_PARAM:
data = TWDR;
switch (bcnt) {
case 0:
switch (data) {
case CMD_SWITCH_APPLICATION:
case CMD_WRITE_MEMORY:
cmd = data;
bcnt++;
break;
default:
blmc.flags |= FLAG_I2C_ACTIVE;
setpwm(data);
cmd = CMD_WAIT;
bcnt = 0;
break;
}
break;
case 1:
switch (cmd) {
case CMD_SWITCH_APPLICATION:
if (data == BOOTTYPE_BOOTLOADER) {
wdt_enable(WDTO_15MS);
}
break;
} else if (cmd == CMD_SET_PWM) {
blmc.flags |= FLAG_I2C_ACTIVE;
setpwm(TWDR);
bcnt = 0;
case CMD_WRITE_MEMORY:
bcnt++;
if (data == MEMTYPE_PARAMETERS) {
cmd = CMD_WRITE_PARAMETERS;
}
break;
} else if (cmd == CMD_SET_PARAM) {
((uint8_t *)&params)[bcnt++ -1] = TWDR;
if (bcnt > sizeof(params)) {
write_parameters();
bcnt = 0;
default:
break;
}
break;
} else {
bcnt = 0;
case 2: /* ignore address bytes */
case 3:
bcnt++;
break;
default:
switch (cmd) {
case CMD_WRITE_PARAMETERS:
((uint8_t *)&params)[bcnt++ -4] = data;
if (bcnt == sizeof(params)) {
write_parameters();
}
break;
default:
break;
}
break;
}
TWCR |= (1<<TWINT) | (1<<TWEA);
TWCR = (1<<TWEN) | (1<<TWIE) | (1<<TWINT) | (1<<TWEA);
break;
/* SLA+R received, ACK returned -> send data */
@ -96,68 +146,68 @@ ISR(TWI_vect)
/* prev. SLA+R, data sent, ACK returned -> send data */
case 0xB8:
switch (cmd) {
case CMD_GET_INFO:
TWDR = info[bcnt++];
bcnt %= sizeof(info);
break;
case CMD_GET_STATUS:
case CMD_WAIT:
switch (bcnt++) {
case 0: TWDR = blmc.pwm - blmc.pwm_limit;
case 0: data = blmc.pwm - blmc.pwm_limit;
break;
case 1: TWDR = blmc.pwm;
case 1: data = blmc.pwm;
break;
case 2: TWDR = (blmc.rpm >> 8);
case 2: data = (blmc.rpm & 0xFF);
break;
case 3: TWDR = (blmc.rpm & 0xFF);
case 3: data = (blmc.rpm >> 8);
break;
case 4: TWDR = (blmc.current >> 8);
case 4: data = (blmc.current & 0xFF);
break;
case 5: TWDR = (blmc.current & 0xFF);
case 5: data = (blmc.current >> 8);
break;
case 6: TWDR = (blmc.voltage >> 8);
case 6: data = (blmc.voltage & 0xFF);
break;
case 7: TWDR = (blmc.voltage & 0xFF);
bcnt = 0;
case 7: data = (blmc.voltage >> 8);
break;
default:
bcnt = 0;
data = 0x00;
break;
}
break;
case CMD_GET_PARAM:
TWDR = ((uint8_t *)&params)[bcnt++];
case CMD_READ_VERSION:
data = info[bcnt++];
bcnt %= sizeof(info);
break;
case CMD_READ_PARAMETERS:
data = ((uint8_t *)&params)[bcnt++];
if (bcnt > sizeof(params))
bcnt = 0;
break;
default:
TWDR = 0xFF;
data = 0xFF;
break;
}
TWCR |= (1<<TWINT) | (1<<TWEA);
TWDR = data;
TWCR = (1<<TWEN) | (1<<TWIE) | (1<<TWINT) | (1<<TWEA);
break;
/* STOP or repeated START */
case 0xA0:
/* Data transmitted, NACK returned */
case 0xC0:
TWCR |= (1<<TWINT) | (1<<TWEA);
TWCR = (1<<TWEN) | (1<<TWIE) | (1<<TWINT) | (1<<TWEA);
break;
/* failsave -> reset Hardware */
default:
TWCR |= (1<<TWINT) | (1<<TWSTO) | (1<<TWEA);
TWCR = (1<<TWEN) | (1<<TWIE) | (1<<TWINT) | (1<<TWSTO) | (1<<TWEA);
break;
}
}

65
main.c

@ -31,6 +31,7 @@
#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/sleep.h>
#include "main.h"
#include "blmc.h"
@ -45,13 +46,13 @@ extern struct blmc_ blmc;
static uint8_t led[2];
ISR(TIMER0_OVF_vect)
ISR(TIMER1_COMPB_vect)
{
static uint8_t timer0_cnt = 0;
static uint8_t rpm_cnt = 0;
static uint8_t adc_chan = SENSE_CURRENT;
/* Come back in 20ms */
TCNT0 = 0xFF - 156;
OCR1B = TCNT1 + 20000;
/* commutations during last 20ms */
uint16_t diff = blmc.rpm_tmp - blmc.rpm_tmp_old;
@ -63,7 +64,7 @@ ISR(TIMER0_OVF_vect)
blmc.flags &= ~(FLAG_RUN_MASK);
blmc.flags |= FLAG_PWM_SPINUP | FLAG_COM_SPINUP;
}
#if 0
/* no i2c cmd in the last 20ms */
if (!(blmc.flags & FLAG_I2C_ACTIVE)) {
/* already in i2c timeout, turn off motor */
@ -75,7 +76,7 @@ ISR(TIMER0_OVF_vect)
} else {
blmc.flags &= ~FLAG_I2C_TIMEOUT;
}
#endif
blmc.flags &= ~FLAG_I2C_ACTIVE;
}
@ -83,9 +84,9 @@ ISR(TIMER0_OVF_vect)
setpwm(blmc.pwm);
/* calc rpm every second */
timer0_cnt++;
if (timer0_cnt == 50) {
timer0_cnt = 0;
rpm_cnt++;
if (rpm_cnt == 50) {
rpm_cnt = 0;
blmc.rpm = blmc.rpm_tmp;
blmc.rpm_tmp = 0;
@ -99,7 +100,6 @@ ISR(TIMER0_OVF_vect)
else
adc_chan = SENSE_CURRENT;
}
/* led blink timer */
static uint8_t led_timer = 0;
led_timer = (led_timer +1) & 0x1F;
@ -125,29 +125,49 @@ ISR(TIMER0_OVF_vect)
}
}
/*
* For newer devices (mega88) the watchdog timer remains active even after a
* system reset. So disable it as soon as possible.
* automagically called on startup
*/
void get_mcusr(void) __attribute__((naked, section(".init3")));
void get_mcusr(void)
{
MCUSR = 0;
WDTCSR = (1<<WDCE) | (0<<WDE);
}
int main(void)
{
DDRB = PHASE_H_MASK | LED_RT | LED_GN;
DDRD = PHASE_L_MASK;
DDRB = PHASE_A_EN | PHASE_A_PWM | LED_RT | LED_GN;
DDRD = PHASE_B_EN | PHASE_B_PWM | PHASE_C_EN | PHASE_C_PWM;
PORTB = 0x00;
PORTD = 0x00;
/* timer0: running with F_CPU/1024 */
TCCR0 = (1<<CS02) | (1<<CS00);
/* timer0: running with F_CPU, 8bit Phase Correct PWM (16kHz) */
TCCR0A = (1<<WGM00);
TCCR0B = (1<<CS00);
/* timer1: running with F_CPU, 8bit Phase Correct PWM (16kHz) */
TCCR1B = (1<<CS10);
TCCR1A = (1<<WGM10);
/* timer1: running with F_CPU/8 */
TCCR1B = (1<<CS11) | (1<<ICNC1);
/* timer2: running with F_CPU, 8bit Phase Correct PWM (16kHz) */
TCCR2 = (1<<WGM20) | (1<<CS20);
TCCR2A = (1<<WGM20);
TCCR2B = (1<<CS20);
/* sync PWM timers */
GTCCR = (1<<TSM) | (1<<PSRASY) | (1<<PSRSYNC);
TCNT0 = 0x00;
TCNT2 = 0x00;
GTCCR = (0<<TSM);
/* enable Timer0 OVF Interrupt */
TIMSK = (1<<TOIE0);
/* enable Timer1 OVF Interrupt */
TIMSK1 = (1<<OCIE1B);
/* Enable Analog Comparator Multiplexer */
SFIOR |= (1<<ACME);
ADCSRB |= (1<<ACME);
ACSR |= (1<<ACIC);
/* I2C Init: keep Address from bootloader, Auto ACKs with Interrupts */
TWCR = (1<<TWEA) | (1<<TWEN) | (1<<TWIE);
@ -156,6 +176,8 @@ int main(void)
if (read_parameters())
blmc.flags |= FLAG_INVALID_EEPROM;
set_sleep_mode(SLEEP_MODE_IDLE);
sei();
while (1) {
@ -204,6 +226,9 @@ int main(void)
/* do a spinup from main loop (blocking for > 200ms) */
if (blmc.flags & FLAG_COM_SPINUP)
spinup();
sleep_mode();
};
return 0;
}

19
main.h

@ -9,4 +9,23 @@
#define LED_RT (1<<PORTB4)
#define LED_GN (1<<PORTB5)
#define PHASE_A_EN (1<<PORTB2)
#define PHASE_A_PWM (1<<PORTB3)
#define PHASE_A_OC (1<<COM2A1)
#define PHASE_B_EN (1<<PORTD7)
#define PHASE_B_PWM (1<<PORTD5)
#define PHASE_B_OC (1<<COM0B1)
#define PHASE_C_EN (1<<PORTD4)
#define PHASE_C_PWM (1<<PORTD3)
#define PHASE_C_OC (1<<COM2B1)
#define SENSE_A 0
#define SENSE_B 2
#define SENSE_C 1
#define SENSE_VOLTAGE 7
#define SENSE_CURRENT 3
#endif
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