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#ifndef __TARGET_H__
#define __TARGET_H__
/* *********************************************************************** */
/*
* using ATmega168 @16MHz:
* Fuse E: 0xFA (512 words bootloader)
* Fuse H: 0xDD (2.7V BOD)
* Fuse L: 0xFF (external crystal)
*/
#define F_CPU 16000000
#define BAUDRATE 19200
#define RFM12_ADDRESS TWAR
/* 1ms @16MHz */
#define TIMEOUT 1000
#define TIMER_RELOAD (0xFF - 250)
/* *********************************************************************** */
#define LED_INIT() { DDRD |= ((1<<PORTD5) | (1<<PORTD6)); LED_OFF(); }
#define LED_GN_ON() PORTD &= ~(1<<PORTD5)
#define LED_GN_OFF() PORTD |= (1<<PORTD5)
#define LED_GN_TOGGLE() PORTD ^= (1<<PORTD5)
#define LED_RT_ON() PORTD &= ~(1<<PORTD6)
#define LED_RT_OFF() PORTD |= (1<<PORTD6)
#define LED_OFF() PORTD |= ((1<<PORTD5) | (1<<PORTD6))
/* *********************************************************************** */
#define UART_RXBUF_SIZE 16
#define UART_TXBUF_SIZE 128
/* *********************************************************************** */
#define PWM_TIM_INIT() { \
DDRB |= (1<<PORTB1) | (1<<PORTB2); \
/* Timer1: 8MHz, FastModePWM, overflow interrupt */ \
TCCR1A = (1<<WGM11) | (0<<WGM10); \
TCCR1B = (1<<WGM12) | (1<<WGM13); \
TIMSK1 = (1<<TOIE1); \
ICR1 = 0xFFFF; \
}
#define PWM_TIM_ENABLE() { TCCR1B |= (1<<CS10); }
#define PWM_TIM_DISABLE() { TCCR1B &= ~(1<<CS10); }
#define PWM_TIM_CHECK() (TCCR1A & ((1<<COM1A1) | (1<<COM1B1)))
#define PWM_TIM_VECT TIMER1_OVF_vect
#define PWM_CH0_PORT PORTB
#define PWM_CH0_NUM 1
#define PWM_CH0_OFF() { PWM_CH0_PORT &= ~(1<<PWM_CH0_NUM); TCCR1A &= ~(1<<COM1A1); }
#define PWM_CH0_ON() { PWM_CH0_PORT |= (1<<PWM_CH0_NUM); TCCR1A &= ~(1<<COM1A1); }
#define PWM_CH0_PWM(x) { PWM_CH0_PORT &= ~(1<<PWM_CH0_NUM); TCCR1A |= (1<<COM1A1); OCR1A = x; }
#define PWM_CH1_PORT PORTB
#define PWM_CH1_NUM 2
#define PWM_CH1_OFF() { PWM_CH1_PORT &= ~(1<<PWM_CH1_NUM); TCCR1A &= ~(1<<COM1B1); }
#define PWM_CH1_ON() { PWM_CH1_PORT |= (1<<PWM_CH1_NUM); TCCR1A &= ~(1<<COM1B1); }
#define PWM_CH1_PWM(x) { PWM_CH1_PORT &= ~(1<<PWM_CH1_NUM); TCCR1A |= (1<<COM1B1); OCR1B = x; }
/* *********************************************************************** */
#define RFM12_INT_INIT() EICRA |= (1<<ISC11)
#define RFM12_INT_ON() EIMSK |= (1<<INT1)
#define RFM12_INT_OFF() EIMSK &= ~(1<<INT1)
#define RFM12_INT_CLEAR() EIFR = INTF1
#define RFM12_INT_VECT INT1_vect
#define RFM12_CS_INIT() DDRD |= (1<<PORTD7)
#define RFM12_CS_ACTIVE() PORTD &= ~(1<<PORTD7)
#define RFM12_CS_INACTIVE() PORTD |= (1<<PORTD7)
#define RFM12_SPI_INIT() { /* SS, SCK and MOSI are outputs */ \
DDRB |= (1<<PORTB2) | (1<<PORTB3) | (1<<PORTB5); \
/* SPI Master, F_CPU /16 */ \
SPCR = (1<<SPE) | (1<<MSTR) | (1<<SPR0); \
}
/* *********************************************************************** */
#endif /* __TARGET_H__ */