578 lines
28 KiB
C
578 lines
28 KiB
C
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#ifndef _IMX_REGS_H
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#define _IMX_REGS_H
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/* ------------------------------------------------------------------------
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* Motorola IMX system registers
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* ------------------------------------------------------------------------
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*
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*/
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# ifndef __ASSEMBLY__
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# define __REG(x) (*((volatile u32 *)(x)))
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# define __REG2(x,y) \
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( __builtin_constant_p(y) ? (__REG((x) + (y))) \
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: (*(volatile u32 *)((u32)&__REG(x) + (y))) )
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# else
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# define __REG(x) (x)
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# define __REG2(x,y) ((x)+(y))
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#endif
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#define IMX_IO_BASE 0x00200000
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/*
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* Register BASEs, based on OFFSETs
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*
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*/
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#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
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#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE)
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#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE)
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#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE)
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#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE)
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#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE)
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#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE)
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#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE)
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#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE)
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#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE)
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#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE)
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#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE)
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#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE)
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#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE)
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#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE)
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#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE)
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#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE)
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#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE)
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#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE)
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#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE)
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#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE)
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#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE)
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#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE)
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#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE)
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#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE)
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#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE)
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#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE)
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#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)
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#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
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/* Watchdog Registers*/
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#define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
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#define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */
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#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */
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/* SYSCTRL Registers */
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#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */
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#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */
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#define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */
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/* Chip Select Registers */
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#define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */
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#define CS0L __REG(IMX_EIM_BASE + 0x4) /* Chip Select 0 Lower Register */
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#define CS1U __REG(IMX_EIM_BASE + 0x8) /* Chip Select 1 Upper Register */
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#define CS1L __REG(IMX_EIM_BASE + 0xc) /* Chip Select 1 Lower Register */
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#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */
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#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */
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#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */
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#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */
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#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */
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#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */
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#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */
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#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */
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#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */
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/* SDRAM controller registers */
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#define SDCTL0 __REG(IMX_SDRAMC_BASE) /* SDRAM 0 Control Register */
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#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4) /* SDRAM 1 Control Register */
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#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */
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#define SDRST __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */
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/* PLL registers */
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#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
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#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
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#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
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#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */
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#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
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#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
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#define CSCR_MPLL_RESTART (1<<21)
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/*
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* GPIO Module and I/O Multiplexer
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* x = 0..3 for reg_A, reg_B, reg_C, reg_D
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*/
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#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
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#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
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#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
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#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
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#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
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#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
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#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
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#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
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#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
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#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)
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#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8)
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#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8)
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#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8)
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#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8)
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#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8)
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#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
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#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
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#define GPIO_PIN_MASK 0x1f
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#define GPIO_PORT_MASK (0x3 << 5)
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#define GPIO_PORTA (0<<5)
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#define GPIO_PORTB (1<<5)
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#define GPIO_PORTC (2<<5)
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#define GPIO_PORTD (3<<5)
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#define GPIO_OUT (1<<7)
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#define GPIO_IN (0<<7)
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#define GPIO_PUEN (1<<8)
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#define GPIO_PF (0<<9)
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#define GPIO_AF (1<<9)
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#define GPIO_OCR_MASK (3<<10)
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#define GPIO_AIN (0<<10)
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#define GPIO_BIN (1<<10)
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#define GPIO_CIN (2<<10)
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#define GPIO_GPIO (3<<10)
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#define GPIO_AOUT (1<<12)
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#define GPIO_BOUT (1<<13)
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/* assignements for GPIO alternate/primary functions */
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/* FIXME: This list is not completed. The correct directions are
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* missing on some (many) pins
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*/
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#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 )
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#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 )
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#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 )
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#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 )
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#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 )
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#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
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#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 )
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#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 )
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#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 )
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#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 )
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#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 )
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#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 )
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#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 )
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#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 )
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#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 )
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#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 )
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#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 )
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#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 )
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#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
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#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
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#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
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#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 )
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#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
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#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
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#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
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#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 )
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#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 )
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#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 )
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#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 )
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#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
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#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 )
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#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
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#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 )
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#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
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#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 )
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#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
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#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 )
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#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
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#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 )
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#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
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#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 )
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#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
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#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 )
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#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 )
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#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
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#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 )
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#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 )
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#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 )
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#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 )
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#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 )
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#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 )
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#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 )
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#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 )
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#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 )
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#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 )
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#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 )
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#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 )
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#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 )
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#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
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#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
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#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 )
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#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 )
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#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 )
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#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 )
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#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 )
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#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 )
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#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 )
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#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 )
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#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 )
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#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 )
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#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
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#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
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#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
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#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
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#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 )
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#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 )
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#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
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#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
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#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 )
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#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 )
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#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
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#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
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#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
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#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
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#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
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#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 )
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#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 )
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#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 )
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#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 )
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#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
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#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 )
|
|||
|
|
#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
|
|||
|
|
#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 )
|
|||
|
|
#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 )
|
|||
|
|
#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
|
|||
|
|
#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 )
|
|||
|
|
#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 )
|
|||
|
|
#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
|
|||
|
|
#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 )
|
|||
|
|
#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
|
|||
|
|
#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
|
|||
|
|
#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 )
|
|||
|
|
#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
|
|||
|
|
#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
|
|||
|
|
#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
|
|||
|
|
#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
|
|||
|
|
#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
|
|||
|
|
#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
|
|||
|
|
#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
|
|||
|
|
#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
|
|||
|
|
#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
|
|||
|
|
#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
|
|||
|
|
#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
|
|||
|
|
#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
|
|||
|
|
#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
|
|||
|
|
#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
|
|||
|
|
#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
|
|||
|
|
#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
|
|||
|
|
#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
|
|||
|
|
#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
|
|||
|
|
#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
|
|||
|
|
#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
|
|||
|
|
#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 )
|
|||
|
|
#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 )
|
|||
|
|
|
|||
|
|
/*
|
|||
|
|
* DMA Controller
|
|||
|
|
*/
|
|||
|
|
#define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */
|
|||
|
|
#define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */
|
|||
|
|
#define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */
|
|||
|
|
#define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */
|
|||
|
|
#define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */
|
|||
|
|
#define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */
|
|||
|
|
#define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */
|
|||
|
|
#define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */
|
|||
|
|
#define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */
|
|||
|
|
#define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */
|
|||
|
|
#define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */
|
|||
|
|
#define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */
|
|||
|
|
#define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */
|
|||
|
|
#define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */
|
|||
|
|
#define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */
|
|||
|
|
#define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */
|
|||
|
|
#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */
|
|||
|
|
#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /*<2A>Control Registers */
|
|||
|
|
#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */
|
|||
|
|
#define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */
|
|||
|
|
#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */
|
|||
|
|
#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */
|
|||
|
|
|
|||
|
|
/* TODO: define DMA_REQ lines */
|
|||
|
|
|
|||
|
|
#define DCR_DRST (1<<1)
|
|||
|
|
#define DCR_DEN (1<<0)
|
|||
|
|
#define DBTOCR_EN (1<<15)
|
|||
|
|
#define DBTOCR_CNT(x) ((x) & 0x7fff )
|
|||
|
|
#define CNTR_CNT(x) ((x) & 0xffffff )
|
|||
|
|
#define CCR_DMOD_LINEAR ( 0x0 << 12 )
|
|||
|
|
#define CCR_DMOD_2D ( 0x1 << 12 )
|
|||
|
|
#define CCR_DMOD_FIFO ( 0x2 << 12 )
|
|||
|
|
#define CCR_DMOD_EOBFIFO ( 0x3 << 12 )
|
|||
|
|
#define CCR_SMOD_LINEAR ( 0x0 << 10 )
|
|||
|
|
#define CCR_SMOD_2D ( 0x1 << 10 )
|
|||
|
|
#define CCR_SMOD_FIFO ( 0x2 << 10 )
|
|||
|
|
#define CCR_SMOD_EOBFIFO ( 0x3 << 10 )
|
|||
|
|
#define CCR_MDIR_DEC (1<<9)
|
|||
|
|
#define CCR_MSEL_B (1<<8)
|
|||
|
|
#define CCR_DSIZ_32 ( 0x0 << 6 )
|
|||
|
|
#define CCR_DSIZ_8 ( 0x1 << 6 )
|
|||
|
|
#define CCR_DSIZ_16 ( 0x2 << 6 )
|
|||
|
|
#define CCR_SSIZ_32 ( 0x0 << 4 )
|
|||
|
|
#define CCR_SSIZ_8 ( 0x1 << 4 )
|
|||
|
|
#define CCR_SSIZ_16 ( 0x2 << 4 )
|
|||
|
|
#define CCR_REN (1<<3)
|
|||
|
|
#define CCR_RPT (1<<2)
|
|||
|
|
#define CCR_FRC (1<<1)
|
|||
|
|
#define CCR_CEN (1<<0)
|
|||
|
|
#define RTOR_EN (1<<15)
|
|||
|
|
#define RTOR_CLK (1<<14)
|
|||
|
|
#define RTOR_PSC (1<<13)
|
|||
|
|
|
|||
|
|
/*
|
|||
|
|
* LCD Controller
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
#define LCDC_SSA __REG(IMX_LCDC_BASE+0x00)
|
|||
|
|
|
|||
|
|
#define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04)
|
|||
|
|
#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
|
|||
|
|
#define SIZE_YMAX(y) ( (y) & 0x1ff )
|
|||
|
|
|
|||
|
|
#define LCDC_VPW __REG(IMX_LCDC_BASE+0x08)
|
|||
|
|
#define VPW_VPW(x) ( (x) & 0x3ff )
|
|||
|
|
|
|||
|
|
#define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C)
|
|||
|
|
#define CPOS_CC1 (1<<31)
|
|||
|
|
#define CPOS_CC0 (1<<30)
|
|||
|
|
#define CPOS_OP (1<<28)
|
|||
|
|
#define CPOS_CXP(x) (((x) & 3ff) << 16)
|
|||
|
|
#define CPOS_CYP(y) ((y) & 0x1ff)
|
|||
|
|
|
|||
|
|
#define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10)
|
|||
|
|
#define LCWHB_BK_EN (1<<31)
|
|||
|
|
#define LCWHB_CW(w) (((w) & 0x1f) << 24)
|
|||
|
|
#define LCWHB_CH(h) (((h) & 0x1f) << 16)
|
|||
|
|
#define LCWHB_BD(x) ((x) & 0xff)
|
|||
|
|
|
|||
|
|
#define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14)
|
|||
|
|
#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
|
|||
|
|
#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
|
|||
|
|
#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
|
|||
|
|
|
|||
|
|
#define LCDC_PCR __REG(IMX_LCDC_BASE+0x18)
|
|||
|
|
#define PCR_TFT (1<<31)
|
|||
|
|
#define PCR_COLOR (1<<30)
|
|||
|
|
#define PCR_PBSIZ_1 (0<<28)
|
|||
|
|
#define PCR_PBSIZ_2 (1<<28)
|
|||
|
|
#define PCR_PBSIZ_4 (2<<28)
|
|||
|
|
#define PCR_PBSIZ_8 (3<<28)
|
|||
|
|
#define PCR_BPIX_1 (0<<25)
|
|||
|
|
#define PCR_BPIX_2 (1<<25)
|
|||
|
|
#define PCR_BPIX_4 (2<<25)
|
|||
|
|
#define PCR_BPIX_8 (3<<25)
|
|||
|
|
#define PCR_BPIX_12 (4<<25)
|
|||
|
|
#define PCR_BPIX_16 (4<<25)
|
|||
|
|
#define PCR_PIXPOL (1<<24)
|
|||
|
|
#define PCR_FLMPOL (1<<23)
|
|||
|
|
#define PCR_LPPOL (1<<22)
|
|||
|
|
#define PCR_CLKPOL (1<<21)
|
|||
|
|
#define PCR_OEPOL (1<<20)
|
|||
|
|
#define PCR_SCLKIDLE (1<<19)
|
|||
|
|
#define PCR_END_SEL (1<<18)
|
|||
|
|
#define PCR_END_BYTE_SWAP (1<<17)
|
|||
|
|
#define PCR_REV_VS (1<<16)
|
|||
|
|
#define PCR_ACD_SEL (1<<15)
|
|||
|
|
#define PCR_ACD(x) (((x) & 0x7f) << 8)
|
|||
|
|
#define PCR_SCLK_SEL (1<<7)
|
|||
|
|
#define PCR_SHARP (1<<6)
|
|||
|
|
#define PCR_PCD(x) ((x) & 0x3f)
|
|||
|
|
|
|||
|
|
#define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C)
|
|||
|
|
#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
|
|||
|
|
#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
|
|||
|
|
#define HCR_H_WAIT_2(x) ((x) & 0xff)
|
|||
|
|
|
|||
|
|
#define LCDC_VCR __REG(IMX_LCDC_BASE+0x20)
|
|||
|
|
#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
|
|||
|
|
#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
|
|||
|
|
#define VCR_V_WAIT_2(x) ((x) & 0xff)
|
|||
|
|
|
|||
|
|
#define LCDC_POS __REG(IMX_LCDC_BASE+0x24)
|
|||
|
|
#define POS_POS(x) ((x) & 1f)
|
|||
|
|
|
|||
|
|
#define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28)
|
|||
|
|
#define LSCR1_GRAY1(x) (((x) & 0xf) << 4)
|
|||
|
|
#define LSCR1_GRAY2(x) ((x) & 0xf)
|
|||
|
|
|
|||
|
|
#define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C)
|
|||
|
|
#define PWMR_CLS(x) (((x) & 0x1ff) << 16)
|
|||
|
|
#define PWMR_LDMSK (1<<15)
|
|||
|
|
#define PWMR_SCR1 (1<<10)
|
|||
|
|
#define PWMR_SCR0 (1<<9)
|
|||
|
|
#define PWMR_CC_EN (1<<8)
|
|||
|
|
#define PWMR_PW(x) ((x) & 0xff)
|
|||
|
|
|
|||
|
|
#define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30)
|
|||
|
|
#define DMACR_BURST (1<<31)
|
|||
|
|
#define DMACR_HM(x) (((x) & 0xf) << 16)
|
|||
|
|
#define DMACR_TM(x) ((x) &0xf)
|
|||
|
|
|
|||
|
|
#define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34)
|
|||
|
|
#define RMCR_LCDC_EN (1<<1)
|
|||
|
|
#define RMCR_SELF_REF (1<<0)
|
|||
|
|
|
|||
|
|
#define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38)
|
|||
|
|
#define LCDICR_INT_SYN (1<<2)
|
|||
|
|
#define LCDICR_INT_CON (1)
|
|||
|
|
|
|||
|
|
#define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40)
|
|||
|
|
#define LCDISR_UDR_ERR (1<<3)
|
|||
|
|
#define LCDISR_ERR_RES (1<<2)
|
|||
|
|
#define LCDISR_EOF (1<<1)
|
|||
|
|
#define LCDISR_BOF (1<<0)
|
|||
|
|
/*
|
|||
|
|
* UART Module
|
|||
|
|
*/
|
|||
|
|
#define URXD0(x) __REG2( IMX_UART1_BASE + 0x0, ((x) & 1) << 12) /* Receiver Register */
|
|||
|
|
#define URTX0(x) __REG2( IMX_UART1_BASE + 0x40, ((x) & 1) << 12) /* Transmitter Register */
|
|||
|
|
#define UCR1(x) __REG2( IMX_UART1_BASE + 0x80, ((x) & 1) << 12) /* Control Register 1 */
|
|||
|
|
#define UCR2(x) __REG2( IMX_UART1_BASE + 0x84, ((x) & 1) << 12) /* Control Register 2 */
|
|||
|
|
#define UCR3(x) __REG2( IMX_UART1_BASE + 0x88, ((x) & 1) << 12) /* Control Register 3 */
|
|||
|
|
#define UCR4(x) __REG2( IMX_UART1_BASE + 0x8c, ((x) & 1) << 12) /* Control Register 4 */
|
|||
|
|
#define UFCR(x) __REG2( IMX_UART1_BASE + 0x90, ((x) & 1) << 12) /* FIFO Control Register */
|
|||
|
|
#define USR1(x) __REG2( IMX_UART1_BASE + 0x94, ((x) & 1) << 12) /* Status Register 1 */
|
|||
|
|
#define USR2(x) __REG2( IMX_UART1_BASE + 0x98, ((x) & 1) << 12) /* Status Register 2 */
|
|||
|
|
#define UESC(x) __REG2( IMX_UART1_BASE + 0x9c, ((x) & 1) << 12) /* Escape Character Register */
|
|||
|
|
#define UTIM(x) __REG2( IMX_UART1_BASE + 0xa0, ((x) & 1) << 12) /* Escape Timer Register */
|
|||
|
|
#define UBIR(x) __REG2( IMX_UART1_BASE + 0xa4, ((x) & 1) << 12) /* BRM Incremental Register */
|
|||
|
|
#define UBMR(x) __REG2( IMX_UART1_BASE + 0xa8, ((x) & 1) << 12) /* BRM Modulator Register */
|
|||
|
|
#define UBRC(x) __REG2( IMX_UART1_BASE + 0xac, ((x) & 1) << 12) /* Baud Rate Count Register */
|
|||
|
|
#define BIPR1(x) __REG2( IMX_UART1_BASE + 0xb0, ((x) & 1) << 12) /* Incremental Preset Register 1 */
|
|||
|
|
#define BIPR2(x) __REG2( IMX_UART1_BASE + 0xb4, ((x) & 1) << 12) /* Incremental Preset Register 2 */
|
|||
|
|
#define BIPR3(x) __REG2( IMX_UART1_BASE + 0xb8, ((x) & 1) << 12) /* Incremental Preset Register 3 */
|
|||
|
|
#define BIPR4(x) __REG2( IMX_UART1_BASE + 0xbc, ((x) & 1) << 12) /* Incremental Preset Register 4 */
|
|||
|
|
#define BMPR1(x) __REG2( IMX_UART1_BASE + 0xc0, ((x) & 1) << 12) /* BRM Modulator Register 1 */
|
|||
|
|
#define BMPR2(x) __REG2( IMX_UART1_BASE + 0xc4, ((x) & 1) << 12) /* BRM Modulator Register 2 */
|
|||
|
|
#define BMPR3(x) __REG2( IMX_UART1_BASE + 0xc8, ((x) & 1) << 12) /* BRM Modulator Register 3 */
|
|||
|
|
#define BMPR4(x) __REG2( IMX_UART1_BASE + 0xcc, ((x) & 1) << 12) /* BRM Modulator Register 4 */
|
|||
|
|
#define UTS(x) __REG2( IMX_UART1_BASE + 0xd0, ((x) & 1) << 12) /* UART Test Register */
|
|||
|
|
|
|||
|
|
/* UART Control Register Bit Fields.*/
|
|||
|
|
#define URXD_CHARRDY (1<<15)
|
|||
|
|
#define URXD_ERR (1<<14)
|
|||
|
|
#define URXD_OVRRUN (1<<13)
|
|||
|
|
#define URXD_FRMERR (1<<12)
|
|||
|
|
#define URXD_BRK (1<<11)
|
|||
|
|
#define URXD_PRERR (1<<10)
|
|||
|
|
#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
|
|||
|
|
#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
|
|||
|
|
#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
|
|||
|
|
#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
|
|||
|
|
#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
|
|||
|
|
#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
|
|||
|
|
#define UCR1_IREN (1<<7) /* Infrared interface enable */
|
|||
|
|
#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
|
|||
|
|
#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
|
|||
|
|
#define UCR1_SNDBRK (1<<4) /* Send break */
|
|||
|
|
#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
|
|||
|
|
#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
|
|||
|
|
#define UCR1_DOZE (1<<1) /* Doze */
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#define UCR1_UARTEN (1<<0) /* UART enabled */
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#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
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#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
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#define UCR2_CTSC (1<<13) /* CTS pin control */
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#define UCR2_CTS (1<<12) /* Clear to send */
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#define UCR2_ESCEN (1<<11) /* Escape enable */
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#define UCR2_PREN (1<<8) /* Parity enable */
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#define UCR2_PROE (1<<7) /* Parity odd/even */
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#define UCR2_STPB (1<<6) /* Stop */
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#define UCR2_WS (1<<5) /* Word size */
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#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
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#define UCR2_TXEN (1<<2) /* Transmitter enabled */
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#define UCR2_RXEN (1<<1) /* Receiver enabled */
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#define UCR2_SRST (1<<0) /* SW reset */
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#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
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#define UCR3_PARERREN (1<<12) /* Parity enable */
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#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
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#define UCR3_DSR (1<<10) /* Data set ready */
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#define UCR3_DCD (1<<9) /* Data carrier detect */
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#define UCR3_RI (1<<8) /* Ring indicator */
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#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
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#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
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#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
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#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
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#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
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#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
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#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
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#define UCR3_BPEN (1<<0) /* Preset registers enable */
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#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
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#define UCR4_INVR (1<<9) /* Inverted infrared reception */
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#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
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#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
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#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
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#define UCR4_IRSC (1<<5) /* IR special case */
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#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
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#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
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#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
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#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
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#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
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#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
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#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
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#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
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#define USR1_RTSS (1<<14) /* RTS pin status */
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#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
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#define USR1_RTSD (1<<12) /* RTS delta */
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#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
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#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
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#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
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#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
|
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#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
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#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
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#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
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#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
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#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
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#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
|
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#define USR2_IDLE (1<<12) /* Idle condition */
|
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#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
|
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#define USR2_WAKE (1<<7) /* Wake */
|
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#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
|
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#define USR2_TXDC (1<<3) /* Transmitter complete */
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|
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#define USR2_BRCD (1<<2) /* Break condition */
|
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#define USR2_ORE (1<<1) /* Overrun error */
|
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|
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#define USR2_RDR (1<<0) /* Recv data ready */
|
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|
|
#define UTS_FRCPERR (1<<13) /* Force parity error */
|
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|
|
#define UTS_LOOP (1<<12) /* Loop tx and rx */
|
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|
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#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
|
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|
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#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
|
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|
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#define UTS_TXFULL (1<<4) /* TxFIFO full */
|
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|
|
#define UTS_RXFULL (1<<3) /* RxFIFO full */
|
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|
|
#define UTS_SOFTRST (1<<0) /* Software reset */
|
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|
|
|
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|
|
/* General purpose timers registers */
|
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|
|
#define TCTL1 __REG(IMX_TIM1_BASE)
|
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|
|
#define TPRER1 __REG(IMX_TIM1_BASE + 0x4)
|
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|
|
#define TCMP1 __REG(IMX_TIM1_BASE + 0x8)
|
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|
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#define TCR1 __REG(IMX_TIM1_BASE + 0xc)
|
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|
|
#define TCN1 __REG(IMX_TIM1_BASE + 0x10)
|
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|
|
#define TSTAT1 __REG(IMX_TIM1_BASE + 0x14)
|
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|
|
#define TCTL2 __REG(IMX_TIM2_BASE)
|
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|
|
#define TPRER2 __REG(IMX_TIM2_BASE + 0x4)
|
|||
|
|
#define TCMP2 __REG(IMX_TIM2_BASE + 0x8)
|
|||
|
|
#define TCR2 __REG(IMX_TIM2_BASE + 0xc)
|
|||
|
|
#define TCN2 __REG(IMX_TIM2_BASE + 0x10)
|
|||
|
|
#define TSTAT2 __REG(IMX_TIM2_BASE + 0x14)
|
|||
|
|
|
|||
|
|
/* General purpose timers bitfields */
|
|||
|
|
#define TCTL_SWR (1<<15) /* Software reset */
|
|||
|
|
#define TCTL_FRR (1<<8) /* Freerun / restart */
|
|||
|
|
#define TCTL_CAP (3<<6) /* Capture Edge */
|
|||
|
|
#define TCTL_OM (1<<5) /* output mode */
|
|||
|
|
#define TCTL_IRQEN (1<<4) /* interrupt enable */
|
|||
|
|
#define TCTL_CLKSOURCE (7<<1) /* Clock source */
|
|||
|
|
#define TCTL_TEN (1) /* Timer enable */
|
|||
|
|
#define TPRER_PRES (0xff) /* Prescale */
|
|||
|
|
#define TSTAT_CAPT (1<<1) /* Capture event */
|
|||
|
|
#define TSTAT_COMP (1) /* Compare event */
|
|||
|
|
|
|||
|
|
#endif /* _IMX_REGS_H */
|