razzor/uboot-1.1.4-kirkwood
1
0
Fork 0
Code Activity

u-boot 1.1.4

Browse Source
This commit is contained in:
razzor
2024-01-07 23:57:24 +01:00
commit f69754bccc
3902 changed files with 1074450 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
CHANGELOG
+4432
View File
File diff suppressed because it is too large Load Diff
COPYING
+298
View File
@@ -0,0 +1,298 @@
NOTE! This copyright does *not* cover the so-called "standalone"
applications that use U-Boot services by means of the jump table
provided by U-Boot exactly for this purpose - this is merely
considered normal use of U-Boot, and does *not* fall under the
heading of "derived work".
The header files "include/image.h" and "include/asm-*/u-boot.h"
define interfaces to U-Boot. Including these (unmodified) header
files in another file is considered normal use of U-Boot, and does
*not* fall under the heading of "derived work".
Also note that the GPL below is copyrighted by the Free Software
Foundation, but the instance of code that it refers to (the U-Boot
source code) is copyrighted by me and others who actually wrote it.
-- Wolfgang Denk
=======================================================================
GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
The licenses for most software are designed to take away your
freedom to share and change it. By contrast, the GNU General Public
License is intended to guarantee your freedom to share and change free
software--to make sure the software is free for all its users. This
General Public License applies to most of the Free Software
Foundation's software and to any other program whose authors commit to
using it. (Some other Free Software Foundation software is covered by
the GNU Library General Public License instead.) You can apply it to
your programs, too.
When we speak of free software, we are referring to freedom, not
price. Our General Public Licenses are designed to make sure that you
have the freedom to distribute copies of free software (and charge for
this service if you wish), that you receive source code or can get it
if you want it, that you can change the software or use pieces of it
in new free programs; and that you know you can do these things.
To protect your rights, we need to make restrictions that forbid
anyone to deny you these rights or to ask you to surrender the rights.
These restrictions translate to certain responsibilities for you if you
distribute copies of the software, or if you modify it.
For example, if you distribute copies of such a program, whether
gratis or for a fee, you must give the recipients all the rights that
you have. You must make sure that they, too, receive or can get the
source code. And you must show them these terms so they know their
rights.
We protect your rights with two steps: (1) copyright the software, and
(2) offer you this license which gives you legal permission to copy,
distribute and/or modify the software.
Also, for each author's protection and ours, we want to make certain
that everyone understands that there is no warranty for this free
software. If the software is modified by someone else and passed on, we
want its recipients to know that what they have is not the original, so
that any problems introduced by others will not reflect on the original
authors' reputations.
Finally, any free program is threatened constantly by software
patents. We wish to avoid the danger that redistributors of a free
program will individually obtain patent licenses, in effect making the
program proprietary. To prevent this, we have made it clear that any
patent must be licensed for everyone's free use or not licensed at all.
The precise terms and conditions for copying, distribution and
modification follow.
GNU GENERAL PUBLIC LICENSE
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
0. This License applies to any program or other work which contains
a notice placed by the copyright holder saying it may be distributed
under the terms of this General Public License. The "Program", below,
refers to any such program or work, and a "work based on the Program"
means either the Program or any derivative work under copyright law:
that is to say, a work containing the Program or a portion of it,
either verbatim or with modifications and/or translated into another
language. (Hereinafter, translation is included without limitation in
the term "modification".) Each licensee is addressed as "you".
Activities other than copying, distribution and modification are not
covered by this License; they are outside its scope. The act of
running the Program is not restricted, and the output from the Program
is covered only if its contents constitute a work based on the
Program (independent of having been made by running the Program).
Whether that is true depends on what the Program does.
1. You may copy and distribute verbatim copies of the Program's
source code as you receive it, in any medium, provided that you
conspicuously and appropriately publish on each copy an appropriate
copyright notice and disclaimer of warranty; keep intact all the
notices that refer to this License and to the absence of any warranty;
and give any other recipients of the Program a copy of this License
along with the Program.
You may charge a fee for the physical act of transferring a copy, and
you may at your option offer warranty protection in exchange for a fee.
2. You may modify your copy or copies of the Program or any portion
of it, thus forming a work based on the Program, and copy and
distribute such modifications or work under the terms of Section 1
above, provided that you also meet all of these conditions:
a) You must cause the modified files to carry prominent notices
stating that you changed the files and the date of any change.
b) You must cause any work that you distribute or publish, that in
whole or in part contains or is derived from the Program or any
part thereof, to be licensed as a whole at no charge to all third
parties under the terms of this License.
c) If the modified program normally reads commands interactively
when run, you must cause it, when started running for such
interactive use in the most ordinary way, to print or display an
announcement including an appropriate copyright notice and a
notice that there is no warranty (or else, saying that you provide
a warranty) and that users may redistribute the program under
these conditions, and telling the user how to view a copy of this
License. (Exception: if the Program itself is interactive but
does not normally print such an announcement, your work based on
the Program is not required to print an announcement.)
These requirements apply to the modified work as a whole. If
identifiable sections of that work are not derived from the Program,
and can be reasonably considered independent and separate works in
themselves, then this License, and its terms, do not apply to those
sections when you distribute them as separate works. But when you
distribute the same sections as part of a whole which is a work based
on the Program, the distribution of the whole must be on the terms of
this License, whose permissions for other licensees extend to the
entire whole, and thus to each and every part regardless of who wrote it.
Thus, it is not the intent of this section to claim rights or contest
your rights to work written entirely by you; rather, the intent is to
exercise the right to control the distribution of derivative or
collective works based on the Program.
In addition, mere aggregation of another work not based on the Program
with the Program (or with a work based on the Program) on a volume of
a storage or distribution medium does not bring the other work under
the scope of this License.
3. You may copy and distribute the Program (or a work based on it,
under Section 2) in object code or executable form under the terms of
Sections 1 and 2 above provided that you also do one of the following:
a) Accompany it with the complete corresponding machine-readable
source code, which must be distributed under the terms of Sections
1 and 2 above on a medium customarily used for software interchange; or,
b) Accompany it with a written offer, valid for at least three
years, to give any third party, for a charge no more than your
cost of physically performing source distribution, a complete
machine-readable copy of the corresponding source code, to be
distributed under the terms of Sections 1 and 2 above on a medium
customarily used for software interchange; or,
c) Accompany it with the information you received as to the offer
to distribute corresponding source code. (This alternative is
allowed only for noncommercial distribution and only if you
received the program in object code or executable form with such
an offer, in accord with Subsection b above.)
The source code for a work means the preferred form of the work for
making modifications to it. For an executable work, complete source
code means all the source code for all modules it contains, plus any
associated interface definition files, plus the scripts used to
control compilation and installation of the executable. However, as a
special exception, the source code distributed need not include
anything that is normally distributed (in either source or binary
form) with the major components (compiler, kernel, and so on) of the
operating system on which the executable runs, unless that component
itself accompanies the executable.
If distribution of executable or object code is made by offering
access to copy from a designated place, then offering equivalent
access to copy the source code from the same place counts as
distribution of the source code, even though third parties are not
compelled to copy the source along with the object code.
4. You may not copy, modify, sublicense, or distribute the Program
except as expressly provided under this License. Any attempt
otherwise to copy, modify, sublicense or distribute the Program is
void, and will automatically terminate your rights under this License.
However, parties who have received copies, or rights, from you under
this License will not have their licenses terminated so long as such
parties remain in full compliance.
5. You are not required to accept this License, since you have not
signed it. However, nothing else grants you permission to modify or
distribute the Program or its derivative works. These actions are
prohibited by law if you do not accept this License. Therefore, by
modifying or distributing the Program (or any work based on the
Program), you indicate your acceptance of this License to do so, and
all its terms and conditions for copying, distributing or modifying
the Program or works based on it.
6. Each time you redistribute the Program (or any work based on the
Program), the recipient automatically receives a license from the
original licensor to copy, distribute or modify the Program subject to
these terms and conditions. You may not impose any further
restrictions on the recipients' exercise of the rights granted herein.
You are not responsible for enforcing compliance by third parties to
this License.
7. If, as a consequence of a court judgment or allegation of patent
infringement or for any other reason (not limited to patent issues),
conditions are imposed on you (whether by court order, agreement or
otherwise) that contradict the conditions of this License, they do not
excuse you from the conditions of this License. If you cannot
distribute so as to satisfy simultaneously your obligations under this
License and any other pertinent obligations, then as a consequence you
may not distribute the Program at all. For example, if a patent
license would not permit royalty-free redistribution of the Program by
all those who receive copies directly or indirectly through you, then
the only way you could satisfy both it and this License would be to
refrain entirely from distribution of the Program.
If any portion of this section is held invalid or unenforceable under
any particular circumstance, the balance of the section is intended to
apply and the section as a whole is intended to apply in other
circumstances.
It is not the purpose of this section to induce you to infringe any
patents or other property right claims or to contest validity of any
such claims; this section has the sole purpose of protecting the
integrity of the free software distribution system, which is
implemented by public license practices. Many people have made
generous contributions to the wide range of software distributed
through that system in reliance on consistent application of that
system; it is up to the author/donor to decide if he or she is willing
to distribute software through any other system and a licensee cannot
impose that choice.
This section is intended to make thoroughly clear what is believed to
be a consequence of the rest of this License.
8. If the distribution and/or use of the Program is restricted in
certain countries either by patents or by copyrighted interfaces, the
original copyright holder who places the Program under this License
may add an explicit geographical distribution limitation excluding
those countries, so that distribution is permitted only in or among
countries not thus excluded. In such case, this License incorporates
the limitation as if written in the body of this License.
9. The Free Software Foundation may publish revised and/or new versions
of the General Public License from time to time. Such new versions will
be similar in spirit to the present version, but may differ in detail to
address new problems or concerns.
Each version is given a distinguishing version number. If the Program
specifies a version number of this License which applies to it and "any
later version", you have the option of following the terms and conditions
either of that version or of any later version published by the Free
Software Foundation. If the Program does not specify a version number of
this License, you may choose any version ever published by the Free Software
Foundation.
10. If you wish to incorporate parts of the Program into other free
programs whose distribution conditions are different, write to the author
to ask for permission. For software which is copyrighted by the Free
Software Foundation, write to the Free Software Foundation; we sometimes
make exceptions for this. Our decision will be guided by the two goals
of preserving the free status of all derivatives of our free software and
of promoting the sharing and reuse of software generally.
NO WARRANTY
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
REPAIR OR CORRECTION.
12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
END OF TERMS AND CONDITIONS
CREDITS
+458
View File
@@ -0,0 +1,458 @@
#
# Parts of the development effort for this project have been
# sponsored by SIEMENS AG, Austria. Thanks to SIEMENS for
# supporting an Open Source project!
#
#
# This is at least a partial credits-file of individual people that
# have contributed to the U-Boot project. It is sorted by name and
# formatted to allow easy grepping and beautification by scripts.
# The fields are: name (N), email (E), web-address (W), PGP key ID
# and fingerprint (P), description (D), and snail-mail address (S).
# Thanks,
#
# Wolfgang Denk
#----------
N: Dr. Bruno Achauer
E: bruno@exet-ag.de
D: Support for NetBSD (both as host and target system)
N: Guillaume Alexandre
E: guillaume.alexandre@gespac.ch
D: Add PCIPPC6 configuration
N: Swen Anderson
E: sand@peppercon.de
D: ERIC Support
N: Pantelis Antoniou
E: panto@intracom.gr
D: NETVIA & NETPHONE board support, ARTOS support.
D: Support for Silicon Turnkey eXpress XTc
N: Pierre Aubert
E: <p.aubert@staubli.com>
D: Support for RPXClassic board
N: Yuli Barcohen
E: yuli@arabellasw.com
D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards.
D: Support for Zephyr Engineering ZPC.1900 board.
D: Support for Interphase iSPAN boards.
D: Support for Analogue&Micro Adder boards.
D: Support for Analogue&Micro Rattler boards.
W: http://www.arabellasw.com
N: Jerry van Baren
E: <vanbaren@cideas.com>
D: BedBug port to 603e core (MPC82xx). Code for enhanced memory test.
N: Pavel Bartusek
E: <pba@sysgo.com>
D: Reiserfs support
W: http://www.elinos.com
N: Andre Beaudin
E: <andre.beaudin@colubris.com>
D: PCMCIA, Ethernet, TFTP
N: Jon Benediktsson
E: jonb@marel.is
D: Support for Marel V37 board
N: Raphael Bossek
E: raphael.bossek@solutions4linux.de
D: 8xxrom-0.3.0
N: Cliff Brake
E: cliff.brake@gmail.com
D: Port to Vibren PXA255 IDP platform
W: http://www.vibren.com
W: http://bec-systems.com
N: Rick Bronson
E: rick@efn.org
D: Atmel AT91RM9200DK and NAND support
N: David Brown
E: DBrown03@harris.com
D: Extensions to 8xxrom-0.3.0
N: Oliver Brown
E: obrown@adventnetworks.com
D: Port to the gw8260 board
N: Curt Brune
E: curt@cucy.com
D: Added support for Samsung S3C4510B CPU (ARM7tdmi based SoC)
D: Added support for ESPD-Inc. EVB4510 Board
W: http://www.cucy.com
N: Jonathan De Bruyne
E: jonathan.debruyne@siemens.atea.be
D: Port to Siemens IAD210 board
N: Ken Chou
E: kchou@ieee.org
D: Support for A3000 SBC board
N: Conn Clark
E: clark@esteem.com
D: ESTEEM192E support
N: Magnus Damm
E: damm@opensource.se
D: 8xxrom
N: George G. Davis
E: gdavis@mvista.com
D: Board ports for ADS GraphicsClient+ and Intel Assabet
N: Arun Dharankar
E: ADharankar@ATTBI.Com
D: threads / scheduler example code
N: Kári Davíðsson
E: kd@flaga.is
D: FLAGA DM Support
N: Wolfgang Denk
E: wd@denx.de
D: U-Boot initial version, continuing maintenance, ARMBoot merge
W: http://www.denx.de
N: Dan A. Dickey
E: ddickey@charter.net
D: FADS Support
N: James F. Dougherty
E: jfd@GigabitNetworks.COM
D: Port to the MOUSSE board
N: Dave Ellis
E: DGE@sixnetio.com
D: EEPROM Speedup, SXNI855T port
N: Thomas Elste
E: info@elste.org
D: Port for the ModNET50 Board, NET+50 CPU Port
W: http://www.imms.de
N: Daniel Engström
E: daniel@omicron.se
D: x86 port, Support for sc520_cdp board
N: Dr. Wolfgang Grandegger
E: wg@denx.de
D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards
W: www.denx.de
N: Peter Figuli
E: peposh@etc.sk
D: Support for WEP EP250 (PXA) board
N: Thomas Frieden
E: ThomasF@hyperion-entertainment.com
D: Support for AmigaOne
N: Frank Gottschling
E: fgottschling@eltec.de
D: Support for ELTEC MHPC/BAB7xx/ELPPC boards, cfb-console, i8042, SMI LynxEM
W: www.eltec.de
N: Marius Groeger
E: mgroeger@sysgo.de
D: MBX Support, board specific function interface, EST SBC8260 support; initial support for StrongARM (LART), ARM720TDMI (implementa A7)
W: www.elinos.com
N: Kirk Haderlie
E: khaderlie@vividimage.com
D: Added TFTP to 8xxrom (-> 0.3.1)
N: Chris Hallinan
E: clh@net1plus.com
D: DHCP Support
N: Anne-Sophie Harnois
E: Anne-Sophie.Harnois@nextream.fr
D: Port to Walnut405 board
N: Andreas Heppel
E: aheppel@sysgo.de
D: CPU Support for MPC 75x; board support for Eltec BAB750 [obsolete!]
N: August Hoeraendl
E: august.hoerandl@gmx.at
D: Support for the logodl board (PXA2xx)
N: Josh Huber
E: huber@alum.wpi.edu
D: Port to the Galileo Evaluation Board, and the MPC74xx cpu series.
W: http://www.mclx.com/
H: Stuart Hughes
E: stuarth@lineo.com
D: Port to MPC8260ADS board
H: Rich Ireland
E: r.ireland@computer.org
D: FPGA device configuration driver
N: Gary Jennejohn
E: garyj@jennejohn.org, gj@denx.de
D: Support for Samsung ARM920T S3C2400X, ARM920T "TRAB"
W: www.denx.de
N: Murray Jensen
E: Murray.Jensen@csiro.au
D: Initial 8260 support; GDB support
D: Port to Cogent+Hymod boards; Hymod Board Database
N: Yoo. Jonghoon
E: yooth@ipone.co.kr
D: Added port to the RPXlite board
N: Mark Jonas
E: mark.jonas@freescale.com
D: Support for Freescale Total5200 platform
W: http://www.mobilegt.com/
N: Sam Song
E: samsongshu@yahoo.com.cn
D: Port to the RPXlite_DW board
N: Brad Kemp
E: Brad.Kemp@seranoa.com
D: Port to Windriver ppmc8260 board
N: Sangmoon Kim
E: dogoil@etinsys.com
D: Support for debris board
N: Frederick W. Klatt
E: fred.klatt@windriver.com
D: Support for Wind River SBC8540/SBC8560 boards
N: Thomas Koeller
E: tkoeller@gmx.net
D: Port to Motorola Sandpoint 3 (MPC8240)
N: Raghu Krishnaprasad
E: Raghu.Krishnaprasad@fci.com
D: Support for Adder-II MPC852T evaluation board
W: http://www.forcecomputers.com
N: Bernhard Kuhn
E: bkuhn@metrowerks.com
D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards
N: Prakash Kumar
E: prakash@embedx.com
D Support for Intrinsyc CERF PXA250 board.
N: Thomas Lange
E: thomas@corelatus.se
D: Support for GTH and dbau1x00 boards; lots of PCMCIA fixes
N: Marc Leeman
E: marc.leeman@barco.com
D: Support for Barco Streaming Video Card (SVC) and Sample Compress Network (SCN)
W: www.barco.com
N: The LEOX team
E: team@leox.org
D: Support for LEOX boards, DS164x RTC
W: http://www.leox.org
N: Leif Lindholm
E: leif.lindholm@i3micro.com
D: Support for AMD dbau1550 board.
N: Stephan Linz
E: linz@li-pro.net
D: Support for Nios Stratix Development Kit (DK-1S10)
D: Support for SSV ADNP/ESC1 (Nios Cyclone)
W: http://www.li-pro.net
N: Raymond Lo
E: lo@routefree.com
D: Support for DOS partitions
N: Dan Malek
E: dan@embeddedalley.com
D: FADSROM, the grandfather of all of this
D: Support for Silicon Turnkey eXpress XTc
N: Andrea "llandre" Marson
E: andrea.marson@dave-tech.it
D: Port to PPChameleonEVB board
W: www.dave-tech.it
N: Reinhard Meyer
E: r.meyer@emk-elektronik.de
D: Port to EMK TOP860 Module
N: Jay Monkman
E: jtm@smoothsmoothie.com
D: EST SBC8260 support
N: Frank Morauf
E: frank.morauf@salzbrenner.com
D: Support for Embedded Planet RPX Super Board
N: David Müller
E: d.mueller@elsoft.ch
D: Support for Samsung ARM920T SMDK2410 eval board
N: Scott McNutt
E: smcnutt@psyent.com
D: Support for Altera Nios-32 CPU
D: Support for Altera Nios-II CPU
D: Support for Nios Cyclone Development Kit (DK-1C20)
W: http://www.psyent.com
N: Rolf Offermanns
E: rof@sysgo.de
D: Initial support for SSV-DNP1110, SMC91111 driver
W: www.elinos.com
N: John Otken
E: jotken@softadvances.com
D: Support for AMCC Luan 440SP board
N: Tolunay Orkun
E: torkun@nextio.com
D: Support for Cogent CSB272 & CSB472 boards
N: Keith Outwater
E: keith_outwater@mvis.com
D: Support for generic/custom MPC860T boards (GEN860T, GEN860T_SC)
N: Frank Panno
E: fpanno@delphintech.com
D: Support for Embedded Planet EP8260 Board
N: Denis Peter
E: d.peter@mpl.ch
D: Support for 4xx SCSI, floppy, CDROM, CT69000 video, ...
D: Support for PIP405 board
D: Support for MIP405 board
N: Dave Peverley
E: dpeverley@mpc-data.co.uk
W: http://www.mpc-data.co.uk
D: OMAP730 P2 board support
N: Bill Pitts
E: wlp@mindspring.com
D: BedBug embedded debugger code
N: Daniel Poirot
E: dan.poirot@windriver.com
D: Support for the Wind River sbc405, sbc8240 board
W: http://www.windriver.com
N: Stefan Roese
E: stefan.roese@esd-electronics.com
D: AMCC PPC401/403/405GP Support; Windows environment support
N: Erwin Rol
E: erwin@muffin.org
D: boot support for RTEMS
N: Paul Ruhland
E: pruhland@rochester.rr.com
D: Port to Logic Zoom LH7A40x SDK board(s)
N: Neil Russell
E: caret@c-side.com
D: Author of LiMon-1.4.2, which contributed some ideas
N: Travis B. Sawyer
E: travis.sawyer@sandburst.com
D: Support for AMCC PPC440GX, XES XPedite1000 440GX PrPMC board. AMCC 440gx Ref Platform (Ocotea)
N: Paolo Scaffardi
E: arsenio@tin.it
D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more
N: Robert Schwebel
E: r.schwebel@pengutronix.de
D: Support for csb226, logodl and innokom boards (PXA2xx)
N: Art Shipkowski
E: art@videon-central.com
D: Support for NetSilicon NS7520
N: Yasushi Shoji
E: yashi@atmark-techno.com
D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board
N: Kurt Stremerch
E: kurt@exys.be
D: Support for Exys XSEngine board
N: Andrea Scian
E: andrea.scian@dave-tech.it
D: Port to B2 board
W: www.dave-tech.it
N: Rob Taylor
E: robt@flyingpig.com
D: Port to MBX860T and Sandpoint8240
N: Erik Theisen
E: etheisen@mindspring.com
D: MBX8xx and many other patches
N: Jim Thompson
E: jim@musenki.com
D: Support for MUSENKI board
N: Rune Torgersen
E: <runet@innovsys.com>
D: Support for Motorola MPC8266ADS board
N: Greg Ungerer
E: greg.ungerer@opengear.com
D: Support for ks8695 CPU, and OpenGear cmXXXX boards
N: David Updegraff
E: dave@cray.com
D: Port to Cray L1 board; DHCP vendor extensions
N: Christian Vejlbo
E: christian.vejlbo@tellabs.com
D: FADS860T ethernet support
N: Robert Whaley
E: rwhaley@applieddata.net
D: Port to ARM PXA27x adsvix SBC
N: Martin Winistoerfer
E: martinwinistoerfer@gmx.ch
D: Port to MPC555/556 microcontrollers and support for cmi board
N: Ming-Len Wu
E: minglen_wu@techware.com.tw
D: Motorola MX1ADS board support
W: http://www.techware.com.tw/
N: Xianghua Xiao
E: x.xiao@motorola.com
D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.
N: John Zhan
E: zhanz@sinovee.com
D: Support for SinoVee Microsystems SC8xx SBC
N: Alex Zuepke
E: azu@sysgo.de
D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
W: www.elinos.com
N: James MacAulay
E: james.macaulay@amirix.com
D: Suppport for Amirix AP1000
W: www.amirix.com
MAINTAINERS
+539
View File
@@ -0,0 +1,539 @@
#########################################################################
# #
# Regular Maintainers for U-Boot board support: #
# #
# For any board without permanent maintainer, please contact #
# Wolfgang Denk <wd@denx.de> #
# and Cc: the <U-Boot-Users@lists.sourceforge.net> mailing lists. #
# #
# Note: lists sorted by Maintainer Name #
#########################################################################
#########################################################################
# PowerPC Systems: #
# #
# Maintainer Name, Email Address #
# Board CPU #
#########################################################################
Greg Allen <gallen@arlut.utexas.edu>
UTX8245 MPC8245
Pantelis Antoniou <panto@intracom.gr>
NETVIA MPC8xx
Reinhard Arlt <reinhard.arlt@esd-electronics.com>
cpci5200 MPC5200
pf5200 MPC5200
CPCI750 PPC750FX/GX
Yuli Barcohen <yuli@arabellasw.com>
Adder MPC87x/MPC852T
ep8248 MPC8248
ISPAN MPC8260
MPC8260ADS MPC826x/MPC827x/MPC8280
Rattler MPC8248
ZPC1900 MPC8265
Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
sacsng MPC8260
Oliver Brown <obrown@adventnetworks.com>
gw8260 MPC8260
Conn Clark <clark@esteem.com>
ESTEEM192E MPC8xx
Kári Davíðsson <kd@flaga.is>
FLAGADM MPC823
Torsten Demke <torsten.demke@fci.com>
eXalion MPC824x
Wolfgang Denk <wd@denx.de>
IceCube_5100 MGT5100
IceCube_5200 MPC5200
AMX860 MPC860
ETX094 MPC850
FPS850L MPC850
FPS860L MPC860
ICU862 MPC862
IP860 MPC860
IVML24 MPC860
IVML24_128 MPC860
IVML24_256 MPC860
IVMS8 MPC860
IVMS8_128 MPC860
IVMS8_256 MPC860
LANTEC MPC850
LWMON MPC823
NC650 MPC852
R360MPI MPC823
RMU MPC850
RRvision MPC823
SM850 MPC850
SPD823TS MPC823
TQM823L MPC823
TQM823L_LCD MPC823
TQM850L MPC850
TQM855L MPC855
TQM860L MPC860
TQM860L_FEC MPC860
c2mon MPC855
hermes MPC860
lwmon MPC823
pcu_e MPC855
CU824 MPC8240
Sandpoint8240 MPC8240
SL8245 MPC8245
ATC MPC8250
PM825 MPC8250
TQM8255 MPC8255
CPU86 MPC8260
PM826 MPC8260
TQM8260 MPC8260
P3G4 MPC7410
PCIPPC2 MPC750
PCIPPC6 MPC750
EXBITGEN PPC405GP
Jon Diekema <jon.diekema@smiths-aerospace.com>
sbc8260 MPC8260
Dave Ellis <DGE@sixnetio.com>
SXNI855T MPC8xx
Thomas Frieden <ThomasF@hyperion-entertainment.com>
AmigaOneG3SE MPC7xx
Matthias Fuchs <matthias.fuchs@esd-electronics.com>
ADCIOP IOP480 (PPC401)
APC405 PPC405GP
AR405 PPC405GP
ASH405 PPC405EP
CANBT PPC405CR
CPCI2DP PPC405GP
CPCI405 PPC405GP
CPCI4052 PPC405GP
CPCI405AB PPC405GP
CPCI405DT PPC405GP
CPCI440 PPC440GP
CPCIISER4 PPC405GP
DASA_SIM IOP480 (PPC401)
DP405 PPC405EP
DU405 PPC405GP
G2000 PPC405EP
HH405 PPC405EP
HUB405 PPC405EP
OCRTC PPC405GP
ORSG PPC405GP
PCI405 PPC405GP
PLU405 PPC405EP
PMC405 PPC405GP
VOH405 PPC405EP
VOM405 PPC405EP
WUH405 PPC405EP
CMS700 PPC405EP
Frank Gottschling <fgottschling@eltec.de>
MHPC MPC8xx
BAB7xx MPC740/MPC750
Wolfgang Grandegger <wg@denx.de>
CCM MPC855
PN62 MPC8240
IPHASE4539 MPC8260
SCM MPC8260
Howard Gray <mvsensor@matrix-vision.de>
MVS1 MPC823
Klaus Heydeck <heydeck@kieback-peter.de>
KUP4K MPC855
KUP4X MPC859
Murray Jensen <Murray.Jensen@csiro.au>
cogent_mpc8xx MPC8xx
cogent_mpc8260 MPC8260
hymod MPC8260
Brad Kemp <Brad.Kemp@seranoa.com>
ppmc8260 MPC8260
Sangmoon Kim <dogoil@etinsys.com>
debris MPC8245
Thomas Lange <thomas@corelatus.se>
GTH MPC860
The LEOX team <team@leox.org>
ELPT860 MPC860T
Nye Liu <nyet@zumanetworks.com>
ZUMA MPC7xx_74xx
Jon Loeliger <jdl@freescale.com>
MPC8540ADS MPC8540
MPC8560ADS MPC8560
MPC8541CDS MPC8541
MPC8555CDS MPC8555
Dan Malek <dan@embeddededge.com>
STxGP3 MPC85xx
STxXTc MPC8xx
Eran Man <eran@nbase.co.il>
EVB64260_750CX MPC750CX
Andrea "llandre" Marson <andrea.marson@dave-tech.it>
PPChameleonEVB PPC405EP
Reinhard Meyer <r.meyer@emk-elektronik.de>
TOP860 MPC860T
TOP5200 MPC5200
Tolunay Orkun <torkun@nextio.com>
csb272 PPC405GP
csb472 PPC405GP
John Otken <jotken@softadvances.com>
luan PPC440SP
Keith Outwater <Keith_Outwater@mvis.com>
GEN860T MPC860T
GEN860T_SC MPC860T
Frank Panno <fpanno@delphintech.com>
ep8260 MPC8260
Peter Pearse <peter.pearse@arm.com>
integratorcp All current ARM supplied &
supported core modules
- see http://www.arm.com
/products/DevTools
/Hardware_Platforms.html
versatile ARM926EJ-S
versatile ARM926EJ-S
Denis Peter <d.peter@mpl.ch>
MIP405 PPC4xx
PIP405 PPC4xx
Daniel Poirot <dan.poirot@windriver.com>
sbc8240 MPC8240
sbc405 PPC405GP
Stefan Roese <sr@denx.de>
uc100 MPC857
TQM85xx MPC8540/8541/8555/8560
bamboo PPC440EP
bunbinga PPC405EP
ebony PPC440GP
ocotea PPC440GX
p3p440 PPC440GP
sycamore PPC405GPr
walnut PPC405GP
yellowstone PPC440GR
yosemite PPC440EP
Yusdi Santoso <yusdi_santoso@adaptec.com>
HIDDEN_DRAGON MPC8241/MPC8245
Travis Sawyer (travis.sawyer@sandburst.com>
KAREF PPC440GX
METROBOX PPC440GX
XPEDITE1K PPC440GX
Peter De Schrijver <p2@mind.be>
ML2 PPC4xx
Erik Theisen <etheisen@mindspring.com>
W7OLMC PPC4xx
W7OLMG PPC4xx
Jim Thompson <jim@musenki.com>
MUSENKI MPC8245/8241
Sandpoint8245 MPC8245
Rune Torgersen <runet@innovsys.com>
MPC8266ADS MPC8266
Josef Wagner <Wagner@Microsys.de>
CPC45 MPC8245
PM520 MPC5200
Stephen Williams <steve@icarus.com>
JSE PPC405GPr
John Zhan <zhanz@sinovee.com>
svm_sc8xx MPC8xx
-------------------------------------------------------------------------
Unknown / orphaned boards:
ADS860 MPC8xx
FADS823 MPC8xx
FADS850SAR MPC8xx
FADS860T MPC8xx
GENIETV MPC8xx
IAD210 MPC8xx
MBX MPC8xx
MBX860T MPC8xx
NX823 MPC8xx
RPXClassic MPC8xx
RPXlite MPC8xx
CRAYL1 PPC4xx
ERIC PPC4xx
MOUSSE MPC824x
RPXsuper MPC8260
rsdproto MPC8260
EVB64260 MPC7xx_74xx
#########################################################################
# ARM Systems: #
# #
# Maintainer Name, Email Address #
# Board CPU #
#########################################################################
Rowel Atienza <rowel@diwalabs.com>
armadillo ARM720T
Rishi Bhattacharya <rishi@ti.com>
omap5912osk ARM926EJS
Cliff Brake <cliff.brake@gmail.com>
pxa255_idp xscale
Rick Bronson <rick@efn.org>
AT91RM9200DK at91rm9200
George G. Davis <gdavis@mvista.com>
assabet SA1100
gcplus SA1100
Thomas Elste <info@elste.org>
modnet50 ARM720T (NET+50)
Peter Figuli <peposh@etc.sk>
wepep250 xscale
Marius Gröger <mag@sysgo.de>
impa7 ARM720T (EP7211)
ep7312 ARM720T (EP7312)
Kshitij Gupta <kshitij@ti.com>
omap1510inn ARM925T
omap1610inn ARM926EJS
Kyle Harris <kharris@nexus-tech.net>
lubbock xscale
cradle xscale
ixdp425 xscale
Gary Jennejohn <gj@denx.de>
smdk2400 ARM920T
trab ARM920T
Nishant Kamat <nskamat@ti.com>
omap1610h2 ARM926EJS
Prakash Kumar <prakash@embedx.com>
cerf250 xscale
David Müller <d.mueller@elsoft.ch>
smdk2410 ARM920T
VCMA9 ARM920T
Rolf Offermanns <rof@sysgo.de>
shannon SA1100
Dave Peverley <dpeverley@mpc-data.co.uk>
omap730p2 ARM926EJS
Robert Schwebel <r.schwebel@pengutronix.de>
csb226 xscale
innokom xscale
Andrea Scian <andrea.scian@dave-tech.it>
B2 ARM7TDMI (S3C44B0X)
Greg Ungerer <greg.ungerer@opengear.com>
cm4008 ks8695p
cm4116 ks8695p
cm4148 ks8695p
Richard Woodruff <r-woodruff2@ti.com>
omap2420h4 ARM1136EJS
Alex Züpke <azu@sysgo.de>
lart SA1100
dnp1110 SA1110
#########################################################################
# x86 Systems: #
# #
# Maintainer Name, Email Address #
# Board CPU #
#########################################################################
Daniel Engström <daniel@omicron.se>
sc520_cdp x86
#########################################################################
# MIPS Systems: #
# #
# Maintainer Name, Email Address #
# Board CPU #
#########################################################################
Wolfgang Denk <wd@denx.de>
incaip MIPS32 4Kc
purple MIPS64 5Kc
Thomas Lange <thomas@corelatus.se>
dbau1x00 MIPS32 Au1000
#########################################################################
# Nios-32 Systems: #
# #
# Maintainer Name, Email Address #
# Board CPU #
#########################################################################
Stephan Linz <linz@li-pro.net>
DK1S10 Nios-32
ADNPESC1 Nios-32
Scott McNutt <smcnutt@psyent.com>
DK1C20 Nios-32
#########################################################################
# Nios-II Systems: #
# #
# Maintainer Name, Email Address #
# Board CPU #
#########################################################################
Scott McNutt <smcnutt@psyent.com>
PCI5441 Nios-II
PK1C20 Nios-II
#########################################################################
# MicroBlaze Systems: #
# #
# Maintainer Name, Email Address #
# Board CPU #
#########################################################################
Yasushi Shoji <yashi@atmark-techno.com>
SUZAKU MicroBlaze
#########################################################################
# Coldfire Systems: #
# #
# Maintainer Name, Email Address #
# Board CPU #
#########################################################################
Matthias Fuchs <matthias.fuchs@esd-electronics.com>
TASREG MCF5249
#########################################################################
# End of MAINTAINERS list #
#########################################################################
MAKEALL
Executable
+310
View File
@@ -0,0 +1,310 @@
#!/bin/sh
: ${JOBS:=}
if [ "${CROSS_COMPILE}" ] ; then
MAKE="make CROSS_COMPILE=${CROSS_COMPILE}"
else
MAKE=make
fi
[ -d LOG ] || mkdir LOG || exit 1
LIST=""
#########################################################################
## MPC5xx Systems
#########################################################################
LIST_5xx=" \
cmi_mpc5xx \
"
#########################################################################
## MPC5xxx Systems
#########################################################################
LIST_5xxx=" \
cpci5200 icecube_5100 icecube_5200 EVAL5200 \
pf5200 PM520 Total5100 Total5200 \
Total5200_Rev2 TQM5200_auto o2dnt \
"
#########################################################################
## MPC8xx Systems
#########################################################################
LIST_8xx=" \
Adder87x GENIETV MBX860T R360MPI \
AdderII GTH MHPC RBC823 \
ADS860 hermes MPC86xADS rmu \
AMX860 IAD210 MPC885ADS RPXClassic \
c2mon ICU862_100MHz MVS1 RPXlite \
CCM IP860 NETPHONE RPXlite_DW \
cogent_mpc8xx IVML24 NETTA RRvision \
ELPT860 IVML24_128 NETTA2 SM850 \
ESTEEM192E IVML24_256 NETTA_ISDN SPD823TS \
ETX094 IVMS8 NETVIA svm_sc8xx \
FADS823 IVMS8_128 NETVIA_V2 SXNI855T \
FADS850SAR IVMS8_256 NX823 TOP860 \
FADS860T KUP4K pcu_e TQM823L \
FLAGADM KUP4X QS823 TQM823L_LCD \
FPS850L LANTEC QS850 TQM850L \
GEN860T lwmon QS860T TQM855L \
GEN860T_SC MBX quantum TQM860L \
uc100 \
v37 \
"
#########################################################################
## PPC4xx Systems
#########################################################################
LIST_4xx=" \
ADCIOP AP1000 AR405 ASH405 \
bubinga CANBT CMS700 CPCI2DP \
CPCI405 CPCI4052 CPCI405AB CPCI405DT \
CPCI440 CPCIISER4 CRAYL1 csb272 \
csb472 DASA_SIM DP405 DU405 \
ebony ERIC EXBITGEN G2000 \
HH405 HUB405 JSE KAREF \
luan METROBOX MIP405 MIP405T \
ML2 ml300 ocotea OCRTC \
ORSG p3p440 PCI405 PIP405 \
PLU405 PMC405 PPChameleonEVB sbc405 \
VOH405 VOM405 W7OLMC W7OLMG \
walnut WUH405 XPEDITE1K yellowstone \
yosemite \
"
#########################################################################
## MPC8220 Systems
#########################################################################
LIST_8220=" \
Alaska8220 Yukon8220 \
"
#########################################################################
## MPC824x Systems
#########################################################################
LIST_824x=" \
A3000 barco BMW CPC45 \
CU824 debris eXalion HIDDEN_DRAGON \
MOUSSE MUSENKI MVBLUE OXC \
PN62 Sandpoint8240 Sandpoint8245 sbc8240 \
SL8245 utx8245 \
"
#########################################################################
## MPC8260 Systems (includes 8250, 8255 etc.)
#########################################################################
LIST_8260=" \
atc cogent_mpc8260 CPU86 CPU87 \
ep8248 ep8260 gw8260 hymod \
IPHASE4539 ISPAN MPC8260ADS MPC8266ADS \
MPC8272ADS PM826 PM828 ppmc8260 \
Rattler8248 RPXsuper rsdproto sacsng \
sbc8260 SCM TQM8260_AC TQM8260_AD \
TQM8260_AE ZPC1900 \
"
#########################################################################
## MPC83xx Systems (includes 8349, etc.)
#########################################################################
LIST_83xx=" \
MPC8349ADS TQM834x\
"
#########################################################################
## MPC85xx Systems (includes 8540, 8560 etc.)
#########################################################################
LIST_85xx=" \
MPC8540ADS MPC8540EVAL MPC8541CDS MPC8548CDS \
MPC8555CDS MPC8560ADS PM854 PM856 \
sbc8540 sbc8560 stxgp3 TQM8540 \
TQM8541 TQM8555 TQM8560 \
"
#########################################################################
## 74xx/7xx Systems
#########################################################################
LIST_74xx=" \
DB64360 DB64460 EVB64260 P3G4 \
PCIPPC2 PCIPPC6 ZUMA \
"
LIST_7xx=" \
BAB7xx CPCI750 ELPPC \
"
LIST_ppc="${LIST_5xx} ${LIST_5xxx} \
${LIST_8xx} \
${LIST_8220} ${LIST_824x} ${LIST_8260} \
${LIST_83xx} \
${LIST_85xx} \
${LIST_4xx} \
${LIST_74xx} ${LIST_7xx}"
#########################################################################
## StrongARM Systems
#########################################################################
LIST_SA="assabet dnp1110 gcplus lart shannon"
#########################################################################
## ARM7 Systems
#########################################################################
LIST_ARM7=" \
armadillo B2 ep7312 evb4510 \
impa7 integratorap ap7 ap720t \
modnet50 \
"
#########################################################################
## ARM9 Systems
#########################################################################
LIST_ARM9=" \
at91rm9200dk cmc_pu2 \
ap920t ap922_XA10 ap926ejs ap946es \
ap966 cp920t cp922_XA10 cp926ejs \
cp946es cp966 lpd7a400 mp2usb \
mx1ads mx1fs2 omap1510inn omap1610h2 \
omap1610inn omap730p2 scb9328 smdk2400 \
smdk2410 trab VCMA9 versatile \
versatileab versatilepb voiceblue
"
#########################################################################
## ARM10 Systems
#########################################################################
LIST_ARM10=" \
integratorcp cp1026 \
"
#########################################################################
## ARM11 Systems
#########################################################################
LIST_ARM11=" \
cp1136 omap2420h4 \
"
#########################################################################
## Xscale Systems
#########################################################################
LIST_pxa=" \
adsvix cerf250 cradle csb226 \
innokom lubbock pxa255_idp wepep250 \
xaeniax xm250 xsengine \
"
LIST_ixp="ixdp425"
LIST_arm=" \
${LIST_SA} \
${LIST_ARM7} ${LIST_ARM9} ${LIST_ARM10} ${LIST_ARM11} \
${LIST_pxa} ${LIST_ixp} \
"
#########################################################################
## MIPS Systems (default = big endian)
#########################################################################
LIST_mips4kc="incaip"
LIST_mips5kc="purple"
LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el"
LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}"
#########################################################################
## MIPS Systems (little endian)
#########################################################################
LIST_mips4kc_el=""
LIST_mips5kc_el=""
LIST_au1xx0_el="dbau1550_el"
LIST_mips_el="${LIST_mips4kc_el} ${LIST_mips5kc_el} ${LIST_au1xx0_el}"
#########################################################################
## i386 Systems
#########################################################################
LIST_I486="sc520_cdp sc520_spunk sc520_spunk_rel"
LIST_x86="${LIST_I486}"
#########################################################################
## NIOS Systems
#########################################################################
LIST_nios=" \
ADNPESC1 ADNPESC1_base_32 \
ADNPESC1_DNPEVA2_base_32 \
DK1C20 DK1C20_standard_32 \
DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \
"
#########################################################################
## Nios-II Systems
#########################################################################
LIST_nios2="PCI5441 PK1C20"
#########################################################################
## MicroBlaze Systems
#########################################################################
LIST_microblaze="suzaku"
#-----------------------------------------------------------------------
#----- for now, just run PPC by default -----
[ $# = 0 ] && set $LIST_ppc
#-----------------------------------------------------------------------
build_target() {
target=$1
${MAKE} distclean >/dev/null
${MAKE} ${target}_config
${MAKE} ${JOBS} all 2>&1 >LOG/$target.MAKELOG | tee LOG/$target.ERR
${CROSS_COMPILE:-ppc_8xx-}size u-boot | tee -a LOG/$target.MAKELOG
}
#-----------------------------------------------------------------------
for arg in $@
do
case "$arg" in
ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
arm|SA|ARM7|ARM9|ARM10|ARM11|pxa|ixp| \
microblaze| \
mips|mips_el| \
nios|nios2| \
x86|I486)
for target in `eval echo '$LIST_'${arg}`
do
build_target ${target}
done
;;
*) build_target ${arg}
;;
esac
done
Makefile
+1855
View File
File diff suppressed because it is too large Load Diff
README
+3498
View File
File diff suppressed because it is too large Load Diff
arm_config.mk
+24
View File
@@ -0,0 +1,24 @@
#
# (C) Copyright 2000-2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__
board/AtmarkTechno/suzaku/Makefile
+40
View File
@@ -0,0 +1,40 @@
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################
board/AtmarkTechno/suzaku/config.mk
+29
View File
@@ -0,0 +1,29 @@
#
# (C) Copyright 2004 Atmark Techno, Inc.
#
# Yasushi SHOJI <yashi@atmark-techno.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0x80F00000
PLATFORM_CPPFLAGS += -mno-xl-soft-mul
PLATFORM_CPPFLAGS += -mno-xl-soft-div
PLATFORM_CPPFLAGS += -mxl-barrel-shift
board/AtmarkTechno/suzaku/flash.c
+46
View File
@@ -0,0 +1,46 @@
/*
* (C) Copyright 2004 Atmark Techno, Inc.
*
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
unsigned long flash_init(void)
{
return 0;
}
void flash_print_info(flash_info_t *info)
{
}
int flash_erase(flash_info_t *info, int s_first, int s_last)
{
return 0;
}
int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
return 0;
}
board/AtmarkTechno/suzaku/suzaku.c
+32
View File
@@ -0,0 +1,32 @@
/*
* (C) Copyright 2004 Atmark Techno, Inc.
*
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* This is a board specific file. It's OK to include board specific
* header files */
#include <asm/suzaku.h>
void do_reset(void)
{
*((unsigned long *)(MICROBLAZE_SYSREG_BASE_ADDR)) = MICROBLAZE_SYSREG_RECONFIGURE;
}
board/AtmarkTechno/suzaku/u-boot.lds
+66
View File
@@ -0,0 +1,66 @@
/*
* (C) Copyright 2004 Atmark Techno, Inc.
*
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(microblaze)
ENTRY(_start)
SECTIONS
{
.text ALIGN(0x4):
{
__text_start = .;
cpu/microblaze/start.o (.text)
*(.text)
__text_end = .;
}
.rodata ALIGN(0x4):
{
__rodata_start = .;
*(.rodata)
__rodata_end = .;
}
.data ALIGN(0x4):
{
__data_start = .;
*(.data)
__data_end = .;
}
.u_boot_cmd ALIGN(0x4):
{
. = .;
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
.bss ALIGN(0x4):
{
__bss_start = .;
*(.bss)
__bss_start = .;
}
}
board/LEOX/elpt860/Makefile
+48
View File
@@ -0,0 +1,48 @@
#######################################################################
#
# Copyright (C) 2000, 2001, 2002, 2003
# The LEOX team <team@leox.org>, http://www.leox.org
#
# LEOX.org is about the development of free hardware and software resources
# for system on chip.
#
# Description: U-Boot port on the LEOX's ELPT860 CPU board
# ~~~~~~~~~~~
#
#######################################################################
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#######################################################################
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################
board/LEOX/elpt860/README.LEOX
+424
View File
@@ -0,0 +1,424 @@
=============================================================================
U-Boot port on the LEOX's ELPT860 CPU board
-------------------------------------------
LEOX.org is about the development of free hardware and software resources
for system on chip.
For more information, contact The LEOX team <team@leox.org>
References:
~~~~~~~~~~
1) Get the last stable release from denx.de:
o ftp://ftp.denx.de/pub/u-boot/u-boot-0.2.0.tar.bz2
2) Get the current CVS snapshot:
o cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login
o cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot
=============================================================================
The ELPT860 CPU board has the following features:
Processor: - MPC860T @ 50MHz
- PowerPC Core
- 65 MIPS
- Caches: D->4KB, I->4KB
- CPM: 4 SCCs, 2 SMCs
- Ethernet 10/100
- SPI, I2C, PCMCIA, Parallel
CPU board: - DRAM: 16 MB
- FLASH: 512 KB + (2 * 4 MB)
- NVRAM: 128 KB
- 1 Serial link
- 2 Ethernet 10 BaseT Channels
On power-up the processor jumps to the address of 0x02000100
Thus, U-Boot is configured to reside in flash starting at the address of
0x02001000. The environment space is located in NVRAM separately from
U-Boot, at the address of 0x03000000.
=============================================================================
U-Boot test results
=============================================================================
##################################################
# Operation on the serial console (SMC1)
##############################
U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
Board: ### No HW ID - assuming ELPT860
DRAM: 16 MB
FLASH: 512 kB
In: serial
Out: serial
Err: serial
Net: SCC ETHERNET
Type "run nfsboot" to mount root filesystem over NFS
Hit any key to stop autoboot: 0
LEOX_elpt860: help
askenv - get environment variables from stdin
autoscr - run script from memory
base - print or set address offset
bdinfo - print Board Info structure
bootm - boot application image from memory
bootp - boot image via network using BootP/TFTP protocol
bootd - boot default, i.e., run 'bootcmd'
cmp - memory compare
coninfo - print console devices and informations
cp - memory copy
crc32 - checksum calculation
echo - echo args to console
erase - erase FLASH memory
flinfo - print FLASH memory information
go - start application at address 'addr'
help - print online help
iminfo - print header information for application image
loadb - load binary file over serial line (kermit mode)
loads - load S-Record file over serial line
loop - infinite loop on address range
md - memory display
mm - memory modify (auto-incrementing)
mtest - simple RAM test
mw - memory write (fill)
nm - memory modify (constant address)
printenv- print environment variables
protect - enable or disable FLASH write protection
rarpboot- boot image via network using RARP/TFTP protocol
reset - Perform RESET of the CPU
run - run commands in an environment variable
saveenv - save environment variables to persistent storage
setenv - set environment variables
sleep - delay execution for some time
tftpboot- boot image via network using TFTP protocol
and env variables ipaddr and serverip
version - print monitor version
? - alias for 'help'
##################################################
# Environment Variables (CFG_ENV_IS_IN_NVRAM)
##############################
LEOX_elpt860: printenv
bootdelay=5
loads_echo=1
baudrate=9600
stdin=serial
stdout=serial
stderr=serial
ethaddr=00:03:ca:00:64:df
ipaddr=192.168.0.30
netmask=255.255.255.0
serverip=192.168.0.1
nfsserverip=192.168.0.1
preboot=echo;echo Type "run nfsboot" to mount root filesystem over NFS;echo
gatewayip=192.168.0.1
ramargs=setenv bootargs root=/dev/ram rw
rootargs=setenv rootpath /tftp/${ipaddr}
nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${nfsserverip}:${rootpath}
addip=setenv bootargs ${bootargs} ip=${ipaddr}:${nfsserverip}:${gatewayip}:${netmask}:${hostname}:eth0:
ramboot=tftp 400000 /home/leox/pMulti;run ramargs;bootm
nfsboot=tftp 400000 /home/leox/uImage;run rootargs;run nfsargs;run addip;bootm
bootcmd=run ramboot
clocks_in_mhz=1
Environment size: 730/16380 bytes
##################################################
# Flash Memory Information
##############################
LEOX_elpt860: flinfo
Bank # 1: AMD AM29F040 (4 Mbits)
Size: 512 KB in 8 Sectors
Sector Start Addresses:
02000000 (RO) 02010000 (RO) 02020000 (RO) 02030000 (RO) 02040000
02050000 02060000 02070000
##################################################
# Board Information Structure
##############################
LEOX_elpt860: bdinfo
memstart = 0x00000000
memsize = 0x01000000
flashstart = 0x02000000
flashsize = 0x00080000
flashoffset = 0x00030000
sramstart = 0x00000000
sramsize = 0x00000000
immr_base = 0xFF000000
bootflags = 0x00000001
intfreq = 50 MHz
busfreq = 50 MHz
ethaddr = 00:03:ca:00:64:df
IP addr = 192.168.0.30
baudrate = 9600 bps
##################################################
# Image Download and run over serial port
# hello_world (S-Record image)
# ===> 1) Enter "loads" command into U-Boot monitor
# ===> 2) From TeraTerm's bar menu, Select 'File/Send file...'
# Then select 'hello_world.srec' with the file browser
##############################
U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
Board: ### No HW ID - assuming ELPT860
DRAM: 16 MB
FLASH: 512 kB
In: serial
Out: serial
Err: serial
Net: SCC ETHERNET
Type "run nfsboot" to mount root filesystem over NFS
Hit any key to stop autoboot: 0
LEOX_elpt860: loads
## Ready for S-Record download ...
S804040004F3050154000501709905014C000501388D
## First Load Addr = 0x00040000
## Last Load Addr = 0x0005018B
## Total Size = 0x0001018C = 65932 Bytes
## Start Addr = 0x00040004
LEOX_elpt860: go 40004 This is a test !!!
## Starting application at 0x00040004 ...
Hello World
argc = 6
argv[0] = "40004"
argv[1] = "This"
argv[2] = "is"
argv[3] = "a"
argv[4] = "test"
argv[5] = "!!!"
argv[6] = "<NULL>"
Hit any key to exit ...
## Application terminated, rc = 0x0
##################################################
# Image download and run over ethernet interface
# Linux-2.4.4 (uImage) + Root filesystem mounted over NFS
##############################
U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
Board: ### No HW ID - assuming ELPT860
DRAM: 16 MB
FLASH: 512 kB
In: serial
Out: serial
Err: serial
Net: SCC ETHERNET
Type "run nfsboot" to mount root filesystem over NFS
Hit any key to stop autoboot: 0
LEOX_elpt860: run nfsboot
ARP broadcast 1
TFTP from server 192.168.0.1; our IP address is 192.168.0.30
Filename '/home/leox/uImage'.
Load address: 0x400000
Loading: #################################################################
#############################
done
Bytes transferred = 477294 (7486e hex)
## Booting image at 00400000 ...
Image Name: Linux-2.4.4
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 477230 Bytes = 466 kB = 0 MB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002
On node 0 totalpages: 4096
zone(0): 4096 pages.
zone(1): 0 pages.
zone(2): 0 pages.
Kernel command line: root=/dev/nfs rw nfsroot=192.168.0.1:/tftp/192.168.0.30 ip=192.168.0.30:192.168.0.1:192.168.0.1:255.255.255.0::eth0:
rtsched version <20010618.1050.24>
Decrementer Frequency: 3125000
Warning: real time clock seems stuck!
Calibrating delay loop... 49.76 BogoMIPS
Memory: 14720k available (928k kernel code, 384k data, 44k init, 0k highmem)
Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes)
Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes)
Page-cache hash table entries: 4096 (order: 2, 16384 bytes)
Inode-cache hash table entries: 1024 (order: 1, 8192 bytes)
POSIX conformance testing by UNIFIX
Linux NET4.0 for Linux 2.4
Based upon Swansea University Computer Society NET3.039
Starting kswapd v1.8
CPM UART driver version 0.03
ttyS0 on SMC1 at 0x0280, BRG1
block: queued sectors max/low 9701kB/3233kB, 64 slots per queue
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP
IP: routing cache hash table of 512 buckets, 4Kbytes
TCP: Hash tables configured (established 1024 bind 1024)
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
Looking up port of RPC 100003/2 on 192.168.0.1
Looking up port of RPC 100005/2 on 192.168.0.1
VFS: Mounted root (nfs filesystem).
Freeing unused kernel memory: 44k init
INIT: version 2.78 booting
Welcome to DENX Embedded Linux Environment
Press 'I' to enter interactive startup.
Mounting proc filesystem: [ OK ]
Configuring kernel parameters: [ OK ]
Cannot access the Hardware Clock via any known method.
Use the --debug option to see the details of our search for an access method.
Setting clock : Wed Dec 31 19:00:11 EST 1969 [ OK ]
Activating swap partitions: [ OK ]
Setting hostname 192.168.0.30: [ OK ]
Finding module dependencies:
[ OK ]
Checking filesystems
Checking all file systems.
[ OK ]
Mounting local filesystems: [ OK ]
Enabling swap space: [ OK ]
INIT: Entering runlevel: 3
Entering non-interactive startup
Starting system logger: [ OK ]
Starting kernel logger: [ OK ]
Starting xinetd: [ OK ]
192 login: root
Last login: Wed Dec 31 19:00:41 on ttyS0
bash-2.04#
##################################################
# Image download and run over ethernet interface
# Linux-2.4.4 + Root filesystem mounted from RAM (pMulti)
##############################
U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
Board: ### No HW ID - assuming ELPT860
DRAM: 16 MB
FLASH: 512 kB
In: serial
Out: serial
Err: serial
Net: SCC ETHERNET
Type "run nfsboot" to mount root filesystem over NFS
Hit any key to stop autoboot: 0
LEOX_elpt860: run ramboot
ARP broadcast 1
TFTP from server 192.168.0.1; our IP address is 192.168.0.30
Filename '/home/leox/pMulti'.
Load address: 0x400000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
#################################################################
########################################################
done
Bytes transferred = 1947816 (1db8a8 hex)
## Booting image at 00400000 ...
Image Name: linux-2.4.4-2002-03-21 Multiboot
Image Type: PowerPC Linux Multi-File Image (gzip compressed)
Data Size: 1947752 Bytes = 1902 kB = 1 MB
Load Address: 00000000
Entry Point: 00000000
Contents:
Image 0: 477230 Bytes = 466 kB = 0 MB
Image 1: 1470508 Bytes = 1436 kB = 1 MB
Verifying Checksum ... OK
Uncompressing Multi-File Image ... OK
Loading Ramdisk to 00e44000, end 00fab02c ... OK
Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002
On node 0 totalpages: 4096
zone(0): 4096 pages.
zone(1): 0 pages.
zone(2): 0 pages.
Kernel command line: root=/dev/ram rw
rtsched version <20010618.1050.24>
Decrementer Frequency: 3125000
Warning: real time clock seems stuck!
Calibrating delay loop... 49.76 BogoMIPS
Memory: 13280k available (928k kernel code, 384k data, 44k init, 0k highmem)
Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes)
Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes)
Page-cache hash table entries: 4096 (order: 2, 16384 bytes)
Inode-cache hash table entries: 1024 (order: 1, 8192 bytes)
POSIX conformance testing by UNIFIX
Linux NET4.0 for Linux 2.4
Based upon Swansea University Computer Society NET3.039
Starting kswapd v1.8
CPM UART driver version 0.03
ttyS0 on SMC1 at 0x0280, BRG1
block: queued sectors max/low 8741kB/2913kB, 64 slots per queue
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df
RAMDISK: Compressed image found at block 0
Freeing initrd memory: 1436k freed
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP
IP: routing cache hash table of 512 buckets, 4Kbytes
TCP: Hash tables configured (established 1024 bind 1024)
IP-Config: Incomplete network configuration information.
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
VFS: Mounted root (ext2 filesystem).
Freeing unused kernel memory: 44k iné
init started: BusyBox v0.60.2 (2002.07.01-12:06+0000) multi-call Configuring hostname
Configuring lo...
Configuring eth0...
Configuring Gateway...
Please press Enter to activate this console.
ELPT860 login: root
Password:
Welcome to Linux-2.4.4 for ELPT CPU board (MPC860T @ 50MHz)
a8888b.
d888888b.
8P"YP"Y88
_ _ 8|o||o|88
| | |_| 8' .88
| | _ ____ _ _ _ _ 8`._.' Y8.
| | | | _ \| | | |\ \/ / d/ `8b.
| |___ | | | | | |_| |/ \ .dP . Y8b.
|_____||_|_| |_|\____|\_/\_/ d8:' " `::88b.
d8" `Y88b
:8P ' :888
8a. : _a88P
._/"Yaa_ : .| 88P|
\ YP" `| 8P `.
/ \._____.d| .'
`--..__)888888P`._.'
login[21]: root login on `ttyS0'
BusyBox v0.60.3 (2002.07.20-10:39+0000) Built-in shell (ash)
Enter 'help' for a list of built-in commands.
root@ELPT860:~ #
board/LEOX/elpt860/config.mk
+36
View File
@@ -0,0 +1,36 @@
#######################################################################
#
# Copyright (C) 2000, 2001, 2002, 2003
# The LEOX team <team@leox.org>, http://www.leox.org
#
# LEOX.org is about the development of free hardware and software resources
# for system on chip.
#
# Description: U-Boot port on the LEOX's ELPT860 CPU board
# ~~~~~~~~~~~
#
#######################################################################
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#######################################################################
#
# ELPT860 board
#
TEXT_BASE = 0x02000000
#TEXT_BASE = 0x00FB0000
board/LEOX/elpt860/elpt860.c
+348
View File
@@ -0,0 +1,348 @@
/*
**=====================================================================
**
** Copyright (C) 2000, 2001, 2002, 2003
** The LEOX team <team@leox.org>, http://www.leox.org
**
** LEOX.org is about the development of free hardware and software resources
** for system on chip.
**
** Description: U-Boot port on the LEOX's ELPT860 CPU board
** ~~~~~~~~~~~
**
**=====================================================================
**
** This program is free software; you can redistribute it and/or
** modify it under the terms of the GNU General Public License as
** published by the Free Software Foundation; either version 2 of
** the License, or (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program; if not, write to the Free Software
** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
** MA 02111-1307 USA
**
**=====================================================================
*/
/*
** Note 1: In this file, you have to provide the following functions:
** ------
** int board_early_init_f(void)
** int checkboard(void)
** long int initdram(int board_type)
** called from 'board_init_f()' into 'common/board.c'
**
** void reset_phy(void)
** called from 'board_init_r()' into 'common/board.c'
*/
#include <common.h>
#include <mpc8xx.h>
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFFFFF
const uint init_sdram_table[] = {
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
0xFFFFFC04, /* last */
/*
* SDRAM Initialization (offset 5 in UPMA RAM)
*
* This is no UPM entry point. The following definition uses
* the remaining space to establish an initialization
* sequence, which is executed by a RUN command.
*
*/
0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, /* last */
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
};
const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
0xFF0FFC00, /* last */
/*
* SDRAM Initialization (offset 5 in UPMA RAM)
*
* This is no UPM entry point. The following definition uses
* the remaining space to establish an initialization
* sequence, which is executed by a RUN command.
*
*/
0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */
_NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
/*
* Refresh (Offset 30 in UPMA RAM)
*/
0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
/*
* Exception. (Offset 3c in UPMA RAM)
*/
0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */
};
/* ------------------------------------------------------------------------- */
#define CFG_PC4 0x0800
#define CFG_DS1 CFG_PC4
/*
* Very early board init code (fpga boot, etc.)
*/
int board_early_init_f (void)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
/*
* Light up the red led on ELPT860 pcb (DS1) (PCDAT)
*/
immr->im_ioport.iop_pcdat &= ~CFG_DS1; /* PCDAT (DS1 = 0) */
immr->im_ioport.iop_pcpar &= ~CFG_DS1; /* PCPAR (0=general purpose I/O) */
immr->im_ioport.iop_pcdir |= CFG_DS1; /* PCDIR (I/O: 0=input, 1=output) */
return (0); /* success */
}
/*
* Check Board Identity:
*
* Test ELPT860 ID string
*
* Return 1 if no second DRAM bank, otherwise returns 0
*/
int checkboard (void)
{
char *s = getenv ("serial#");
if (!s || strncmp (s, "ELPT860", 7))
printf ("### No HW ID - assuming ELPT860\n");
return (0); /* success */
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size8, size9;
long int size_b0 = 0;
/*
* This sequence initializes SDRAM chips on ELPT860 board
*/
upmconfig (UPMA, (uint *) init_sdram_table,
sizeof (init_sdram_table) / sizeof (uint));
memctl->memc_mptpr = 0x0200;
memctl->memc_mamr = 0x18002111;
memctl->memc_mar = 0x00000088;
memctl->memc_mcr = 0x80002000; /* CS1: SDRAM bank 0 */
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
/*
* Preliminary prescaler for refresh (depends on number of
* banks): This value is selected for four cycles every 62.4 us
* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
/*
* The following value is used as an address (i.e. opcode) for
* the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
* the port size is 32bit the SDRAM does NOT "see" the lower two
* address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
* MICRON SDRAMs:
* -> 0 00 010 0 010
* | | | | +- Burst Length = 4
* | | | +----- Burst Type = Sequential
* | | +------- CAS Latency = 2
* | +----------- Operating Mode = Standard
* +-------------- Write Burst Mode = Programmed Burst Length
*/
memctl->memc_mar = 0x00000088;
/*
* Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
* preliminary addresses - these have to be modified after the
* SDRAM size has been determined.
*/
memctl->memc_or1 = CFG_OR1_PRELIM;
memctl->memc_br1 = CFG_BR1_PRELIM;
memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay (200);
/* perform SDRAM initializsation sequence */
memctl->memc_mcr = 0x80002105; /* CS1: SDRAM bank 0 */
udelay (1);
memctl->memc_mcr = 0x80002230; /* CS1: SDRAM bank 0 - execute twice */
udelay (1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay (1000);
/*
* Check Bank 0 Memory Size for re-configuration
*
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL,
SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL,
SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
size_b0 = size9;
/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
} else { /* back to 8 columns */
size_b0 = size8;
memctl->memc_mamr = CFG_MAMR_8COL;
udelay (500);
/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
}
udelay (1000);
/*
* Adjust refresh rate depending on SDRAM type, both banks
* For types > 128 MBit leave it at the current (fast) rate
*/
if (size_b0 < 0x02000000) {
/* reduce to 15.6 us (62.4 us / quad) */
memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
udelay (1000);
}
/*
* Final mapping: map bigger bank first
*/
memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
{
unsigned long reg;
/* adjust refresh rate depending on SDRAM type, one bank */
reg = memctl->memc_mptpr;
reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
memctl->memc_mptpr = reg;
}
udelay (10000);
return (size_b0);
}
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int
dram_size (long int mamr_value, long int *base, long int maxsize)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
memctl->memc_mamr = mamr_value;
return (get_ram_size (base, maxsize));
}
/* ------------------------------------------------------------------------- */
#define CFG_PA1 0x4000
#define CFG_PA2 0x2000
#define CFG_LBKs (CFG_PA2 | CFG_PA1)
void reset_phy (void)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
/*
* Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
* and no AUI loopback
*/
immr->im_ioport.iop_padat &= ~CFG_LBKs; /* PADAT (LBK eth 1&2 = 0) */
immr->im_ioport.iop_papar &= ~CFG_LBKs; /* PAPAR (0=general purpose I/O) */
immr->im_ioport.iop_padir |= CFG_LBKs; /* PADIR (I/O: 0=input, 1=output) */
}
board/LEOX/elpt860/flash.c
+615
View File
@@ -0,0 +1,615 @@
/*
**=====================================================================
**
** Copyright (C) 2000, 2001, 2002, 2003
** The LEOX team <team@leox.org>, http://www.leox.org
**
** LEOX.org is about the development of free hardware and software resources
** for system on chip.
**
** Description: U-Boot port on the LEOX's ELPT860 CPU board
** ~~~~~~~~~~~
**
**=====================================================================
**
** This program is free software; you can redistribute it and/or
** modify it under the terms of the GNU General Public License as
** published by the Free Software Foundation; either version 2 of
** the License, or (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program; if not, write to the Free Software
** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
** MA 02111-1307 USA
**
**=====================================================================
*/
/*
** Note 1: In this file, you have to provide the following variable:
** ------
** flash_info_t flash_info[CFG_MAX_FLASH_BANKS]
** 'flash_info_t' structure is defined into 'include/flash.h'
** and defined as extern into 'common/cmd_flash.c'
**
** Note 2: In this file, you have to provide the following functions:
** ------
** unsigned long flash_init(void)
** called from 'board_init_r()' into 'common/board.c'
**
** void flash_print_info(flash_info_t *info)
** called from 'do_flinfo()' into 'common/cmd_flash.c'
**
** int flash_erase(flash_info_t *info,
** int s_first,
** int s_last)
** called from 'do_flerase()' & 'flash_sect_erase()' into 'common/cmd_flash.c'
**
** int write_buff (flash_info_t *info,
** uchar *src,
** ulong addr,
** ulong cnt)
** called from 'flash_write()' into 'common/cmd_flash.c'
*/
#include <common.h>
#include <mpc8xx.h>
#ifndef CFG_ENV_ADDR
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
#endif
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Internal Functions
*/
static void flash_get_offsets (ulong base, flash_info_t *info);
static ulong flash_get_size (volatile unsigned char *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static int write_byte (flash_info_t *info, ulong dest, uchar data);
/*-----------------------------------------------------------------------
*/
unsigned long
flash_init (void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long size_b0;
int i;
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
{
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size ((volatile unsigned char *)FLASH_BASE0_PRELIM,
&flash_info[0]);
if ( flash_info[0].flash_id == FLASH_UNKNOWN )
{
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
}
/* Remap FLASH according to real size */
memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V;
/* Re-do sizing to get full correct info */
size_b0 = flash_get_size ((volatile unsigned char *)CFG_FLASH_BASE,
&flash_info[0]);
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len-1,
&flash_info[0]);
#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE-1,
&flash_info[0]);
#endif
flash_info[0].size = size_b0;
return (size_b0);
}
/*-----------------------------------------------------------------------
*/
static void
flash_get_offsets (ulong base,
flash_info_t *info)
{
int i;
#define SECTOR_64KB 0x00010000
/* set up sector start adress table */
for (i = 0; i < info->sector_count; i++)
{
info->start[i] = base + (i * SECTOR_64KB);
}
}
/*-----------------------------------------------------------------------
*/
void
flash_print_info (flash_info_t *info)
{
int i;
if ( info->flash_id == FLASH_UNKNOWN )
{
printf ("missing or unknown FLASH type\n");
return;
}
switch ( info->flash_id & FLASH_VENDMASK )
{
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_STM: printf ("STM (Thomson) "); break;
default: printf ("Unknown Vendor "); break;
}
switch ( info->flash_id & FLASH_TYPEMASK )
{
case FLASH_AM040: printf ("AM29F040 (4 Mbits)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i)
{
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
return;
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong
flash_get_size (volatile unsigned char *addr,
flash_info_t *info)
{
short i;
uchar value;
ulong base = (ulong)addr;
/* Write auto select command: read Manufacturer ID */
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
addr[0x0555] = 0x90;
value = addr[0];
switch ( value )
{
/* case AMD_MANUFACT: */
case 0x01:
info->flash_id = FLASH_MAN_AMD;
break;
/* case FUJ_MANUFACT: */
case 0x04:
info->flash_id = FLASH_MAN_FUJ;
break;
/* case STM_MANUFACT: */
case 0x20:
info->flash_id = FLASH_MAN_STM;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
value = addr[1]; /* device ID */
switch ( value )
{
case STM_ID_F040B:
case AMD_ID_F040B:
info->flash_id += FLASH_AM040; /* 4 Mbits = 512k * 8 */
info->sector_count = 8;
info->size = 0x00080000;
break;
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
/* set up sector start adress table */
for (i = 0; i < info->sector_count; i++)
{
info->start[i] = base + (i * 0x00010000);
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++)
{
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr = (volatile unsigned char *)(info->start[i]);
info->protect[i] = addr[2] & 1;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if ( info->flash_id != FLASH_UNKNOWN )
{
addr = (volatile unsigned char *)info->start[0];
*addr = 0xF0; /* reset bank */
}
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int
flash_erase (flash_info_t *info,
int s_first,
int s_last)
{
volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
if ( (s_first < 0) || (s_first > s_last) )
{
if ( info->flash_id == FLASH_UNKNOWN )
{
printf ("- missing\n");
}
else
{
printf ("- no sectors to erase\n");
}
return ( 1 );
}
if ( (info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP) )
{
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return ( 1 );
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect)
{
if ( info->protect[sect] )
{
prot++;
}
}
if ( prot )
{
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
}
else
{
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
addr[0x0555] = 0x80;
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++)
{
if (info->protect[sect] == 0) /* not protected */
{
addr = (volatile unsigned char *)(info->start[sect]);
addr[0] = 0x30;
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if ( flag )
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if ( l_sect < 0 )
goto DONE;
start = get_timer (0);
last = start;
addr = (volatile unsigned char *)(info->start[l_sect]);
while ( (addr[0] & 0x80) != 0x80 )
{
if ( (now = get_timer(start)) > CFG_FLASH_ERASE_TOUT )
{
printf ("Timeout\n");
return ( 1 );
}
/* show that we're waiting */
if ( (now - last) > 1000 ) /* every second */
{
putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (volatile unsigned char *)info->start[0];
addr[0] = 0xF0; /* reset bank */
printf (" done\n");
return ( 0 );
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int
write_buff (flash_info_t *info,
uchar *src,
ulong addr,
ulong cnt)
{
ulong cp, wp, data;
uchar bdata;
int i, l, rc;
if ( (info->flash_id & FLASH_TYPEMASK) == FLASH_AM040 )
{
/* Width of the data bus: 8 bits */
wp = addr;
while ( cnt )
{
bdata = *src++;
if ( (rc = write_byte(info, wp, bdata)) != 0 )
{
return (rc);
}
++wp;
--cnt;
}
return ( 0 );
}
else
{
/* Width of the data bus: 32 bits */
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ( (l = addr - wp) != 0 )
{
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp)
{
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i)
{
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp)
{
data = (data << 8) | (*(uchar *)cp);
}
if ( (rc = write_word(info, wp, data)) != 0 )
{
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while ( cnt >= 4 )
{
data = 0;
for (i=0; i<4; ++i)
{
data = (data << 8) | *src++;
}
if ( (rc = write_word(info, wp, data)) != 0 )
{
return (rc);
}
wp += 4;
cnt -= 4;
}
if ( cnt == 0 )
{
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp)
{
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp)
{
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int
write_word (flash_info_t *info,
ulong dest,
ulong data)
{
vu_long *addr = (vu_long*)(info->start[0]);
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ( (*((vu_long *)dest) & data) != data )
{
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
addr[0x0555] = 0x00A000A0;
*((vu_long *)dest) = data;
/* re-enable interrupts if necessary */
if ( flag )
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) )
{
if ( get_timer(start) > CFG_FLASH_WRITE_TOUT )
{
return (1);
}
}
return (0);
}
/*-----------------------------------------------------------------------
* Write a byte to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int
write_byte (flash_info_t *info,
ulong dest,
uchar data)
{
volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ( (*((volatile unsigned char *)dest) & data) != data )
{
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
addr[0x0555] = 0xA0;
*((volatile unsigned char *)dest) = data;
/* re-enable interrupts if necessary */
if ( flag )
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) )
{
if ( get_timer(start) > CFG_FLASH_WRITE_TOUT )
{
return (1);
}
}
return (0);
}
/*-----------------------------------------------------------------------
*/
board/LEOX/elpt860/u-boot.lds
+154
View File
@@ -0,0 +1,154 @@
/*
**=====================================================================
**
** Copyright (C) 2000, 2001, 2002, 2003
** The LEOX team <team@leox.org>, http://www.leox.org
**
** LEOX.org is about the development of free hardware and software resources
** for system on chip.
**
** Description: U-Boot port on the LEOX's ELPT860 CPU board
** ~~~~~~~~~~~
**
**=====================================================================
**
** This program is free software; you can redistribute it and/or
** modify it under the terms of the GNU General Public License as
** published by the Free Software Foundation; either version 2 of
** the License, or (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program; if not, write to the Free Software
** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
** MA 02111-1307 USA
**
**=====================================================================
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib_ppc/ppcstring.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
lib_generic/string.o (.text)
lib_ppc/cache.o (.text)
lib_ppc/extable.o (.text)
lib_ppc/time.o (.text)
lib_ppc/ticks.o (.text)
. = env_offset;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}
board/LEOX/elpt860/u-boot.lds.debug
+141
View File
@@ -0,0 +1,141 @@
/*
**=====================================================================
**
** Copyright (C) 2000, 2001, 2002, 2003
** The LEOX team <team@leox.org>, http://www.leox.org
**
** LEOX.org is about the development of free hardware and software resources
** for system on chip.
**
** Description: U-Boot port on the LEOX's ELPT860 CPU board
** ~~~~~~~~~~~
**
**=====================================================================
**
** This program is free software; you can redistribute it and/or
** modify it under the terms of the GNU General Public License as
** published by the Free Software Foundation; either version 2 of
** the License, or (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program; if not, write to the Free Software
** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
** MA 02111-1307 USA
**
**=====================================================================
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
. = env_offset;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}
board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
+114
View File
@@ -0,0 +1,114 @@
/*
* (C) Copyright 2002
* Hyperion Entertainment, ThomasF@hyperion-entertainment.com
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include "articiaS.h"
#include "memio.h"
#include "via686.h"
__asm(" .globl send_kb \n
send_kb: \n
lis r9, 0xfe00 \n
\n
li r4, 0x10 # retries \n
mtctr r4 \n
\n
idle: \n
lbz r4, 0x64(r9) \n
andi. r4, r4, 0x02 \n
bne idle \n
\n
ready: \n
stb r3, 0x60(r9) \n
\n
check: \n
lbz r4, 0x64(r9) \n
andi. r4, r4, 0x01 \n
beq check \n
\n
lbz r4, 0x60(r9) \n
cmpwi r4, 0xfa \n
beq done \n
\n
bdnz idle \n
\n
li r3, 0 \n
blr \n
\n
done: \n
li r3, 1 \n
blr \n
\n
.globl test_kb \n
test_kb: \n
mflr r10 \n
li r3, 0xed \n
bl send_kb \n
li r3, 0x01 \n
bl send_kb \n
mtlr r10 \n
blr \n
");
int checkboard (void)
{
printf ("Board: AmigaOneG3SE\n");
return 0;
}
long initdram (int board_type)
{
return articiaS_ram_init ();
}
void after_reloc (ulong dest_addr, gd_t *gd)
{
/* HJF: DECLARE_GLOBAL_DATA_PTR; */
board_init_r (gd, dest_addr);
}
int misc_init_r (void)
{
extern pci_dev_t video_dev;
extern void drv_video_init (void);
if (video_dev != ~0)
drv_video_init ();
return (0);
}
void pci_init_board (void)
{
#ifndef CONFIG_RAMBOOT
articiaS_pci_init ();
#endif
}
board/MAI/AmigaOneG3SE/Makefile
+56
View File
@@ -0,0 +1,56 @@
#
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
COBJS = $(BOARD).o articiaS.o flash.o serial.o smbus.o articiaS_pci.o \
via686.o i8259.o ../bios_emulator/x86interface.o \
../bios_emulator/bios.o ../bios_emulator/glue.o \
interrupts.o ps2kbd.o video.o usb_uhci.o enet.o \
../menu/cmd_menu.o cmd_boota.o nvram.o
AOBJS = board_asm_init.o memio.o
OBJS = $(COBJS) $(AOBJS)
EMUDIR = ../bios_emulator/scitech/src/x86emu/
EMUOBJ = $(EMUDIR)decode.o $(EMUDIR)ops2.o $(EMUDIR)fpu.o $(EMUDIR)prim_ops.o \
$(EMUDIR)ops.o $(EMUDIR)sys.o
EMUSRC = $(EMUOBJ:.o=.c)
$(LIB): .depend $(OBJS) $(EMUSRC)
make libx86emu.a -C ../bios_emulator/scitech/src/x86emu -f makefile.uboot CROSS_COMPILE=$(CROSS_COMPILE)
-rm $(LIB)
$(AR) crv $@ $(OBJS) $(EMUOBJ)
#########################################################################
.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
$(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
sinclude .depend
#########################################################################
board/MAI/AmigaOneG3SE/articiaS.c
+705
View File
@@ -0,0 +1,705 @@
/*
* (C) Copyright 2002
* Hyperion Entertainment, ThomasF@hyperion-entertainment.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include "memio.h"
#include "articiaS.h"
#include "smbus.h"
#include "via686.h"
#undef DEBUG
struct dimm_bank {
uint8 used; /* Bank is populated */
uint32 rows; /* Number of row addresses */
uint32 columns; /* Number of column addresses */
uint8 registered; /* SIMM is registered */
uint8 ecc; /* SIMM has ecc */
uint8 burst_len; /* Supported burst lengths */
uint32 cas_lat; /* Supported CAS latencies */
uint32 cas_used; /* CAS to use (not set by user) */
uint32 trcd; /* RAS to CAS latency */
uint32 trp; /* Precharge latency */
uint32 tclk_hi; /* SDRAM cycle time (highest CAS latency) */
uint32 tclk_2hi; /* SDRAM second highest CAS latency */
uint32 size; /* Size of bank in bytes */
uint8 auto_refresh; /* Module supports auto refresh */
uint32 refresh_time; /* Refresh time (in ns) */
};
/*
** Based in part on the evb64260 code
*/
/*
* translate ns.ns/10 coding of SPD timing values
* into 10 ps unit values
*/
static inline unsigned short NS10to10PS (unsigned char spd_byte)
{
unsigned short ns, ns10;
/* isolate upper nibble */
ns = (spd_byte >> 4) & 0x0F;
/* isolate lower nibble */
ns10 = (spd_byte & 0x0F);
return (ns * 100 + ns10 * 10);
}
/*
* translate ns coding of SPD timing values
* into 10 ps unit values
*/
static inline unsigned short NSto10PS (unsigned char spd_byte)
{
return (spd_byte * 100);
}
long detect_sdram (uint8 * rom, int dimmNum, struct dimm_bank *banks)
{
DECLARE_GLOBAL_DATA_PTR;
int dimm_address = (dimmNum == 0) ? SM_DIMM0_ADDR : SM_DIMM1_ADDR;
uint32 busclock = gd->bus_clk;
uint32 memclock = busclock;
uint32 tmemclock = 1000000000 / (memclock / 100);
uint32 datawidth;
if (sm_get_data (rom, dimm_address) == 0) {
/* Nothing in slot, make both banks empty */
debug ("Slot %d: vacant\n", dimmNum);
banks[0].used = 0;
banks[1].used = 0;
return 0;
}
if (rom[2] != 0x04) {
debug ("Slot %d: No SDRAM\n", dimmNum);
banks[0].used = 0;
banks[1].used = 0;
return 0;
}
/* Determine number of banks/rows */
if (rom[5] == 1) {
banks[0].used = 1;
banks[1].used = 0;
} else {
banks[0].used = 1;
banks[1].used = 1;
}
/* Determine number of row addresses */
if (rom[3] & 0xf0) {
/* Different banks sizes */
banks[0].rows = rom[3] & 0x0f;
banks[1].rows = (rom[3] & 0xf0) >> 4;
} else {
/* Equal sized banks */
banks[0].rows = rom[3] & 0x0f;
banks[1].rows = banks[0].rows;
}
/* Determine number of column addresses */
if (rom[4] & 0xf0) {
/* Different bank sizes */
banks[0].columns = rom[4] & 0x0f;
banks[1].columns = (rom[4] & 0xf0) >> 4;
} else {
banks[0].columns = rom[4] & 0x0f;
banks[1].columns = banks[0].columns;
}
/* Check Jedec revision, and modify row/column accordingly */
if (rom[62] > 0x10) {
if (banks[0].rows <= 3)
banks[0].rows += 15;
if (banks[1].rows <= 3)
banks[1].rows += 15;
if (banks[0].columns <= 3)
banks[0].columns += 15;
if (banks[0].columns <= 3)
banks[0].columns += 15;
}
/* Check registered/unregisterd */
if (rom[21] & 0x12) {
banks[0].registered = 1;
banks[1].registered = 1;
} else {
banks[0].registered = 0;
banks[1].registered = 0;
}
#ifdef CONFIG_ECC
/* Check parity/ECC */
banks[0].ecc = (rom[11] == 0x02);
banks[1].ecc = (rom[11] == 0x02);
#endif
/* Find burst lengths supported */
banks[0].burst_len = rom[16] & 0x8f;
banks[1].burst_len = rom[16] & 0x8f;
/* Find possible cas latencies */
banks[0].cas_lat = rom[18] & 0x7F;
banks[1].cas_lat = rom[18] & 0x7F;
/* RAS/CAS latency */
banks[0].trcd = (NSto10PS (rom[29]) + (tmemclock - 1)) / tmemclock;
banks[1].trcd = (NSto10PS (rom[29]) + (tmemclock - 1)) / tmemclock;
/* Precharge latency */
banks[0].trp = (NSto10PS (rom[27]) + (tmemclock - 1)) / tmemclock;
banks[1].trp = (NSto10PS (rom[27]) + (tmemclock - 1)) / tmemclock;
/* highest CAS latency */
banks[0].tclk_hi = NS10to10PS (rom[9]);
banks[1].tclk_hi = NS10to10PS (rom[9]);
/* second highest CAS latency */
banks[0].tclk_2hi = NS10to10PS (rom[23]);
banks[1].tclk_2hi = NS10to10PS (rom[23]);
/* bank sizes */
datawidth = rom[13] & 0x7f;
banks[0].size =
(1L << (banks[0].rows + banks[0].columns)) *
/* FIXME datawidth */ 8 * rom[17];
if (rom[13] & 0x80)
banks[1].size = 2 * banks[0].size;
else
banks[1].size = (1L << (banks[1].rows + banks[1].columns)) *
/* FIXME datawidth */ 8 * rom[17];
/* Refresh */
if (rom[12] & 0x80) {
banks[0].auto_refresh = 1;
banks[1].auto_refresh = 1;
} else {
banks[0].auto_refresh = 0;
banks[1].auto_refresh = 0;
}
switch (rom[12] & 0x7f) {
case 0:
banks[0].refresh_time = (1562500 + (tmemclock - 1)) / tmemclock;
banks[1].refresh_time = (1562500 + (tmemclock - 1)) / tmemclock;
break;
case 1:
banks[0].refresh_time = (390600 + (tmemclock - 1)) / tmemclock;
banks[1].refresh_time = (390600 + (tmemclock - 1)) / tmemclock;
break;
case 2:
banks[0].refresh_time = (781200 + (tmemclock - 1)) / tmemclock;
banks[1].refresh_time = (781200 + (tmemclock - 1)) / tmemclock;
break;
case 3:
banks[0].refresh_time = (3125000 + (tmemclock - 1)) / tmemclock;
banks[1].refresh_time = (3125000 + (tmemclock - 1)) / tmemclock;
break;
case 4:
banks[0].refresh_time = (6250000 + (tmemclock - 1)) / tmemclock;
banks[1].refresh_time = (6250000 + (tmemclock - 1)) / tmemclock;
break;
case 5:
banks[0].refresh_time = (12500000 + (tmemclock - 1)) / tmemclock;
banks[1].refresh_time = (12500000 + (tmemclock - 1)) / tmemclock;
break;
default:
banks[0].refresh_time = 0x100; /* Default of Articia S */
banks[1].refresh_time = 0x100;
break;
}
#ifdef DEBUG
printf ("\nInformation for SIMM bank %ld:\n", dimmNum);
printf ("Number of banks: %ld\n", banks[0].used + banks[1].used);
printf ("Number of row addresses: %ld\n", banks[0].rows);
printf ("Number of coumns addresses: %ld\n", banks[0].columns);
printf ("SIMM is %sregistered\n",
banks[0].registered == 0 ? "not " : "");
#ifdef CONFIG_ECC
printf ("SIMM %s ECC\n",
banks[0].ecc == 1 ? "supports" : "doesn't support");
#endif
printf ("Supported burst lenghts: %s %s %s %s %s\n",
banks[0].burst_len & 0x08 ? "8" : " ",
banks[0].burst_len & 0x04 ? "4" : " ",
banks[0].burst_len & 0x02 ? "2" : " ",
banks[0].burst_len & 0x01 ? "1" : " ",
banks[0].burst_len & 0x80 ? "PAGE" : " ");
printf ("Supported CAS latencies: %s %s %s\n",
banks[0].cas_lat & 0x04 ? "CAS 3" : " ",
banks[0].cas_lat & 0x02 ? "CAS 2" : " ",
banks[0].cas_lat & 0x01 ? "CAS 1" : " ");
printf ("RAS to CAS latency: %ld\n", banks[0].trcd);
printf ("Precharge latency: %ld\n", banks[0].trp);
printf ("SDRAM highest CAS latency: %ld\n", banks[0].tclk_hi);
printf ("SDRAM 2nd highest CAS latency: %ld\n", banks[0].tclk_2hi);
printf ("SDRAM data width: %ld\n", datawidth);
printf ("Auto Refresh %ssupported\n",
banks[0].auto_refresh ? "" : "not ");
printf ("Refresh time: %ld clocks\n", banks[0].refresh_time);
if (banks[0].used)
printf ("Bank 0 size: %ld MB\n", banks[0].size / 1024 / 1024);
if (banks[1].used)
printf ("Bank 1 size: %ld MB\n", banks[1].size / 1024 / 1024);
printf ("\n");
#endif
sm_term ();
return 1;
}
void select_cas (struct dimm_bank *banks, uint8 fast)
{
if (!banks[0].used) {
banks[0].cas_used = 0;
banks[0].cas_used = 0;
return;
}
if (fast) {
/* Search for fast CAS */
uint32 i;
uint32 c = 0x01;
for (i = 1; i < 5; i++) {
if (banks[0].cas_lat & c) {
banks[0].cas_used = i;
banks[1].cas_used = i;
debug ("Using CAS %d (fast)\n", i);
return;
}
c <<= 1;
}
/* Default to CAS 3 */
banks[0].cas_used = 3;
banks[1].cas_used = 3;
debug ("Using CAS 3 (fast)\n");
return;
} else {
/* Search for slow cas */
uint32 i;
uint32 c = 0x08;
for (i = 4; i > 1; i--) {
if (banks[0].cas_lat & c) {
banks[0].cas_used = i;
banks[1].cas_used = i;
debug ("Using CAS %d (slow)\n", i);
return;
}
c >>= 1;
}
/* Default to CAS 3 */
banks[0].cas_used = 3;
banks[1].cas_used = 3;
debug ("Using CAS 3 (slow)\n");
return;
}
banks[0].cas_used = 3;
banks[1].cas_used = 3;
debug ("Using CAS 3\n");
return;
}
uint32 get_reg_setting (uint32 banks, uint32 rows, uint32 columns, uint32 size)
{
uint32 i;
struct RowColumnSize {
uint32 banks;
uint32 rows;
uint32 columns;
uint32 size;
uint32 register_value;
};
struct RowColumnSize rcs_map[] = {
/* Sbk Radr Cadr MB Value */
{1, 11, 8, 8, 0x00840f00},
{1, 11, 9, 16, 0x00925f00},
{1, 11, 10, 32, 0x00a64f00},
{2, 12, 8, 32, 0x00c55f00},
{2, 12, 9, 64, 0x00d66f00},
{2, 12, 10, 128, 0x00e77f00},
{2, 12, 11, 256, 0x00ff8f00},
{2, 13, 11, 512, 0x00ff9f00},
{0, 0, 0, 0, 0x00000000}
};
i = 0;
while (rcs_map[i].banks != 0) {
if (rows == rcs_map[i].rows
&& columns == rcs_map[i].columns
&& (size / 1024 / 1024) == rcs_map[i].size)
return rcs_map[i].register_value;
i++;
}
return 0;
}
uint32 burst_to_len (uint32 support)
{
if (support & 0x80)
return 0x7;
else if (support & 0x8)
return 0x3;
else if (support & 0x4)
return 0x2;
else if (support & 0x2)
return 0x1;
else if (support & 0x1)
return 0x0;
return 0;
}
long articiaS_ram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
register uint32 i;
register uint32 value1;
register uint32 value2;
uint8 rom[128];
uint32 burst_len;
uint32 burst_support;
uint32 total_ram = 0;
struct dimm_bank banks[4]; /* FIXME: Move to initram */
uint32 busclock = gd->bus_clk;
uint32 memclock = busclock;
uint32 reg32;
uint32 refresh_clocks;
uint8 auto_refresh;
memset (banks, 0, sizeof (struct dimm_bank) * 4);
detect_sdram (rom, 0, &banks[0]);
detect_sdram (rom, 1, &banks[2]);
for (i = 0; i < 4; i++) {
total_ram = total_ram + (banks[i].used * banks[i].size);
}
pci_write_cfg_long (0, 0, GLOBALINFO0, 0x117430c0);
pci_write_cfg_long (0, 0, HBUSACR0, 0x1f0100b0);
pci_write_cfg_long (0, 0, SRAM_CR, 0x00f12000); /* Note: Might also try 0x00f10000 (original: 0x00f12000) */
pci_write_cfg_byte (0, 0, DRAM_RAS_CTL0, 0x3f);
pci_write_cfg_byte (0, 0, DRAM_RAS_CTL1, 0x00); /* was: 0x04); */
pci_write_cfg_word (0, 0, DRAM_ECC0, 0x2020); /* was: 0x2400); No ECC yet */
/* FIXME: Move this stuff to seperate function, like setup_dimm_bank */
if (banks[0].used) {
value1 = get_reg_setting (banks[0].used + banks[1].used,
banks[0].rows, banks[0].columns,
banks[0].size);
} else {
value1 = 0;
}
if (banks[1].used) {
value2 = get_reg_setting (banks[0].used + banks[1].used,
banks[1].rows, banks[1].columns,
banks[1].size);
} else {
value2 = 0;
}
pci_write_cfg_long (0, 0, DIMM0_B0_SCR0, value1);
pci_write_cfg_long (0, 0, DIMM0_B1_SCR0, value2);
debug ("DIMM0_B0_SCR0 = 0x%08x\n", value1);
debug ("DIMM0_B1_SCR0 = 0x%08x\n", value2);
if (banks[2].used) {
value1 = get_reg_setting (banks[2].used + banks[3].used,
banks[2].rows, banks[2].columns,
banks[2].size);
} else {
value1 = 0;
}
if (banks[3].used) {
value2 = get_reg_setting (banks[2].used + banks[3].used,
banks[3].rows, banks[3].columns,
banks[3].size);
} else {
value2 = 0;
}
pci_write_cfg_long (0, 0, DIMM1_B2_SCR0, value1);
pci_write_cfg_long (0, 0, DIMM1_B3_SCR0, value2);
debug ("DIMM0_B2_SCR0 = 0x%08x\n", value1);
debug ("DIMM0_B3_SCR0 = 0x%08x\n", value2);
pci_write_cfg_long (0, 0, DIMM2_B4_SCR0, 0);
pci_write_cfg_long (0, 0, DIMM2_B5_SCR0, 0);
pci_write_cfg_long (0, 0, DIMM3_B6_SCR0, 0);
pci_write_cfg_long (0, 0, DIMM3_B7_SCR0, 0);
/* Determine timing */
select_cas (&banks[0], 0);
select_cas (&banks[2], 0);
/* FIXME: What about write recovery */
/* Auto refresh Precharge */
#if 0
reg32 = (0x3 << 13) | (0x7 << 10) | ((banks[0].trp - 2) << 8) |
/* Write recovery CAS Latency */
(0x1 << 6) | (banks[0].cas_used << 4) |
/* RAS/CAS latency */
((banks[0].trcd - 1) << 0);
reg32 |= ((0x3 << 13) | (0x7 << 10) | ((banks[2].trp - 2) << 8) |
(0x1 << 6) | (banks[2].cas_used << 4) |
((banks[2].trcd - 1) << 0)) << 16;
#else
if (100000000 == gd->bus_clk)
reg32 = 0x71737173;
else
reg32 = 0x69736973;
#endif
pci_write_cfg_long (0, 0, DIMM0_TCR0, reg32);
debug ("DIMM0_TCR0 = 0x%08x\n", reg32);
/* Write default in DIMM2/3 (not used on A1) */
pci_write_cfg_long (0, 0, DIMM2_TCR0, 0x7d737d73);
/* Determine buffered/unbuffered mode for each SIMM. Uses first bank as reference (second, if present, uses the same) */
reg32 = pci_read_cfg_long (0, 0, DRAM_GCR0);
reg32 &= 0xFF00FFFF;
#if 0
if (banks[0].used && banks[0].registered)
reg32 |= 0x1 << 16;
if (banks[2].used && banks[2].registered)
reg32 |= 0x1 << 18;
#else
if (banks[0].registered || banks[2].registered)
reg32 |= 0x55 << 16;
#endif
pci_write_cfg_long (0, 0, DRAM_GCR0, reg32);
debug ("DRAM_GCR0 = 0x%08x\n", reg32);
/* Determine refresh */
refresh_clocks = 0xffffffff;
auto_refresh = 1;
for (i = 0; i < 4; i++) {
if (banks[i].used) {
if (banks[i].auto_refresh == 0)
auto_refresh = 0;
if (banks[i].refresh_time < refresh_clocks)
refresh_clocks = banks[i].refresh_time;
}
}
#if 1
/* It seems this is suggested by the ArticiaS data book */
if (100000000 == gd->bus_clk)
refresh_clocks = 1561;
else
refresh_clocks = 2083;
#endif
debug ("Refresh set to %ld clocks, auto refresh %s\n",
refresh_clocks, auto_refresh ? "on" : "off");
pci_write_cfg_long (0, 0, DRAM_REFRESH0,
(1 << 16) | (1 << 15) | (auto_refresh << 12) |
(refresh_clocks));
debug ("DRAM_REFRESH0 = 0x%08x\n",
(1 << 16) | (1 << 15) | (auto_refresh << 12) |
(refresh_clocks));
/* pci_write_cfg_long(0, 0, DRAM_REFRESH0, 0x00019400); */
/* Set mode registers */
/* FIXME: For now, set same burst len for all modules. Dunno if that's necessary */
/* Find a common burst len */
burst_support = 0xff;
if (banks[0].used)
burst_support = banks[0].burst_len;
if (banks[1].used)
burst_support = banks[1].burst_len;
if (banks[2].used)
burst_support = banks[2].burst_len;
if (banks[3].used)
burst_support = banks[3].burst_len;
/*
** Mode register:
** Bits Use
** 0-2 Burst len
** 3 Burst type (0 = sequential, 1 = interleave)
** 4-6 CAS latency
** 7-8 Operation mode (0 = default, all others invalid)
** 9 Write burst
** 10-11 Reserved
**
** Mode register burst table:
** A2 A1 A0 lenght
** 0 0 0 1
** 0 0 1 2
** 0 1 0 4
** 0 1 1 8
** 1 0 0 invalid
** 1 0 1 invalid
** 1 1 0 invalid
** 1 1 1 page (only valid for non-interleaved)
*/
burst_len = burst_to_len (burst_support);
burst_len = 2; /* FIXME */
if (banks[0].used) {
pci_write_cfg_word (0, 0, DRAM_PCR0,
0x8000 | burst_len | (banks[0].cas_used << 4));
debug ("Mode bank 0: 0x%08x\n",
0x8000 | burst_len | (banks[0].cas_used << 4));
} else {
/* Seems to be needed to disable the bank */
pci_write_cfg_word (0, 0, DRAM_PCR0, 0x0000 | 0x032);
}
if (banks[1].used) {
pci_write_cfg_word (0, 0, DRAM_PCR0,
0x9000 | burst_len | (banks[1].cas_used << 4));
debug ("Mode bank 1: 0x%08x\n",
0x8000 | burst_len | (banks[1].cas_used << 4));
} else {
/* Seems to be needed to disable the bank */
pci_write_cfg_word (0, 0, DRAM_PCR0, 0x1000 | 0x032);
}
if (banks[2].used) {
pci_write_cfg_word (0, 0, DRAM_PCR0,
0xa000 | burst_len | (banks[2].cas_used << 4));
debug ("Mode bank 2: 0x%08x\n",
0x8000 | burst_len | (banks[2].cas_used << 4));
} else {
/* Seems to be needed to disable the bank */
pci_write_cfg_word (0, 0, DRAM_PCR0, 0x2000 | 0x032);
}
if (banks[3].used) {
pci_write_cfg_word (0, 0, DRAM_PCR0,
0xb000 | burst_len | (banks[3].cas_used << 4));
debug ("Mode bank 3: 0x%08x\n",
0x8000 | burst_len | (banks[3].cas_used << 4));
} else {
/* Seems to be needed to disable the bank */
pci_write_cfg_word (0, 0, DRAM_PCR0, 0x3000 | 0x032);
}
pci_write_cfg_word (0, 0, 0xba, 0x00);
return total_ram;
}
extern int drv_isa_kbd_init (void);
int last_stage_init (void)
{
drv_isa_kbd_init ();
return 0;
}
int overwrite_console (void)
{
return (0);
}
#define in_8 read_byte
#define out_8 write_byte
static __inline__ unsigned long get_msr (void)
{
unsigned long msr;
asm volatile ("mfmsr %0":"=r" (msr):);
return msr;
}
static __inline__ void set_msr (unsigned long msr)
{
asm volatile ("mtmsr %0"::"r" (msr));
}
int board_early_init_f (void)
{
unsigned char c_value = 0;
unsigned long msr;
/* Basic init of PS/2 keyboard (needed for some reason)... */
/* Ripped from John's code */
while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
out_8 ((unsigned char *) 0xfe000064, 0xaa);
while ((in_8 ((unsigned char *) 0xfe000064) & 0x01) == 0);
c_value = in_8 ((unsigned char *) 0xfe000060);
while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
out_8 ((unsigned char *) 0xfe000064, 0xab);
while ((in_8 ((unsigned char *) 0xfe000064) & 0x01) == 0);
c_value = in_8 ((unsigned char *) 0xfe000060);
while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
out_8 ((unsigned char *) 0xfe000064, 0xae);
/* while ((in_8((unsigned char *)0xfe000064) & 0x01) == 0); */
/* c_value = in_8((unsigned char *)0xfe000060); */
/* Enable FPU */
msr = get_msr ();
set_msr (msr | MSR_FP);
via_calibrate_bus_freq ();
return 0;
}
board/MAI/AmigaOneG3SE/articiaS.h
+142
View File
@@ -0,0 +1,142 @@
#ifndef ARTICIAS_H
#define ARTICIAS_H
#include "short_types.h"
#include <common.h>
#define REG_GROUP 0xF0
/* ArticiaS registers */
#define GLOBALINFO0 0x50
#define GLOBALINFO1 0x51
#define GLOBALINFO2 0x52
#define GLOBALINFO3 0x53
#define GLOBALCTL0 0x54
#define GLOBALCTL1 0x55
#define NVRAMCTL 0x56
#define PCI1ACR0 0x58
#define PCI1ACR1 0x59
#define PCI1ACR2 0x5a
#define PCI1ACR3 0x5b
#define HBUSACR0 0x5c
#define HBUSACR1 0x5d
#define HBUSACR2 0x5e
#define HBUSACR3 0x5f
#define HOSTINT0 0x68
#define HOSTINT1 0x69
#define HOSTINT2 0x6a
#define HOSTINT3 0x6b
#define HOSTRBCR 0x70
#define XDBCR 0x74
#define LBSBCR2 0xd2
/* Memory controller */
#define DIMM0_B0_SCR0 0x90
#define DIMM0_B1_SCR0 0x94
#define DIMM1_B2_SCR0 0x98
#define DIMM1_B3_SCR0 0x9c
#define DIMM2_B4_SCR0 0xa0
#define DIMM2_B5_SCR0 0xa4
#define DIMM3_B6_SCR0 0xa8
#define DIMM3_B7_SCR0 0xac
#define DIMM0_TCR0 0xb0
#define DIMM1_TCR0 0xb2
#define DIMM2_TCR0 0xb4
#define DIMM3_TCR0 0xb6
#define DRAM_REFRESH0 0xb8
#define DRAM_GCR0 0xc0
#define DRAM_PCR0 0xc6
#define DRAM_ECC0 0xc4
#define SRAM_CR 0xc8
#define DRAM_RAS_CTL0 0xcc
#define DRAM_RAS_CTL1 0xcd
/* Bits for REG_GROUP */
#define REG_GROUP_MULTI (1<<1)
#define REG_GROUP_SPECIAL (1<<3)
#define REG_GROUP_DIAG (0x1<<4)
#define REG_GROUP_POWER (0x2<<4)
#define GLOBALINFO0_BO (1<<7)
#define GLOBALINFO2_B1ARBITER (1<<6)
#define HBUSACR0_CPUAPC (1<<0)
#define HBUSACR0_NUMREQ_2 (0<<1)
#define HBUSACR0_NUMREQ_3 (1<<1)
#define HBUSACR0_NUMREQ_4 (2<<1)
#define HBUSACR0_NUMREQ_MASK (7<<1)
#define HBUSACR0_RAW (1<<6)
#define HBUSACR0_WAIT (1<<7)
#define HBUSACR0_RESERVED (0x30)
#define HBUSACR2_BURST (1<<0)
#define HBUSACR2_LAT (1<<1)
#define HBUSACR3_LMWC_SM (1<<0)
#define HBUSACR3_LMWC_PCI1 (1<<1)
#define HBUSACR3_LMWC_PCI0 (1<<2)
#define HBUSACR3_PMWC_PCI1 (1<<3)
#define HBUSACR3_PMWC_PCI0 (1<<4)
#define HBUSACR3_FKH (1<<5)
#define HBUSACR3_92H_EN (1<<6)
#define HBUSACR3_60H_64H_EN (1<<7)
#define HOSTRBCR_PREFETCH (1<<4)
#define XDBCR_HWTOXD (1<<0)
#define XDBCR_KBTOXD (1<<1)
#define XDBCR_RTCTOXD (1<<2)
#define XDBCR_SCALE_1_1 (0x0<<3)
#define XDBCR_SCALE_2_2 (0x1<<3)
#define XDBCR_SCALE_3_2 (0x2<<3)
#define XDBCR_SCALE_4_4 (0x3<<3)
#define XDBCR_SCALE_5_8 (0x4<<3)
#define XDBCR_SCALE_6_8 (0x5<<3)
#define XDBCR_SCALE_8_8 (0x6<<3)
#define XDBCR_SCALE_0_16 (0x7<<3)
#define XDBCR_XDPROM (1<<7)
#define LBSBCR2_1_RWAC (1<<2)
/* PCI controller */
#define ARTICIAS_PCI_CFGADDR 0xfec00cf8
#define ARTICIAS_PCI_CFGDATA 0xfee00cfc
#define ARTICIAS_PCI_BUS 0x80000000
#define ARTICIAS_PCI_MAXSIZE 0x7cffffff
#define ARTICIAS_PCI_PHYS 0x80000000
#define ARTICIAS_SYS_BUS 0x00000000
#define ARTICIAS_SYS_MAXSIZE 0x7fffffff
#define ARTICIAS_SYS_PHYS 0x00000000
#define ARTICIAS_PCIIO_BUS 0x00800000
#define ARTICIAS_PCIIO_MAXSIZE 0x003fffff
#define ARTICIAS_PCIIO_PHYS 0xfe800000
#define ARTICIAS_ISAIO_BUS 0x00002000
#define ARTICIAS_ISAIO_MAXSIZE 0x0000d000
#define ARTICIAS_ISAIO_PHYS 0xfe002000
/* Prototypes */
long articiaS_ram_init(void);
void articiaS_pci_init(void);
#endif
board/MAI/AmigaOneG3SE/articiaS_pci.c
+576
View File
@@ -0,0 +1,576 @@
/*
* (C) Copyright 2002
* Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
#include "memio.h"
#include "articiaS.h"
#undef ARTICIA_PCI_DEBUG
#ifdef ARTICIA_PCI_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
struct pci_controller articiaS_hose;
long irq_alloc(long wanted);
static pci_dev_t pci_hose_find_class(struct pci_controller *hose, int bus, short find_class, int index);
static int articiaS_init_vga(void);
static void pci_cfgfunc_dummy(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table);
unsigned char pci_irq_alloc(void);
extern void via_cfgfunc_via686(struct pci_controller * host, pci_dev_t dev, struct pci_config_table *table);
extern void via_cfgfunc_ide_init(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table);
extern void via_init_irq_routing(uint8 []);
extern void via_init_afterscan(void);
#define cfgfunc_via686 1
#define cfgfunc_dummy 2
#define cfgfunc_ide_init 3
static struct pci_config_table config_table[] =
{
{
0x1106, PCI_ANY_ID, PCI_CLASS_BRIDGE_ISA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
(void *)cfgfunc_via686, {0, 0, 0}
},
{
0x1106, PCI_ANY_ID, PCI_ANY_ID, 0,7,4,
(void *)cfgfunc_dummy, {0,0,0}
},
{
0x1106, 0x3068, PCI_ANY_ID, 0, 7, PCI_ANY_ID,
(void *)cfgfunc_dummy, {0,0,0}
},
{
0x1106, PCI_ANY_ID, PCI_ANY_ID, 0,7,1,
(void *)cfgfunc_ide_init, {0,0,0}
},
{
0,
}
};
void pci_cfgfunc_dummy(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table)
{
}
unsigned long irq_penalties[16] =
{
1000, /* 0:timer */
1000, /* 1:keyboard */
1000, /* 2:cascade */
50, /* 3:serial (COM2) */
50, /* 4:serial (COM1) */
4, /* 5:USB2 */
100, /* 6:floppy */
3, /* 7:parallel */
50, /* 8:AC97/MC97 */
0, /* 9: */
3, /* 10:: */
0, /* 11: */
3, /* 12: USB1 */
0, /* 13: */
100, /* 14: ide0 */
100, /* 15: ide1 */
};
/*
* The following defines a hard-coded interrupt mapping for the
* know devices on the board.
* If a device isn't found here, assumed to be a device that's
* plugged into a PCI or AGP slot
* NOTE: This table is machine dependant.
*/
struct pci_irq_fixup_table
{
uint8 bus; /* Bus number */
uint8 device; /* Device number */
uint8 func; /* Function number */
uint8 interrupt; /* Interrupt to use (0xff to disable) */
};
struct pci_irq_fixup_table fixuptab [] =
{
{ 0, 0, 0, 0xff}, /* Articia S host bridge */
{ 0, 1, 0, 0xff}, /* Articia S AGP bridge */
/* { 0, 6, 0, 0x05}, /###* 3COM ethernet */
{ 0, 7, 0, 0xff}, /* VIA southbridge */
{ 0, 7, 1, 0x0e}, /* IDE controller in legacy mode */
/* { 0, 7, 2, 0x05}, /###* First USB controller */
/* { 0, 7, 3, 0x0c}, /###* Second USB controller (shares interrupt with ethernet) */
{ 0, 7, 4, 0xff}, /* ACPI Power Management */
/* { 0, 7, 5, 0x08}, /###* AC97 */
/* { 0, 7, 6, 0x08}, /###* MC97 */
{ 0xff, 0xff, 0xff, 0xff}
};
/*
* This table maps IRQ's to PCI interrupts
*/
uint8 pci_intmap[4] = {0, 0, 0, 0};
/*
* Map PCI slots to interrupt routings
* This table lists the device number assigned to a card inserted
* into the slot, along with a permutation for the slot's IRQ routing.
* NOTE: This table is machine dependant.
*/
struct pci_slot_irq_routing
{
uint8 bus;
uint8 device;
uint8 ints[4];
};
struct pci_slot_irq_routing amigaone_pci_routing[] =
{
{0, 8, {0, 1, 2, 3}}, /* Slot 1 (left of riser slot) */
{0, 9, {1, 2, 3, 0}}, /* Slot 2 (middle slot) */
{0, 10, {2, 3, 0, 1}}, /* Slot 3 (leftmost slot) */
{1, 0, {1, 0, 2, 3}}, /* AGP slot (only IRQA and IRQB) */
{1, 1, {1, 2, 3, 0}}, /* PCI slot on AGP bus */
{0, 6, {3, 3, 3, 3}}, /* On board ethernet */
{0, 7, {0, 1, 2, 3}}, /* Southbridge */
{0xff, 0, {0, 0, 0, 0}}
};
void articiaS_pci_irq_init(void)
{
char *s;
s = getenv("pci_irqa");
if (s)
pci_intmap[0] = simple_strtoul (s, NULL, 10);
else
pci_intmap[0] = pci_irq_alloc();
s = getenv("pci_irqb");
if (s)
pci_intmap[1] = simple_strtoul (s, NULL, 10);
else
pci_intmap[1] = pci_irq_alloc();
s = getenv("pci_irqc");
if (s)
pci_intmap[2] = simple_strtoul (s, NULL, 10);
else
pci_intmap[2] = pci_irq_alloc();
s = getenv("pci_irqd");
if (s)
pci_intmap[3] = simple_strtoul (s, NULL, 10);
else
pci_intmap[3] = pci_irq_alloc();
}
unsigned char pci_irq_alloc(void)
{
int i;
int interrupt = 10;
unsigned long min_penalty = 1000;
/* Search for the minimal penalty, favoring interrupts at the end */
for (i = 0; i < 16; i++)
{
if (irq_penalties[i] <= min_penalty)
{
interrupt = i;
min_penalty = irq_penalties[i];
}
}
PRINTF("pci_irq_alloc: Minimal penalty is %ld for %d\n", min_penalty, interrupt);
irq_penalties[interrupt]++;
return interrupt;
}
void articiaS_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
int8 bus, device, func, pin, line;
int i;
bus = PCI_BUS(dev);
device = PCI_DEV(dev);
func = PCI_FUNC(dev);
PRINTF("Fixup irq of %d:%d.%d\n", bus, device, func);
/* Search for the device in the table */
for (i = 0; fixuptab[i].bus != 0xff; i++)
{
if (bus == fixuptab[i].bus && device == fixuptab[i].device && func == fixuptab[i].func)
{
/* If the device needs an interrupt, write it */
if (fixuptab[i].interrupt != 0xff)
{
PRINTF("Assigning IRQ %d (fixed)\n", fixuptab[i].interrupt);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, fixuptab[i].interrupt);
}
else
{
/* Otherwise, see if it wants an interrupt, and disable it if needed */
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
if (pin)
{
PRINTF("Disabling IRQ\n");
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 0xff);
}
}
return;
}
}
/* If we get here, we have another PCI device in a slot... find the appropriate IRQ */
/* Find matching pin */
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
pin--;
/* Search for it's map */
for (i = 0; amigaone_pci_routing[i].bus != 0xff; i++)
{
if (bus == amigaone_pci_routing[i].bus && device == amigaone_pci_routing[i].device)
{
line = pci_intmap[amigaone_pci_routing[i].ints[pin]];
PRINTF("Assigning IRQ %d (pin %d)\n", line, pin);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, line);
return;
}
}
PRINTF("Unkonwn PCI device found\n");
}
void articiaS_pci_init (void)
{
int i;
char *s;
PRINTF("atriciaS_pci_init\n");
/* Why aren't these relocated?? */
for (i=0; config_table[i].config_device; i++)
{
switch((int)config_table[i].config_device)
{
case cfgfunc_via686: config_table[i].config_device = via_cfgfunc_via686; break;
case cfgfunc_dummy: config_table[i].config_device = pci_cfgfunc_dummy; break;
case cfgfunc_ide_init: config_table[i].config_device = via_cfgfunc_ide_init; break;
default: PRINTF("Error: Unknown constant\n");
}
}
articiaS_hose.first_busno = 0;
articiaS_hose.last_busno = 0xff;
articiaS_hose.config_table = config_table;
articiaS_hose.fixup_irq = articiaS_pci_fixup_irq;
articiaS_pci_irq_init();
/* System memory */
pci_set_region(articiaS_hose.regions + 0,
ARTICIAS_SYS_BUS,
ARTICIAS_SYS_PHYS,
ARTICIAS_SYS_MAXSIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region(articiaS_hose.regions + 1,
ARTICIAS_PCI_BUS,
ARTICIAS_PCI_PHYS,
ARTICIAS_PCI_MAXSIZE,
PCI_REGION_MEM);
/* PCI io space */
pci_set_region(articiaS_hose.regions + 2,
ARTICIAS_PCIIO_BUS,
ARTICIAS_PCIIO_PHYS,
ARTICIAS_PCIIO_MAXSIZE,
PCI_REGION_IO);
/* PCI/ISA io space */
pci_set_region(articiaS_hose.regions + 3,
ARTICIAS_ISAIO_BUS,
ARTICIAS_ISAIO_PHYS,
ARTICIAS_ISAIO_MAXSIZE,
PCI_REGION_IO);
articiaS_hose.region_count = 4;
pci_setup_indirect(&articiaS_hose, ARTICIAS_PCI_CFGADDR, ARTICIAS_PCI_CFGDATA);
PRINTF("Registering articia hose...\n");
pci_register_hose(&articiaS_hose);
PRINTF("Enabling AGP...\n");
pci_write_config_byte(PCI_BDF(0,0,0), 0x58, 0x01);
PRINTF("Scanning bus...\n");
articiaS_hose.last_busno = pci_hose_scan(&articiaS_hose);
via_init_irq_routing(pci_intmap);
PRINTF("After-Scan results:\n");
PRINTF("Bus range: %d - %d\n", articiaS_hose.first_busno , articiaS_hose.last_busno);
via_init_afterscan();
pci_write_config_byte(PCI_BDF(0,1,0), PCI_INTERRUPT_LINE, 0xFF);
s = getenv("as_irq");
if (s)
{
pci_write_config_byte(PCI_BDF(0,0,0), PCI_INTERRUPT_LINE, simple_strtoul (s, NULL, 10));
}
s = getenv("x86_run_bios");
if (!s || (s && strcmp(s, "on")==0))
{
if (articiaS_init_vga() == -1)
{
/* If the VGA didn't init and we have stdout set to VGA, reset to serial */
/* s = getenv("stdout"); */
/* if (s && strcmp(s, "vga") == 0) */
/* { */
/* setenv("stdout", "serial"); */
/* } */
}
}
pci_write_config_byte(PCI_BDF(0,1,0), PCI_INTERRUPT_LINE, 0xFF);
}
pci_dev_t pci_hose_find_class(struct pci_controller *hose, int bus, short find_class, int index)
{
unsigned int sub_bus, found_multi=0;
unsigned short vendor, class;
unsigned char header_type;
pci_dev_t dev;
u8 c1, c2;
sub_bus = bus;
for (dev = PCI_BDF(bus,0,0);
dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
dev += PCI_BDF(0,0,1))
{
if ( dev == PCI_BDF(hose->first_busno,0,0) )
continue;
if (PCI_FUNC(dev) && !found_multi)
continue;
pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
if (vendor != 0xffff && vendor != 0x0000)
{
if (!PCI_FUNC(dev))
found_multi = header_type & 0x80;
pci_hose_read_config_byte(hose, dev, 0x0B, &c1);
pci_hose_read_config_byte(hose, dev, 0x0A, &c2);
class = c1<<8 | c2;
/*printf("At %02x:%02x:%02x: class %x\n", */
/* PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), class); */
if (class == find_class)
{
if (index == 0)
return dev;
else index--;
}
}
}
return ~0;
}
/*
* For a given bus number, find the bridge on this hose that provides this
* bus number. The function scans for bridges and peeks config space offset
* 0x19 (PCI_SECONDARY_BUS).
*/
pci_dev_t pci_find_bridge_for_bus(struct pci_controller *hose, int busnr)
{
pci_dev_t dev;
int bus;
unsigned int found_multi=0;
unsigned char header_type;
unsigned short vendor;
unsigned char secondary_bus;
if (hose == NULL) hose = &articiaS_hose;
if (busnr < hose->first_busno || busnr > hose->last_busno) return PCI_ANY_ID; /* Not in range */
/*
* The bridge must be on a lower bus number
*/
for (bus = hose->first_busno; bus < busnr; bus++)
{
for (dev = PCI_BDF(bus,0,0);
dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
dev += PCI_BDF(0,0,1))
{
if ( dev == PCI_BDF(hose->first_busno,0,0) )
continue;
if (PCI_FUNC(dev) && !found_multi)
continue;
pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
if (vendor != 0xffff && vendor != 0x0000)
{
if (!PCI_FUNC(dev))
found_multi = header_type & 0x80;
if (header_type == 1) /* Bridge device header */
{
pci_hose_read_config_byte(hose, dev, PCI_SECONDARY_BUS, &secondary_bus);
if ((int)secondary_bus == busnr) return dev;
}
}
}
}
return PCI_ANY_ID;
}
static short classes[] =
{
PCI_CLASS_DISPLAY_VGA,
PCI_CLASS_DISPLAY_XGA,
PCI_CLASS_DISPLAY_3D,
PCI_CLASS_DISPLAY_OTHER,
~0
};
extern int execute_bios(pci_dev_t gr_dev, void *);
pci_dev_t video_dev;
int articiaS_init_vga (void)
{
DECLARE_GLOBAL_DATA_PTR;
extern void shutdown_bios(void);
pci_dev_t dev = ~0;
int busnr = 0;
int classnr = 0;
video_dev = PCI_ANY_ID;
printf("VGA: ");
PRINTF("Trying to initialize x86 VGA Card(s)\n");
while (dev == ~0)
{
PRINTF("Searching for class 0x%x on bus %d\n", classes[classnr], busnr);
/* Find the first of this class on this bus */
dev = pci_hose_find_class(&articiaS_hose, busnr, classes[classnr], 0);
if (dev != ~0)
{
PRINTF("Found VGA Card at %02x:%02x:%02x\n", PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
break;
}
busnr++;
if (busnr > articiaS_hose.last_busno)
{
busnr = 0;
classnr ++;
if (classes[classnr] == ~0)
{
printf("NOT PRESENT\n");
return -1;
}
}
}
/*
* If we get here we have found the first graphics card.
* If the bus number is not 0, then it is probably behind a bridge, and the
* bridge needs to be told to forward VGA access.
*/
if (PCI_BUS(dev) != 0)
{
pci_dev_t bridge;
PRINTF("Behind bridge, looking for bridge\n");
bridge = pci_find_bridge_for_bus(&articiaS_hose, PCI_BUS(dev));
if (dev != PCI_ANY_ID)
{
unsigned char agp_control_0;
PRINTF("Got the bridge at %02x:%02x:%02x\n",
PCI_BUS(bridge), PCI_DEV(bridge), PCI_FUNC(bridge));
pci_hose_read_config_byte(&articiaS_hose, bridge, 0x3E, &agp_control_0);
agp_control_0 |= 0x18;
pci_hose_write_config_byte(&articiaS_hose, bridge, 0x3E, agp_control_0);
PRINTF("Configured for VGA forwarding\n");
}
}
/*
* Now try to run the bios
*/
PRINTF("Trying to run bios now\n");
if (execute_bios(dev, gd->relocaddr))
{
printf("OK\n");
video_dev = dev;
}
else
{
printf("ERROR\n");
}
PRINTF("Done scanning.\n");
shutdown_bios();
if (dev == PCI_ANY_ID) return -1;
else return 0;
}
board/MAI/AmigaOneG3SE/board_asm_init.S
+156
View File
@@ -0,0 +1,156 @@
#include "macros.h"
#define GLOBALINFO0 0x50
#define GLOBALINFO0_BO (1<<7)
#define GLOBALINFO2_B1ARBITER (1<<6)
#define HBUSACR0 0x5c
#define HBUSACR2_BURST (1<<0)
#define HBUSACR2_LAT (1<<1)
#define RECEIVER_HOLDING 0
#define TRANSMITTER_HOLDING 0
#define INTERRUPT_ENABLE 1
#define INTERRUPT_STATUS 2
#define FIFO_CONTROL 2
#define LINE_CONTROL 3
#define MODEM_CONTROL 4
#define LINE_STATUS 5
#define MODEM_STATUS 6
#define SCRATCH_PAD 7
#define DIVISOR_LATCH_LSB 0
#define DIVISOR_LATCH_MSB 1
#define PRESCALER_DIVISION 5
#define UART(x) (0x3f8+(x))
#define GLOBALINFO0 0x50
#define GLOBALINFO0_BO (1<<7)
#define GLOBALINFO2_B1ARBITER (1<<6)
#define HBUSACR0 0x5c
#define HBUSACR2_BURST (1<<0)
#define HBUSACR2_LAT (1<<1)
#define SUPERIO_1 ((7 << 3) | (0))
#define SUPERIO_2 ((7 << 3) | (1))
.globl board_asm_init
board_asm_init:
mflr r29
/* Set 'Must-set' register */
li r3, 0
li r4, 0
li r5, 0x5e
bl pci_read_cfg_byte
ori r3, r3, (1<<1)
xori r6, r3, (1<<1)
li r3, 0
bl pci_write_cfg_byte
li r3, 0
li r5, 0x52
bl pci_read_cfg_byte
ori r6, r3, (1<<6)
li r3, 0
bl pci_write_cfg_byte
li r3, 0
li r4, 0x08
li r5, 0xd2
bl pci_read_cfg_byte
ori r6, r3, (1<<2)
li r3, 0
bl pci_write_cfg_byte
/* Do PCI reset */
/* li r3, 0
li r4, 0x38
li r5, 0x47
bl pci_read_cfg_byte
ori r6, r3, 0x01
li r3, 0
li r4, 0x38
li r5, 0x47
bl pci_write_cfg_byte*/
/* Enable NVRAM for environment */
li r3, 0
li r4, 0
li r5, 0x56
li r6, 0x0B
bl pci_write_cfg_byte
/* Init Super-I/O chips */
siowb 0x40, 0x08
siowb 0x41, 0x01
siowb 0x45, 0x80
siowb 0x46, 0x60
siowb 0x47, 0x20
siowb 0x48, 0x01
siowb 0x4a, 0xc4
siowb 0x50, 0x0e
siowb 0x51, 0x76
siowb 0x52, 0x34
siowb 0x54, 0x00
siowb 0x55, 0x90
siowb 0x56, 0x99
siowb 0x57, 0x90
siowb 0x85, 0x01
/* Enable configuration mode for SuperIO */
li r3, 0
li r4, (7<<3)
li r5, 0x85
bl pci_read_cfg_byte
ori r6, r3, 0x02
mr r31, r6
li r3,0
bl pci_write_cfg_byte
/* COM1 as 3f8 */
outb 0x3f0, 0xe7
outb 0x3f1, 0xfe
/* COM2 as 2f8 */
outb 0x3f0, 0xe8
outb 0x3f1, 0xeb
/* Enable */
outb 0x3f0, 0xe2
inb r3, 0x3f1
ori r3, r3, 0x0c
outb 0x3f0, 0xe2
outbr 0x3f1, r3
/* Disable configuration mode */
li r3, 0
li r4, (7<<3)
li r5, 0x85
mr r6, r31
bl pci_write_cfg_byte
/* Set line control */
outb UART(LINE_CONTROL), 0x83
outb UART(DIVISOR_LATCH_LSB), 0x0c
outb UART(DIVISOR_LATCH_MSB), 0x00
outb UART(LINE_CONTROL), 0x3
mtlr r29
blr
.globl new_reset
.globl new_reset_end
new_reset:
li r0, 0x100
oris r0, r0, 0xFFF0
mtlr r0
blr
new_reset_end:
board/MAI/AmigaOneG3SE/cmd_boota.c
+129
View File
@@ -0,0 +1,129 @@
#include <common.h>
#include <command.h>
#include "../disk/part_amiga.h"
#include <asm/cache.h>
#undef BOOTA_DEBUG
#ifdef BOOTA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
struct block_header {
u32 id;
u32 summed_longs;
s32 chk_sum;
};
extern block_dev_desc_t *ide_get_dev (int dev);
extern struct bootcode_block *get_bootcode (block_dev_desc_t * dev_desc);
extern int sum_block (struct block_header *header);
struct bootcode_block bblk;
int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
unsigned char *load_address = (unsigned char *) CFG_LOAD_ADDR;
unsigned char *base_address;
unsigned long offset;
unsigned long part_number = 0;
block_dev_desc_t *boot_disk;
char *s;
struct bootcode_block *boot_code;
/* Get parameters */
switch (argc) {
case 2:
load_address = (unsigned char *) simple_strtol (argv[1], NULL, 16);
part_number = 0;
break;
case 3:
load_address = (unsigned char *) simple_strtol (argv[1], NULL, 16);
part_number = simple_strtol (argv[2], NULL, 16);
break;
}
base_address = load_address;
PRINTF ("Loading boot code from disk %d to %p\n", part_number,
load_address);
/* Find the appropriate disk device */
boot_disk = ide_get_dev (part_number);
if (!boot_disk) {
PRINTF ("Unknown disk %d\n", part_number);
return 1;
}
/* Find the bootcode block */
boot_code = get_bootcode (boot_disk);
if (!boot_code) {
PRINTF ("Not a bootable disk %d\n", part_number);
return 1;
}
/* Only use the offset from the first block */
offset = boot_code->load_data[0];
memcpy (load_address, &boot_code->load_data[1], 122 * 4);
load_address += 122 * 4;
/* Setup for the loop */
bblk.next = boot_code->next;
boot_code = &bblk;
/* Scan the chain, and copy the loader succesively into the destination area */
while (0xffffffff != boot_code->next) {
PRINTF ("Loading block %d\n", boot_code->next);
/* Load block */
if (1 !=
boot_disk->block_read (boot_disk->dev, boot_code->next, 1,
(ulong *) & bblk)) {
PRINTF ("Read error\n");
return 1;
}
/* check sum */
if (sum_block ((struct block_header *) (ulong *) & bblk) != 0) {
PRINTF ("Checksum error\n");
return 1;
}
/* Ok, concatenate it to the already loaded code */
memcpy (load_address, boot_code->load_data, 123 * 4);
load_address += 123 * 4;
}
printf ("Bootcode loaded to %p (size %d)\n", base_address,
load_address - base_address);
printf ("Entry point at %p\n", base_address + offset);
flush_cache (base_address, load_address - base_address);
s = getenv ("autostart");
if (s && strcmp (s, "yes") == 0) {
DECLARE_GLOBAL_DATA_PTR;
void (*boot) (bd_t *, char *, block_dev_desc_t *);
char *args;
boot = (void (*)(bd_t *, char *, block_dev_desc_t *)) (base_address + offset);
boot (gd->bd, getenv ("amiga_bootargs"), boot_disk);
}
return 0;
}
#if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP)
U_BOOT_CMD(
boota, 3, 1, do_boota,
"boota - boot an Amiga kernel\n",
"address disk"
);
#endif /* _CMD_BOOTA_H */
board/MAI/AmigaOneG3SE/config.mk
+32
View File
@@ -0,0 +1,32 @@
#
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# AmigaOneG3SE boards
#
X86EMU = -I../bios_emulator/scitech/include -I../bios_emulator/scitech/src/x86emu
TEXT_BASE = 0xfff00000
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -Wa,-mregnames -DEASTEREGG $(X86EMU) -Dprintk=printf #-DDEBUG
board/MAI/AmigaOneG3SE/enet.c
+884
View File
@@ -0,0 +1,884 @@
/*
* (C) Copyright 2002
* Adam Kowalczyk, ACK Software Controls Inc. akowalczyk@cogeco.ca
*
* Some portions taken from 3c59x.c Written 1996-1999 by Donald Becker.
*
* Outline of the program based on eepro100.c which is
*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <asm/io.h>
#include <pci.h>
#include "articiaS.h"
#include "memio.h"
/* 3Com Ethernet PCI definitions*/
/* #define PCI_VENDOR_ID_3COM 0x10B7 */
#define PCI_DEVICE_ID_3COM_3C905C 0x9200
/* 3Com Commands, top 5 bits are command and bottom 11 bits are parameters */
#define TotalReset (0<<11)
#define SelectWindow (1<<11)
#define StartCoax (2<<11)
#define RxDisable (3<<11)
#define RxEnable (4<<11)
#define RxReset (5<<11)
#define UpStall (6<<11)
#define UpUnstall (6<<11)+1
#define DownStall (6<<11)+2
#define DownUnstall (6<<11)+3
#define RxDiscard (8<<11)
#define TxEnable (9<<11)
#define TxDisable (10<<11)
#define TxReset (11<<11)
#define FakeIntr (12<<11)
#define AckIntr (13<<11)
#define SetIntrEnb (14<<11)
#define SetStatusEnb (15<<11)
#define SetRxFilter (16<<11)
#define SetRxThreshold (17<<11)
#define SetTxThreshold (18<<11)
#define SetTxStart (19<<11)
#define StartDMAUp (20<<11)
#define StartDMADown (20<<11)+1
#define StatsEnable (21<<11)
#define StatsDisable (22<<11)
#define StopCoax (23<<11)
#define SetFilterBit (25<<11)
/* The SetRxFilter command accepts the following classes */
#define RxStation 1
#define RxMulticast 2
#define RxBroadcast 4
#define RxProm 8
/* 3Com status word defnitions */
#define IntLatch 0x0001
#define HostError 0x0002
#define TxComplete 0x0004
#define TxAvailable 0x0008
#define RxComplete 0x0010
#define RxEarly 0x0020
#define IntReq 0x0040
#define StatsFull 0x0080
#define DMADone (1<<8)
#define DownComplete (1<<9)
#define UpComplete (1<<10)
#define DMAInProgress (1<<11) /* DMA controller is still busy.*/
#define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/
/* Polling Registers */
#define DnPoll 0x2d
#define UpPoll 0x3d
/* Register window 0 offets */
#define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */
#define Wn0EepromData 12 /* Window 0: EEPROM results register. */
#define IntrStatus 0x0E /* Valid in all windows. */
/* Register window 0 EEPROM bits */
#define EEPROM_Read 0x80
#define EEPROM_WRITE 0x40
#define EEPROM_ERASE 0xC0
#define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */
#define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */
/* EEPROM locations. */
#define PhysAddr01 0
#define PhysAddr23 1
#define PhysAddr45 2
#define ModelID 3
#define EtherLink3ID 7
#define IFXcvrIO 8
#define IRQLine 9
#define NodeAddr01 10
#define NodeAddr23 11
#define NodeAddr45 12
#define DriverTune 13
#define Checksum 15
/* Register window 1 offsets, the window used in normal operation */
#define TX_FIFO 0x10
#define RX_FIFO 0x10
#define RxErrors 0x14
#define RxStatus 0x18
#define Timer 0x1A
#define TxStatus 0x1B
#define TxFree 0x1C /* Remaining free bytes in Tx buffer. */
/* Register Window 2 */
#define Wn2_ResetOptions 12
/* Register Window 3: MAC/config bits */
#define Wn3_Config 0 /* Internal Configuration */
#define Wn3_MAC_Ctrl 6
#define Wn3_Options 8
#define BFEXT(value, offset, bitcount) \
((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
#define BFINS(lhs, rhs, offset, bitcount) \
(((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
(((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
#define RAM_SIZE(v) BFEXT(v, 0, 3)
#define RAM_WIDTH(v) BFEXT(v, 3, 1)
#define RAM_SPEED(v) BFEXT(v, 4, 2)
#define ROM_SIZE(v) BFEXT(v, 6, 2)
#define RAM_SPLIT(v) BFEXT(v, 16, 2)
#define XCVR(v) BFEXT(v, 20, 4)
#define AUTOSELECT(v) BFEXT(v, 24, 1)
/* Register Window 4: Xcvr/media bits */
#define Wn4_FIFODiag 4
#define Wn4_NetDiag 6
#define Wn4_PhysicalMgmt 8
#define Wn4_Media 10
#define Media_SQE 0x0008 /* Enable SQE error counting for AUI. */
#define Media_10TP 0x00C0 /* Enable link beat and jabber for 10baseT. */
#define Media_Lnk 0x0080 /* Enable just link beat for 100TX/100FX. */
#define Media_LnkBeat 0x0800
/* Register Window 7: Bus Master control */
#define Wn7_MasterAddr 0
#define Wn7_MasterLen 6
#define Wn7_MasterStatus 12
/* Boomerang bus master control registers. */
#define PktStatus 0x20
#define DownListPtr 0x24
#define FragAddr 0x28
#define FragLen 0x2c
#define TxFreeThreshold 0x2f
#define UpPktStatus 0x30
#define UpListPtr 0x38
/* The Rx and Tx descriptor lists. */
#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
struct rx_desc_3com {
u32 next; /* Last entry points to 0 */
u32 status; /* FSH -> Frame Start Header */
u32 addr; /* Up to 63 addr/len pairs possible */
u32 length; /* Set LAST_FRAG to indicate last pair */
};
/* Values for the Rx status entry. */
#define RxDComplete 0x00008000
#define RxDError 0x4000
#define IPChksumErr (1<<25)
#define TCPChksumErr (1<<26)
#define UDPChksumErr (1<<27)
#define IPChksumValid (1<<29)
#define TCPChksumValid (1<<30)
#define UDPChksumValid (1<<31)
struct tx_desc_3com {
u32 next; /* Last entry points to 0 */
u32 status; /* bits 0:12 length, others see below */
u32 addr;
u32 length;
};
/* Values for the Tx status entry. */
#define CRCDisable 0x2000
#define TxDComplete 0x8000
#define AddIPChksum 0x02000000
#define AddTCPChksum 0x04000000
#define AddUDPChksum 0x08000000
#define TxIntrUploaded 0x80000000 /* IRQ when in FIFO, but maybe not sent. */
/* XCVR Types */
#define XCVR_10baseT 0
#define XCVR_AUI 1
#define XCVR_10baseTOnly 2
#define XCVR_10base2 3
#define XCVR_100baseTx 4
#define XCVR_100baseFx 5
#define XCVR_MII 6
#define XCVR_NWAY 8
#define XCVR_ExtMII 9
#define XCVR_Default 10 /* I don't think this is correct -> should have been 0x10 if Auto Negotiate */
struct descriptor { /* A generic descriptor. */
u32 next; /* Last entry points to 0 */
u32 status; /* FSH -> Frame Start Header */
u32 addr; /* Up to 63 addr/len pairs possible */
u32 length; /* Set LAST_FRAG to indicate last pair */
};
/* Misc. definitions */
#define NUM_RX_DESC PKTBUFSRX * 10
#define NUM_TX_DESC 1 /* Number of TX descriptors */
#define TOUT_LOOP 1000000
#define ETH_ALEN 6
#define EL3WINDOW(dev, win_num) ETH_OUTW(dev, SelectWindow + (win_num), EL3_CMD)
#define EL3_CMD 0x0e
#define EL3_STATUS 0x0e
#undef ETH_DEBUG
#ifdef ETH_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
static struct rx_desc_3com *rx_ring; /* RX descriptor ring */
static struct tx_desc_3com *tx_ring; /* TX descriptor ring */
static u8 rx_buffer[NUM_RX_DESC][PKTSIZE_ALIGN]; /* storage for the incoming messages */
static int rx_next = 0; /* RX descriptor ring pointer */
static int tx_next = 0; /* TX descriptor ring pointer */
static int tx_threshold;
static void init_rx_ring(struct eth_device* dev);
static void purge_tx_ring(struct eth_device* dev);
static void read_hw_addr(struct eth_device* dev, bd_t * bis);
static int eth_3com_init(struct eth_device* dev, bd_t *bis);
static int eth_3com_send(struct eth_device* dev, volatile void *packet, int length);
static int eth_3com_recv(struct eth_device* dev);
static void eth_3com_halt(struct eth_device* dev);
#define io_to_phys(a) pci_io_to_phys((pci_dev_t)dev->priv, a)
#define phys_to_io(a) pci_phys_to_io((pci_dev_t)dev->priv, a)
#define mem_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
#define phys_to_mem(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
static inline int ETH_INL(struct eth_device* dev, u_long addr)
{
__asm volatile ("eieio");
return le32_to_cpu(*(volatile u32 *)io_to_phys(addr + dev->iobase));
}
static inline int ETH_INW(struct eth_device* dev, u_long addr)
{
__asm volatile ("eieio");
return le16_to_cpu(*(volatile u16 *)io_to_phys(addr + dev->iobase));
}
static inline int ETH_INB(struct eth_device* dev, u_long addr)
{
__asm volatile ("eieio");
return *(volatile u8 *)io_to_phys(addr + dev->iobase);
}
static inline void ETH_OUTB(struct eth_device* dev, int command, u_long addr)
{
*(volatile u8 *)io_to_phys(addr + dev->iobase) = command;
__asm volatile ("eieio");
}
static inline void ETH_OUTW(struct eth_device* dev, int command, u_long addr)
{
*(volatile u16 *)io_to_phys(addr + dev->iobase) = cpu_to_le16(command);
__asm volatile ("eieio");
}
static inline void ETH_OUTL(struct eth_device* dev, int command, u_long addr)
{
*(volatile u32 *)io_to_phys(addr + dev->iobase) = cpu_to_le32(command);
__asm volatile ("eieio");
}
static inline int ETH_STATUS(struct eth_device* dev)
{
__asm volatile ("eieio");
return le16_to_cpu(*(volatile u16 *)io_to_phys(EL3_STATUS + dev->iobase));
}