247 lines
6.7 KiB
C
247 lines
6.7 KiB
C
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/*
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* MPC8220 Internal Memory Map
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* Copyright (c) 2004 TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* The Internal Memory Map of the 8220.
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*
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*/
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#ifndef __IMMAP_MPC8220__
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#define __IMMAP_MPC8220__
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/*
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* System configuration registers.
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*/
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typedef struct sys_conf {
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u16 mbar; /* 0x00 */
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u16 res1;
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u16 res2; /* 0x04 */
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u16 sdramds;
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u32 res3[6]; /* 0x08 */
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u32 cscfg[6]; /* 0x20 */
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u32 res4[2]; /* 0x38 */
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u8 res5[3]; /* 0x40 */
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u8 rstctrl;
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u8 res6[3]; /* 0x44 */
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u8 rststat;
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u32 res7[2]; /* 0x48 */
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u32 jtagid; /* 0x50 */
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} sysconf8220_t;
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/*
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* Memory controller registers.
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*/
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typedef struct mem_ctlr {
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ushort mode; /* 0x100 */
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ushort res1;
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u32 ctrl; /* 0x104 */
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u32 cfg1; /* 0x108 */
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u32 cfg2; /* 0x10c */
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} memctl8220_t;
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/*
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* XLB Arbitration registers
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*/
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typedef struct xlb_arb
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{
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uint res1[16]; /* 0x200 */
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uint config; /* 0x240 */
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uint version; /* 0x244 */
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uint status; /* 0x248 */
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uint intEnable; /* 0x24c */
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uint addrCap; /* 0x250 */
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uint busSigCap; /* 0x254 */
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uint addrTenTimeOut; /* 0x258 */
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uint dataTenTimeOut; /* 0x25c */
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uint busActTimeOut; /* 0x260 */
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uint mastPriEn; /* 0x264 */
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uint mastPriority; /* 0x268 */
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uint baseAddr; /* 0x26c */
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} xlbarb8220_t;
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/*
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* Flexbus registers
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*/
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typedef struct flexbus
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{
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ushort csar0; /* 0x00 */
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ushort res1;
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uint csmr0; /* 0x04 */
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uint cscr0; /* 0x08 */
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ushort csar1; /* 0x0c */
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ushort res2;
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uint csmr1; /* 0x10 */
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uint cscr1; /* 0x14 */
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ushort csar2; /* 0x18 */
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ushort res3;
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uint csmr2; /* 0x1c */
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uint cscr2; /* 0x20 */
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ushort csar3; /* 0x24 */
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ushort res4;
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uint csmr3; /* 0x28 */
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uint cscr3; /* 0x2c */
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ushort csar4; /* 0x30 */
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ushort res5;
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uint csmr4; /* 0x34 */
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uint cscr4; /* 0x38 */
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ushort csar5; /* 0x3c */
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ushort res6;
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uint csmr5; /* 0x40 */
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uint cscr5; /* 0x44 */
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} flexbus8220_t;
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/*
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* GPIO registers
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*/
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typedef struct gpio
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{
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u32 out; /* 0x00 */
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u32 obs; /* 0x04 */
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u32 obc; /* 0x08 */
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u32 obt; /* 0x0c */
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u32 en; /* 0x10 */
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u32 ebs; /* 0x14 */
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u32 ebc; /* 0x18 */
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u32 ebt; /* 0x1c */
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u32 mc; /* 0x20 */
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u32 st; /* 0x24 */
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u32 intr; /* 0x28 */
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} gpio8220_t;
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/*
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* General Purpose Timer registers
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*/
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typedef struct gptimer
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{
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u8 OCPW;
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u8 OctIct;
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u8 Control;
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u8 Mode;
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u16 Prescl; /* Prescale */
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u16 Count; /* Count */
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u16 PwmWid; /* PWM Width */
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u8 PwmOp; /* Output Polarity */
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u8 PwmLd; /* Immediate Update */
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u16 Capture; /* Capture internal counter */
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u8 OvfPin; /* Ovf and Pin */
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u8 Int; /* Interrupts */
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} gptmr8220_t;
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/*
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* PSC registers
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*/
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typedef struct psc
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{
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u32 mr1_2; /* 0x00 Mode reg 1 & 2 */
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u32 sr_csr; /* 0x04 Status/Clock Select reg */
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u32 cr; /* 0x08 Command reg */
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u8 xmitbuf[4]; /* 0x0c Receive/Transmit Buffer */
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u32 ipcr_acr; /* 0x10 Input Port Change/Auxiliary Control reg */
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u32 isr_imr; /* 0x14 Interrupt Status/Mask reg */
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u32 ctur; /* 0x18 Counter Timer Upper reg */
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u32 ctlr; /* 0x1c Counter Timer Lower reg */
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u32 rsvd1[4]; /* 0x20 ... 0x2c */
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u32 ivr; /* 0x30 Interrupt Vector reg */
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u32 ipr; /* 0x34 Input Port reg */
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u32 opsetr; /* 0x38 Output Port Set reg */
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u32 opresetr; /* 0x3c Output Port Reset reg */
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u32 sicr; /* 0x40 PSC/IrDA control reg */
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u32 ircr1; /* 0x44 IrDA control reg 1*/
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u32 ircr2; /* 0x48 IrDA control reg 2*/
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u32 irsdr; /* 0x4c IrDA SIR Divide reg */
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u32 irmdr; /* 0x50 IrDA MIR Divide reg */
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u32 irfdr; /* 0x54 PSC IrDA FIR Divide reg */
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u32 rfnum; /* 0x58 RX-FIFO counter */
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u32 txnum; /* 0x5c TX-FIFO counter */
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u32 rfdata; /* 0x60 RX-FIFO data */
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u32 rfstat; /* 0x64 RX-FIFO status */
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u32 rfcntl; /* 0x68 RX-FIFO control */
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u32 rfalarm; /* 0x6c RX-FIFO alarm */
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u32 rfrptr; /* 0x70 RX-FIFO read pointer */
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u32 rfwptr; /* 0x74 RX-FIFO write pointer */
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u32 rflfrptr; /* 0x78 RX-FIFO last read frame pointer */
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u32 rflfwptr; /* 0x7c RX-FIFO last write frame pointer */
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u32 tfdata; /* 0x80 TX-FIFO data */
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u32 tfstat; /* 0x84 TX-FIFO status */
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u32 tfcntl; /* 0x88 TX-FIFO control */
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u32 tfalarm; /* 0x8c TX-FIFO alarm */
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u32 tfrptr; /* 0x90 TX-FIFO read pointer */
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u32 tfwptr; /* 0x94 TX-FIFO write pointer */
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u32 tflfrptr; /* 0x98 TX-FIFO last read frame pointer */
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u32 tflfwptr; /* 0x9c TX-FIFO last write frame pointer */
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} psc8220_t;
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/*
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* Interrupt Controller registers
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*/
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typedef struct interrupt_controller {
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} intctl8220_t;
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/* Fast controllers
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*/
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/*
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* I2C registers
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*/
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typedef struct i2c
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{
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u8 adr; /* 0x00 */
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u8 res1[3];
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u8 fdr; /* 0x04 */
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u8 res2[3];
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u8 cr; /* 0x08 */
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u8 res3[3];
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u8 sr; /* 0x0C */
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u8 res4[3];
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u8 dr; /* 0x10 */
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u8 res5[3];
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u32 reserved0; /* 0x14 */
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u32 reserved1; /* 0x18 */
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u32 reserved2; /* 0x1c */
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u8 icr; /* 0x20 */
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u8 res6[3];
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} i2c8220_t;
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/*
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* Port Configuration Registers
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*/
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typedef struct pcfg
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{
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uint pcfg0; /* 0x00 */
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uint pcfg1; /* 0x04 */
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uint pcfg2; /* 0x08 */
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uint pcfg3; /* 0x0c */
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} pcfg8220_t;
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/* ...and the whole thing wrapped up....
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*/
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typedef struct immap {
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sysconf8220_t im_sysconf; /* System Configuration */
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memctl8220_t im_memctl; /* Memory Controller */
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xlbarb8220_t im_xlbarb; /* XLB Arbitration */
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psc8220_t im_psc; /* PSC controller */
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flexbus8220_t im_fb; /* FlexBus Controller */
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i2c8220_t im_i2c; /* I2C control/status */
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pcfg8220_t im_pcfg; /* Port configuration */
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} immap_t;
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#endif /* __IMMAP_MPC8220__ */
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