465 lines
16 KiB
C
465 lines
16 KiB
C
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/*
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* Copyright (C) 2004 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*
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* Support for Interphase iSPAN Communications Controllers
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* (453x and others). Tested on 4532.
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*
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* Derived from iSPAN 4539 port (iphase4539) by
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* Wolfgang Grandegger <wg@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc8260.h>
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#include <asm/io.h>
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/*
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* I/O Ports configuration table
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*
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* If conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
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#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
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#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
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/* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
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/* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
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/* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
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/* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
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/* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
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/* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
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/* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
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/* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
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/* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
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/* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
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/* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
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/* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
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/* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
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/* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
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/* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
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/* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
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/* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
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/* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
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/* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
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/* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
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/* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
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/* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 SMTXD */
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/* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 SMRXD */
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/* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
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/* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
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/* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
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/* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
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/* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
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/* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
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/* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
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/* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
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},
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/* Port B */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
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/* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
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/* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
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/* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
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/* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
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/* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
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/* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
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/* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
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/* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
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/* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
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/* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
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/* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
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/* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
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/* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
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/* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
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/* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
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/* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
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/* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
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/* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
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/* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
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/* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
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/* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
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/* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
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/* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
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/* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
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/* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
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/* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
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/* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
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/* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
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/* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
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/* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
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/* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
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/* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
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/* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
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/* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
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/* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
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/* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
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/* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
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/* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
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/* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
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/* PC18 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Rx Clock (CLK14) */
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/* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
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/* PC16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Tx Clock (CLK16) */
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/* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
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/* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
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/* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
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/* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
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/* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
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/* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
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/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
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/* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
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/* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
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/* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
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/* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
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/* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
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/* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
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/* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
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/* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
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/* PC0 */ { 0, 0, 0, 0, 0, 0 } /* PC0 */
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
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/* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
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/* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
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/* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
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/* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
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/* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
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/* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
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/* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
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/* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
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/* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
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/* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
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/* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
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/* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
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/* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPICLK */
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/* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMOSI */
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/* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMISO */
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/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
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/* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* MII MDIO */
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/* PD12 */ { 1, 0, 0, 1, 0, 0 }, /* MII MDC */
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
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/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 SMTXD */
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/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 SMRXD */
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/* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
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/* PD6 */ { CFG_FCC3, 0, 0, 1, 0, 1 }, /* MII PHY Reset */
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/* PD5 */ { CFG_FCC3, 0, 0, 1, 0, 0 }, /* MII PHY Enable */
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/* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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}
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};
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#define PSPAN_ADDR 0xF0020000
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#define EEPROM_REG 0x408
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#define EEPROM_READ_CMD 0xA000
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#define PSPAN_WRITE(a,v) \
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*((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio()
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#define PSPAN_READ(a) \
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*((volatile unsigned long *)(PSPAN_ADDR+(a)))
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static int seeprom_read (int addr, uchar * data, int size)
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{
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ulong val, cmd;
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int i;
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for (i = 0; i < size; i++) {
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cmd = EEPROM_READ_CMD;
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cmd |= ((addr + i) << 24) & 0xff000000;
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/* Wait for ACT to authorize write */
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while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
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eieio ();
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/* Write command */
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PSPAN_WRITE (EEPROM_REG, cmd);
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/* Wait for data to be valid */
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while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
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eieio ();
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/* Do it twice, first read might be erratic */
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while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
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eieio ();
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/* Read error */
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if (val & 0x00000040) {
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return -1;
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} else {
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data[i] = (val >> 16) & 0xff;
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}
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}
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return 0;
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}
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/***************************************************************
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* We take some basic Hardware Configuration Parameter from the
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* Serial EEPROM conected to the PSpan bridge. We keep it as
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* simple as possible.
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*/
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#ifdef DEBUG
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static int hwc_flash_size (void)
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{
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uchar byte;
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if (!seeprom_read (0x40, &byte, sizeof (byte))) {
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switch ((byte >> 2) & 0x3) {
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case 0x1:
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return 0x0400000;
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break;
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case 0x2:
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return 0x0800000;
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break;
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case 0x3:
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return 0x1000000;
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default:
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return 0x0100000;
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}
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}
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return -1;
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}
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static int hwc_local_sdram_size (void)
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{
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uchar byte;
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if (!seeprom_read (0x40, &byte, sizeof (byte))) {
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switch ((byte & 0x03)) {
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case 0x1:
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return 0x0800000;
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case 0x2:
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return 0x1000000;
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default:
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return 0; /* not present */
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}
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}
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return -1;
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}
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#endif /* DEBUG */
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static int hwc_main_sdram_size (void)
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{
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||
|
|
uchar byte;
|
||
|
|
|
||
|
|
if (!seeprom_read (0x41, &byte, sizeof (byte))) {
|
||
|
|
return 0x1000000 << ((byte >> 5) & 0x7);
|
||
|
|
}
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int hwc_serial_number (void)
|
||
|
|
{
|
||
|
|
int sn = -1;
|
||
|
|
|
||
|
|
if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) {
|
||
|
|
sn = cpu_to_le32 (sn);
|
||
|
|
}
|
||
|
|
return sn;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int hwc_mac_address (char *str)
|
||
|
|
{
|
||
|
|
char mac[6];
|
||
|
|
|
||
|
|
if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) {
|
||
|
|
sprintf (str, "%02X:%02X:%02X:%02X:%02X:%02X",
|
||
|
|
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
|
||
|
|
} else {
|
||
|
|
strcpy (str, "ERROR");
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int hwc_manufact_date (char *str)
|
||
|
|
{
|
||
|
|
uchar byte;
|
||
|
|
int value;
|
||
|
|
|
||
|
|
if (seeprom_read (0x92, &byte, sizeof (byte)))
|
||
|
|
goto out;
|
||
|
|
value = byte;
|
||
|
|
if (seeprom_read (0x93, &byte, sizeof (byte)))
|
||
|
|
goto out;
|
||
|
|
value += byte << 8;
|
||
|
|
sprintf (str, "%02d/%02d/%04d",
|
||
|
|
value & 0x1F, (value >> 5) & 0xF,
|
||
|
|
1980 + ((value >> 9) & 0x1FF));
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
out:
|
||
|
|
strcpy (str, "ERROR");
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int hwc_board_type (char **str)
|
||
|
|
{
|
||
|
|
ushort id = 0;
|
||
|
|
|
||
|
|
if (seeprom_read (7, (uchar *) & id, sizeof (id)) == 0) {
|
||
|
|
switch (id) {
|
||
|
|
case 0x9080:
|
||
|
|
*str = "4532-002";
|
||
|
|
break;
|
||
|
|
case 0x9081:
|
||
|
|
*str = "4532-001";
|
||
|
|
break;
|
||
|
|
case 0x9082:
|
||
|
|
*str = "4532-000";
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
*str = "Unknown";
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
*str = "Unknown";
|
||
|
|
}
|
||
|
|
|
||
|
|
return id;
|
||
|
|
}
|
||
|
|
|
||
|
|
long int initdram (int board_type)
|
||
|
|
{
|
||
|
|
long maxsize = hwc_main_sdram_size();
|
||
|
|
|
||
|
|
#if !defined(CFG_RAMBOOT) && !defined(CFG_USE_FIRMWARE)
|
||
|
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||
|
|
volatile memctl8260_t *memctl = &immap->im_memctl;
|
||
|
|
volatile uchar *base;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
immap->im_siu_conf.sc_ppc_acr = 0x00000026;
|
||
|
|
immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
|
||
|
|
immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
|
||
|
|
immap->im_siu_conf.sc_lcl_acr = 0x00000000;
|
||
|
|
immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
|
||
|
|
immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
|
||
|
|
immap->im_siu_conf.sc_tescr1 = 0x00004000;
|
||
|
|
immap->im_siu_conf.sc_ltescr1 = 0x00004000;
|
||
|
|
|
||
|
|
memctl->memc_mptpr = CFG_MPTPR;
|
||
|
|
|
||
|
|
/* Initialise 60x bus SDRAM */
|
||
|
|
base = (uchar *)(CFG_SDRAM_BASE | 0x110);
|
||
|
|
memctl->memc_psrt = CFG_PSRT;
|
||
|
|
memctl->memc_or1 = CFG_60x_OR;
|
||
|
|
memctl->memc_br1 = CFG_SDRAM_BASE | CFG_60x_BR;
|
||
|
|
|
||
|
|
memctl->memc_psdmr = CFG_PSDMR | 0x28000000;
|
||
|
|
*base = 0xFF;
|
||
|
|
memctl->memc_psdmr = CFG_PSDMR | 0x08000000;
|
||
|
|
for (i = 0; i < 8; i++)
|
||
|
|
*base = 0xFF;
|
||
|
|
memctl->memc_psdmr = CFG_PSDMR | 0x18000000;
|
||
|
|
*base = 0xFF;
|
||
|
|
memctl->memc_psdmr = CFG_PSDMR | 0x40000000;
|
||
|
|
|
||
|
|
/* Initialise local bus SDRAM */
|
||
|
|
base = (uchar *)CFG_LSDRAM_BASE;
|
||
|
|
memctl->memc_lsrt = CFG_LSRT;
|
||
|
|
memctl->memc_or2 = CFG_LOC_OR;
|
||
|
|
memctl->memc_br2 = CFG_LSDRAM_BASE | CFG_LOC_BR;
|
||
|
|
|
||
|
|
memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
|
||
|
|
*base = 0xFF;
|
||
|
|
memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
|
||
|
|
for (i = 0; i < 8; i++)
|
||
|
|
*base = 0xFF;
|
||
|
|
memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
|
||
|
|
*base = 0xFF;
|
||
|
|
memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
|
||
|
|
|
||
|
|
/* We must be able to test a location outsize the maximum legal size
|
||
|
|
* to find out THAT we are outside; but this address still has to be
|
||
|
|
* mapped by the controller. That means, that the initial mapping has
|
||
|
|
* to be (at least) twice as large as the maximum expected size.
|
||
|
|
*/
|
||
|
|
maxsize = (~(memctl->memc_or1 & BRx_BA_MSK) + 1) / 2;
|
||
|
|
|
||
|
|
maxsize = get_ram_size((long *)(memctl->memc_br1 & BRx_BA_MSK), maxsize);
|
||
|
|
|
||
|
|
memctl->memc_or1 |= ~(maxsize - 1);
|
||
|
|
|
||
|
|
if (maxsize != hwc_main_sdram_size())
|
||
|
|
puts("Oops: memory test has not found all memory!\n");
|
||
|
|
#endif /* !CFG_RAMBOOT && !CFG_USE_FIRMWARE */
|
||
|
|
|
||
|
|
/* Return total RAM size (size of 60x SDRAM) */
|
||
|
|
return maxsize;
|
||
|
|
}
|
||
|
|
|
||
|
|
int checkboard(void)
|
||
|
|
{
|
||
|
|
char string[32], *id;
|
||
|
|
|
||
|
|
hwc_manufact_date(string);
|
||
|
|
hwc_board_type(&id);
|
||
|
|
printf("Board: Interphase iSPAN %s (#%d %s)\n",
|
||
|
|
id, hwc_serial_number(), string);
|
||
|
|
#ifdef DEBUG
|
||
|
|
printf("Manufacturing date: %s\n", string);
|
||
|
|
printf("Serial number : %d\n", hwc_serial_number());
|
||
|
|
printf("FLASH size : %d MB\n", hwc_flash_size() >> 20);
|
||
|
|
printf("Main SDRAM size : %d MB\n", hwc_main_sdram_size() >> 20);
|
||
|
|
printf("Local SDRAM size : %d MB\n", hwc_local_sdram_size() >> 20);
|
||
|
|
hwc_mac_address(string);
|
||
|
|
printf("MAC address : %s\n", string);
|
||
|
|
#endif
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int misc_init_r(void)
|
||
|
|
{
|
||
|
|
char *s, str[32];
|
||
|
|
int num;
|
||
|
|
|
||
|
|
if ((s = getenv("serial#")) == NULL &&
|
||
|
|
(num = hwc_serial_number()) != -1) {
|
||
|
|
sprintf(str, "%06d", num);
|
||
|
|
setenv("serial#", str);
|
||
|
|
}
|
||
|
|
if ((s = getenv("ethaddr")) == NULL && hwc_mac_address(str) == 0) {
|
||
|
|
setenv("ethaddr", str);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|