284 lines
8.3 KiB
C
284 lines
8.3 KiB
C
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/*
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2001
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* James Dougherty (jfd@cs.stanford.edu)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* PCI Configuration space access support for MPC824x/MPC107 PCI Bridge
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*/
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#include <common.h>
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#include <mpc824x.h>
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#include <pci.h>
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#include "mousse.h"
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/*
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* Promise ATA/66 support.
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*/
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#define XFER_PIO_4 0x0C /* 0000|1100 */
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#define XFER_PIO_3 0x0B /* 0000|1011 */
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#define XFER_PIO_2 0x0A /* 0000|1010 */
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#define XFER_PIO_1 0x09 /* 0000|1001 */
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#define XFER_PIO_0 0x08 /* 0000|1000 */
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#define XFER_PIO_SLOW 0x00 /* 0000|0000 */
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/* Promise Regs */
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#define REG_A 0x01
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#define REG_B 0x02
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#define REG_C 0x04
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#define REG_D 0x08
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void
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pdc202xx_decode_registers (unsigned char registers, unsigned char value)
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{
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unsigned char bit = 0, bit1 = 0, bit2 = 0;
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switch(registers) {
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case REG_A:
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bit2 = 0;
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printf(" A Register ");
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if (value & 0x80) printf("SYNC_IN ");
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if (value & 0x40) printf("ERRDY_EN ");
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if (value & 0x20) printf("IORDY_EN ");
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if (value & 0x10) printf("PREFETCH_EN ");
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if (value & 0x08) { printf("PA3 ");bit2 |= 0x08; }
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if (value & 0x04) { printf("PA2 ");bit2 |= 0x04; }
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if (value & 0x02) { printf("PA1 ");bit2 |= 0x02; }
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if (value & 0x01) { printf("PA0 ");bit2 |= 0x01; }
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printf("PIO(A) = %d ", bit2);
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break;
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case REG_B:
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bit1 = 0;bit2 = 0;
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printf(" B Register ");
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if (value & 0x80) { printf("MB2 ");bit1 |= 0x80; }
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if (value & 0x40) { printf("MB1 ");bit1 |= 0x40; }
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if (value & 0x20) { printf("MB0 ");bit1 |= 0x20; }
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printf("DMA(B) = %d ", bit1 >> 5);
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if (value & 0x10) printf("PIO_FORCED/PB4 ");
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if (value & 0x08) { printf("PB3 ");bit2 |= 0x08; }
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if (value & 0x04) { printf("PB2 ");bit2 |= 0x04; }
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if (value & 0x02) { printf("PB1 ");bit2 |= 0x02; }
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if (value & 0x01) { printf("PB0 ");bit2 |= 0x01; }
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printf("PIO(B) = %d ", bit2);
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break;
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case REG_C:
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bit2 = 0;
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printf(" C Register ");
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if (value & 0x80) printf("DMARQp ");
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if (value & 0x40) printf("IORDYp ");
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if (value & 0x20) printf("DMAR_EN ");
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if (value & 0x10) printf("DMAW_EN ");
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if (value & 0x08) { printf("MC3 ");bit2 |= 0x08; }
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if (value & 0x04) { printf("MC2 ");bit2 |= 0x04; }
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if (value & 0x02) { printf("MC1 ");bit2 |= 0x02; }
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if (value & 0x01) { printf("MC0 ");bit2 |= 0x01; }
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printf("DMA(C) = %d ", bit2);
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break;
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case REG_D:
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printf(" D Register ");
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break;
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default:
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return;
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}
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printf("\n %s ", (registers & REG_D) ? "DP" :
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(registers & REG_C) ? "CP" :
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(registers & REG_B) ? "BP" :
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(registers & REG_A) ? "AP" : "ERROR");
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for (bit=128;bit>0;bit/=2)
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printf("%s", (value & bit) ? "1" : "0");
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printf("\n");
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}
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/*
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* Promise ATA/66 Support: configure Promise ATA66 card in specified mode.
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*/
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int
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pdc202xx_tune_chipset (pci_dev_t dev, int drive, unsigned char speed)
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{
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unsigned short drive_conf;
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int err = 0;
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unsigned char drive_pci, AP, BP, CP, DP;
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unsigned char TA = 0, TB = 0;
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switch (drive) {
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case 0: drive_pci = 0x60; break;
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case 1: drive_pci = 0x64; break;
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case 2: drive_pci = 0x68; break;
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case 3: drive_pci = 0x6c; break;
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default: return -1;
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}
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pci_read_config_word(dev, drive_pci, &drive_conf);
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pci_read_config_byte(dev, (drive_pci), &AP);
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pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
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pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
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pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
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if ((AP & 0x0F) || (BP & 0x07)) {
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/* clear PIO modes of lower 8421 bits of A Register */
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pci_write_config_byte(dev, (drive_pci), AP & ~0x0F);
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pci_read_config_byte(dev, (drive_pci), &AP);
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/* clear PIO modes of lower 421 bits of B Register */
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pci_write_config_byte(dev, (drive_pci)|0x01, BP & ~0x07);
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pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
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pci_read_config_byte(dev, (drive_pci), &AP);
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pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
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}
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pci_read_config_byte(dev, (drive_pci), &AP);
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pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
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pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
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switch(speed) {
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case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
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case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
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case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
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case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
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case XFER_PIO_0:
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default: TA = 0x09; TB = 0x13; break;
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}
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pci_write_config_byte(dev, (drive_pci), AP|TA);
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pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
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pci_read_config_byte(dev, (drive_pci), &AP);
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pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
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pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
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pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
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#ifdef PDC202XX_DEBUG
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pdc202xx_decode_registers(REG_A, AP);
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pdc202xx_decode_registers(REG_B, BP);
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pdc202xx_decode_registers(REG_C, CP);
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pdc202xx_decode_registers(REG_D, DP);
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#endif
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return err;
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}
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/*
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* Show/Init PCI devices on the specified bus number.
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*/
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void pci_mousse_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
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{
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unsigned int line;
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switch(PCI_DEV(dev)) {
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case 0x0d:
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line = 0x00000101;
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break;
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case 0x0e:
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default:
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line = 0x00000303;
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break;
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}
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pci_write_config_dword(dev, PCI_INTERRUPT_LINE, line);
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}
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void pci_mousse_setup_pdc202xx(struct pci_controller *hose, pci_dev_t dev,
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struct pci_config_table *_)
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{
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unsigned short vendorId;
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unsigned int mbar0, cmd;
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int bar, a;
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pci_read_config_word(dev, PCI_VENDOR_ID, &vendorId);
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if(vendorId == PCI_VENDOR_ID_PROMISE || vendorId == PCI_VENDOR_ID_CMD){
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/* PDC 202xx card is handled differently, it is a bootable
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* device and needs all 5 MBAR's configured
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*/
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for(bar = 0; bar < 5; bar++){
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pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0);
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, ~0);
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pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0);
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#ifdef DEBUG
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printf(" ATA_bar[%d] = %dbytes\n", bar,
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~(mbar0 & PCI_BASE_ADDRESS_MEM_MASK) + 1);
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#endif
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}
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/* Program all BAR's */
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PROMISE_MBAR0);
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, PROMISE_MBAR1);
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, PROMISE_MBAR2);
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, PROMISE_MBAR3);
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, PROMISE_MBAR4);
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, PROMISE_MBAR5);
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for(bar = 0; bar < 5; bar++){
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pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0);
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#ifdef DEBUG
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printf(" ATA_bar[%d]@0x%x\n", bar, mbar0);
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#endif
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}
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/* Enable ROM Expansion base */
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pci_write_config_dword(dev, PCI_ROM_ADDRESS, PROMISE_MBAR5|1);
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/* Io enable, Memory enable, master enable */
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pci_read_config_dword(dev, PCI_COMMAND, &cmd);
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cmd &= ~0xffff0000;
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cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
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pci_write_config_dword(dev, PCI_COMMAND, cmd);
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/* Breath some life into the controller */
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for( a = 0; a < 4; a++)
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pdc202xx_tune_chipset(dev, a, XFER_PIO_0);
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}
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}
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static struct pci_config_table pci_sandpoint_config_table[] = {
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0e, 0x00,
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pci_mousse_setup_pdc202xx },
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#ifndef CONFIG_PCI_PNP
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0d, 0x00,
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pci_cfgfunc_config_device, {PCI_ENET_IOADDR,
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PCI_ENET_MEMADDR,
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER}},
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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pci_cfgfunc_config_device, {PCI_SLOT_IOADDR,
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PCI_SLOT_MEMADDR,
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER}},
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#endif
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{ }
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};
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struct pci_controller hose = {
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config_table: pci_sandpoint_config_table,
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fixup_irq: pci_mousse_fixup_irq,
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};
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void pci_init_board(void)
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{
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pci_mpc824x_init(&hose);
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}
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