307 lines
9.1 KiB
C
307 lines
9.1 KiB
C
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* (C) Copyright 2003
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* Texas Instruments, <www.ti.com>
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* Kshitij Gupta <Kshitij@ti.com>
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*
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* Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if defined(CONFIG_OMAP1610)
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#include <./configs/omap1510.h>
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#endif
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#ifdef CONFIG_CS_AUTOBOOT
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unsigned long omap_flash_base;
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#endif
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void flash__init (void);
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void ether__init (void);
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void set_muxconf_regs (void);
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void peripheral_power_enable (void);
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#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
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static inline void delay (unsigned long loops)
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{
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0" (loops));
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}
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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if (machine_is_omap_h2())
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gd->bd->bi_arch_number = MACH_TYPE_OMAP_H2;
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else if (machine_is_omap_innovator())
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gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR;
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else
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gd->bd->bi_arch_number = MACH_TYPE_OMAP_GENERIC;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0x10000100;
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/* Configure MUX settings */
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set_muxconf_regs ();
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peripheral_power_enable ();
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/* this speeds up your boot a quite a bit. However to make it
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* work, you need make sure your kernel startup flush bug is fixed.
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* ... rkw ...
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*/
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icache_enable ();
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flash__init ();
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ether__init ();
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return 0;
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}
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int misc_init_r (void)
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{
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/* currently empty */
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return (0);
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}
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/******************************
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Routine:
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Description:
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******************************/
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void flash__init (void)
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{
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#define EMIFS_GlB_Config_REG 0xfffecc0c
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unsigned int regval;
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#ifdef CONFIG_CS_AUTOBOOT
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/* Check swapping of CS0 and CS3, set flash base accordingly */
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omap_flash_base = ((*((u32 *)OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ?
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PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1;
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#endif
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regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
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/* Turn off write protection for flash devices. */
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regval = regval | 0x0001;
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*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
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}
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/*************************************************************
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Routine:ether__init
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Description: take the Ethernet controller out of reset and wait
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for the EEPROM load to complete.
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*************************************************************/
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void ether__init (void)
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{
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#define ETH_CONTROL_REG 0x0400030b
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#ifdef CONFIG_H2_OMAP1610
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#define LAN_RESET_REGISTER 0x0400001c
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/* The debug board on which the lan chip resides may not be powered
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* ON at the same time as the OMAP chip. So wait in a loop until the
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* lan reset register (on the debug board) is available (powered on)
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* and reset the lan chip.
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*/
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*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
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do {
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*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
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udelay (3);
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} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
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do {
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*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
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udelay (3);
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} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
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#endif
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*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
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udelay (3);
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}
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/******************************
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Routine:
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Description:
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******************************/
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int dram_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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/******************************************************
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Routine: set_muxconf_regs
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Description: Setting up the configuration Mux registers
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specific to the hardware
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*******************************************************/
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void set_muxconf_regs (void)
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{
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volatile unsigned int *MuxConfReg;
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/* set each registers to its reset value; */
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
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/* setup for UART1 */
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*MuxConfReg &= ~(0x02000000); /* bit 25 */
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/* setup for UART2 */
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*MuxConfReg &= ~(0x01000000); /* bit 24 */
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/* Disable Uwire CS Hi-Z */
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*MuxConfReg |= 0x08000000;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
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*MuxConfReg = 0x00000000;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
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*MuxConfReg = 0x00000000;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
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*MuxConfReg = 0x00000000;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
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/*setup mux for UART3 */
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*MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */
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*MuxConfReg &= ~0x0000003e;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
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*MuxConfReg = 0x00000000;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
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/* Disable Uwire CS Hi-Z */
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*MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
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/* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */
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/* hardware will actually use TX and RTS based on bit 25 in */
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/* FUNC_MUX_CTRL_0. I told you this thing was screwy! */
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*MuxConfReg |= 0x00201000;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
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*MuxConfReg = 0x00000000;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
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*MuxConfReg = 0x00000000;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
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/* setup for UART2 */
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/* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */
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/* hardware will actually use TX and RTS based on bit 24 in */
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/* FUNC_MUX_CTRL_0. */
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*MuxConfReg |= 0x09000000;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
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*MuxConfReg = 0x00000000;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
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*MuxConfReg = 0x00000000;
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/* mux setup for SD/MMC driver */
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
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*MuxConfReg &= 0xFFFE0FFF;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
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*MuxConfReg = 0x00000000;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
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/* bit 13 for MMC2 XOR_CLK */
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*MuxConfReg &= ~(0x00002000);
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/* bit 29 for UART 1 */
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*MuxConfReg &= ~(0x00002000);
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
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/* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
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*MuxConfReg |= 0x000C0000;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
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*MuxConfReg &= ~(0x00000070);
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*MuxConfReg &= ~(0x00000008);
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*MuxConfReg |= 0x00000003;
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*MuxConfReg |= 0x00000180;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
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/* bit 17, software controls VBUS */
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*MuxConfReg &= ~(0x00020000);
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/* Enable USB 48 and 12M clocks */
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*MuxConfReg |= 0x00000200;
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*MuxConfReg &= ~(0x00000180);
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/*2.75V for MMCSDIO1 */
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
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*MuxConfReg = 0x00001FE7;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
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*MuxConfReg = 0x00000000;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
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*MuxConfReg = 0x00000000;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
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*MuxConfReg = 0x00000000;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
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*MuxConfReg = 0x00000000;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
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*MuxConfReg = 0x00000000;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
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*MuxConfReg = 0x00000000;
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/* Turn on UART2 48 MHZ clock */
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
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*MuxConfReg |= 0x40000000;
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
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/* setup for USB VBus detection OMAP161x */
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*MuxConfReg |= 0x00040000; /* bit 18 */
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
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/* PullUps for SD/MMC driver */
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*MuxConfReg |= ~(0xFFFE0FFF);
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MuxConfReg =
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(volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
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*MuxConfReg = COMP_MODE_ENABLE;
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}
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/******************************************************
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Routine: peripheral_power_enable
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Description: Enable the power for UART1
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*******************************************************/
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void peripheral_power_enable (void)
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{
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#define UART1_48MHZ_ENABLE ((unsigned short)0x0200)
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#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834)
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*SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
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}
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