376 lines
14 KiB
C
376 lines
14 KiB
C
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/*
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* (C) Copyright 2004
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/omap2420.h>
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#include <asm/io.h>
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#include <asm/arch/bits.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/clocks.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/sys_info.h>
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/************************************************************
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* sdelay() - simple spin loop. Will be constant time as
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* its generally used in 12MHz bypass conditions only. This
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* is necessary until timers are accessible.
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*
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* not inline to increase chances its in cache when called
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*************************************************************/
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void sdelay (unsigned long loops)
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{
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__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0" (loops));
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}
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/*********************************************************************************
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* prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default).
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* -- called from SRAM, or Flash (using temp SRAM stack).
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*********************************************************************************/
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void prcm_init(void)
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{
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u32 div;
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void (*f_lock_pll) (u32, u32, u32, u32);
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extern void *_end_vect, *_start;
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f_lock_pll = (void *)((u32)&_end_vect - (u32)&_start + SRAM_VECT_CODE);
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__raw_writel(0, CM_FCLKEN1_CORE); /* stop all clocks to reduce ringing */
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__raw_writel(0, CM_FCLKEN2_CORE); /* may not be necessary */
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__raw_writel(0, CM_ICLKEN1_CORE);
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__raw_writel(0, CM_ICLKEN2_CORE);
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__raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); /* set DPLL out */
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__raw_writel(MPU_DIV, CM_CLKSEL_MPU); /* set MPU divider */
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__raw_writel(DSP_DIV, CM_CLKSEL_DSP); /* set dsp and iva dividers */
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__raw_writel(GFX_DIV, CM_CLKSEL_GFX); /* set gfx dividers */
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div = BUS_DIV;
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__raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/Vlnc/SSi dividers */
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sdelay(1000);
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if(running_in_sram()){
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/* If running fully from SRAM this is OK. The Flash bus drops out for just a little.
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* but then comes back. If running from Flash this sequence kills you, thus you need
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* to run it using CONFIG_PARTIAL_SRAM.
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*/
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__raw_writel(MODE_BYPASS_FAST, CM_CLKEN_PLL); /* go to bypass, fast relock */
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wait_on_value(BIT0|BIT1, BIT0, CM_IDLEST_CKGEN, LDELAY); /* wait till in bypass */
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sdelay(1000);
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/* set clock selection and dpll dividers. */
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__raw_writel(DPLL_VAL, CM_CLKSEL1_PLL); /* set pll for target rate */
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__raw_writel(COMMIT_DIVIDERS, PRCM_CLKCFG_CTRL); /* commit dividers */
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sdelay(10000);
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__raw_writel(DPLL_LOCK, CM_CLKEN_PLL); /* enable dpll */
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sdelay(10000);
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wait_on_value(BIT0|BIT1, BIT1, CM_IDLEST_CKGEN, LDELAY); /*wait for dpll lock */
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}else if(running_in_flash()){
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/* if running from flash, need to jump to small relocated code area in SRAM.
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* This is the only safe spot to do configurations from.
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*/
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(*f_lock_pll)(PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK, CM_IDLEST_CKGEN);
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}
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__raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL); /* enable apll */
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wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY); /* wait for apll lock */
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sdelay(1000);
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}
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/**************************************************************************
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* make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
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* command line mem=xyz use all memory with out discontigious support
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* compiled in. Could do it at the ATAG, but there really is two banks...
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* Called as part of 2nd phase DDR init.
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**************************************************************************/
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void make_cs1_contiguous(void)
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{
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u32 size, a_add_low, a_add_high;
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size = get_sdr_cs_size(SDRC_CS0_OSET);
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size /= SZ_32M; /* find size to offset CS1 */
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a_add_high = (size & 3) << 8; /* set up low field */
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a_add_low = (size & 0x3C) >> 2; /* set up high field */
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__raw_writel((a_add_high|a_add_low),SDRC_CS_CFG);
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}
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/********************************************************
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* mem_ok() - test used to see if timings are correct
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* for a part. Helps in gussing which part
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* we are currently using.
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*******************************************************/
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u32 mem_ok(void)
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{
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u32 val1, val2;
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u32 pattern = 0x12345678;
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__raw_writel(0x0,OMAP2420_SDRC_CS0+0x400); /* clear pos A */
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__raw_writel(pattern, OMAP2420_SDRC_CS0); /* pattern to pos B */
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__raw_writel(0x0,OMAP2420_SDRC_CS0+4); /* remove pattern off the bus */
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val1 = __raw_readl(OMAP2420_SDRC_CS0+0x400); /* get pos A value */
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val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */
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if ((val1 != 0) || (val2 != pattern)) /* see if pos A value changed*/
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return(0);
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else
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return(1);
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}
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/********************************************************
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* sdrc_init() - init the sdrc chip selects CS0 and CS1
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* - early init routines, called from flash or
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* SRAM.
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*******************************************************/
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void sdrc_init(void)
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{
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#define EARLY_INIT 1
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do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); /* only init up first bank here */
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}
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/*************************************************************************
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* do_sdrc_init(): initialize the SDRAM for use.
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* -called from low level code with stack only.
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* -code sets up SDRAM timing and muxing for 2422 or 2420.
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* -optimal settings can be placed here, or redone after i2c
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* inspection of board info
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*
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* This is a bit ugly, but should handle all memory moduels
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* used with the H4. The first time though this code from s_init()
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* we configure the first chip select. Later on we come back and
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* will configure the 2nd chip select if it exists.
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*
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**************************************************************************/
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void do_sdrc_init(u32 offset, u32 early)
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{
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u32 cpu, dllen=0, rev, common=0, cs0=0, pmask=0, pass_type, mtype;
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sdrc_data_t *sdata; /* do not change type */
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u32 a, b, r;
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static const sdrc_data_t sdrc_2422 =
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{
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H4_2422_SDRC_SHARING, H4_2422_SDRC_MDCFG_0_DDR, 0 , H4_2422_SDRC_ACTIM_CTRLA_0,
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H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL, H4_2422_SDRC_MR_0_DDR,
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0, H4_2422_SDRC_DLLAB_CTRL
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};
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static const sdrc_data_t sdrc_2420 =
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{
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H4_2420_SDRC_SHARING, H4_2420_SDRC_MDCFG_0_DDR, H4_2420_SDRC_MDCFG_0_SDR,
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H4_2420_SDRC_ACTIM_CTRLA_0, H4_2420_SDRC_ACTIM_CTRLB_0,
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H4_2420_SDRC_RFR_CTRL, H4_2420_SDRC_MR_0_DDR, H4_2420_SDRC_MR_0_SDR,
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H4_2420_SDRC_DLLAB_CTRL
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};
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if (offset == SDRC_CS0_OSET)
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cs0 = common = 1; /* int regs shared between both chip select */
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cpu = get_cpu_type();
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rev = get_cpu_rev();
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/* warning generated, though code generation is correct. this may bite later,
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* but is ok for now. there is only so much C code you can do on stack only
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* operation.
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*/
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if (cpu == CPU_2422){
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sdata = (sdrc_data_t *)&sdrc_2422;
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pass_type = STACKED;
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} else{
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sdata = (sdrc_data_t *)&sdrc_2420;
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pass_type = IP_DDR;
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}
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__asm__ __volatile__("": : :"memory"); /* limit compiler scope */
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/* u-boot is compiled to run in DDR or SRAM at 8xxxxxxx or 4xxxxxxx.
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* If we are running in flash prior to relocation and we use data
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* here which is not pc relative we need to get the address correct.
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* We need to find the current flash mapping to dress up the initial
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* pointer load. As long as this is const data we should be ok.
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*/
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if((early) && running_in_flash()){
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sdata = (sdrc_data_t *)(((u32)sdata & 0x0003FFFF) | get_gpmc0_base());
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/* NOR internal boot offset is 0x4000 from xloader signature */
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if(running_from_internal_boot())
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sdata = (sdrc_data_t *)((u32)sdata + 0x4000);
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}
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if (!early && (((mtype = get_mem_type()) == DDR_COMBO)||(mtype == DDR_STACKED))) {
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if(mtype == DDR_COMBO){
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pmask = BIT2;/* combo part has a shared CKE signal, can't use feature */
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pass_type = COMBO_DDR; /* CS1 config */
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__raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, SDRC_POWER);
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}
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if(rev != CPU_2420_2422_ES1) /* for es2 and above smooth things out */
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make_cs1_contiguous();
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}
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next_mem_type:
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if (common) { /* do a SDRC reset between types to clear regs*/
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__raw_writel(SOFTRESET, SDRC_SYSCONFIG); /* reset sdrc */
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wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);/* wait till reset done set */
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__raw_writel(0, SDRC_SYSCONFIG); /* clear soft reset */
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__raw_writel(sdata->sdrc_sharing, SDRC_SHARING);
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#ifdef POWER_SAVE
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__raw_writel(__raw_readl(SMS_SYSCONFIG)|SMART_IDLE, SMS_SYSCONFIG);
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__raw_writel(sdata->sdrc_sharing|SMART_IDLE, SDRC_SHARING);
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__raw_writel((__raw_readl(SDRC_POWER)|BIT6), SDRC_POWER);
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#endif
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}
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if ((pass_type == IP_DDR) || (pass_type == STACKED)) /* (IP ddr-CS0),(2422-CS0/CS1) */
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__raw_writel(sdata->sdrc_mdcfg_0_ddr, SDRC_MCFG_0+offset);
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else if (pass_type == COMBO_DDR){ /* (combo-CS0/CS1) */
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__raw_writel(H4_2420_COMBO_MDCFG_0_DDR,SDRC_MCFG_0+offset);
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} else if (pass_type == IP_SDR){ /* ip sdr-CS0 */
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__raw_writel(sdata->sdrc_mdcfg_0_sdr, SDRC_MCFG_0+offset);
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}
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a = sdata->sdrc_actim_ctrla_0;
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b = sdata->sdrc_actim_ctrlb_0;
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r = sdata->sdrc_dllab_ctrl;
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/* work around ES1 DDR issues */
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if((pass_type != IP_SDR) && (rev == CPU_2420_2422_ES1)){
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a = H4_242x_SDRC_ACTIM_CTRLA_0_ES1;
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b = H4_242x_SDRC_ACTIM_CTRLB_0_ES1;
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r = H4_242x_SDRC_RFR_CTRL_ES1;
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}
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if (cs0) {
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__raw_writel(a, SDRC_ACTIM_CTRLA_0);
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__raw_writel(b, SDRC_ACTIM_CTRLB_0);
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} else {
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__raw_writel(a, SDRC_ACTIM_CTRLA_1);
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__raw_writel(b, SDRC_ACTIM_CTRLB_1);
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}
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__raw_writel(r, SDRC_RFR_CTRL+offset);
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/* init sequence for mDDR/mSDR using manual commands (DDR is a bit different) */
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__raw_writel(CMD_NOP, SDRC_MANUAL_0+offset);
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sdelay(5000); /* susposed to be 100us per design spec for mddr/msdr */
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__raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0+offset);
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__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
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__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
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/*
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* CSx SDRC Mode Register
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* Burst length = (4 - DDR) (2-SDR)
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* Serial mode
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* CAS latency = x
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*/
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if(pass_type == IP_SDR)
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__raw_writel(sdata->sdrc_mr_0_sdr, SDRC_MR_0+offset);
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else
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__raw_writel(sdata->sdrc_mr_0_ddr, SDRC_MR_0+offset);
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/* NOTE: ES1 242x _BUG_ DLL + External Bandwidth fix*/
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if (rev == CPU_2420_2422_ES1){
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dllen = (BIT0|BIT3); /* es1 clear both bit0 and bit3 */
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__raw_writel((__raw_readl(SMS_CLASS_ARB0)|BURSTCOMPLETE_GROUP7)
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,SMS_CLASS_ARB0);/* enable bust complete for lcd */
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}
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else
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dllen = BIT0|BIT1; /* es2, clear bit0, and 1 (set phase to 72) */
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/* enable & load up DLL with good value for 75MHz, and set phase to 90
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* ES1 recommends 90 phase, ES2 recommends 72 phase.
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*/
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if (common && (pass_type != IP_SDR)) {
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__raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLA_CTRL);
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__raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen), SDRC_DLLA_CTRL);
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__raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLB_CTRL);
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__raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen) , SDRC_DLLB_CTRL);
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}
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sdelay(90000);
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if(mem_ok())
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return; /* STACKED, other configued type */
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++pass_type; /* IPDDR->COMBODDR->IPSDR for CS0 */
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goto next_mem_type;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*****************************************************
|
||
|
|
* gpmc_init(): init gpmc bus
|
||
|
|
* Init GPMC for x16, MuxMode (SDRAM in x32).
|
||
|
|
* This code can only be executed from SRAM or SDRAM.
|
||
|
|
*****************************************************/
|
||
|
|
void gpmc_init(void)
|
||
|
|
{
|
||
|
|
u32 mux=0, mtype, mwidth, rev, tval;
|
||
|
|
|
||
|
|
rev = get_cpu_rev();
|
||
|
|
if (rev == CPU_2420_2422_ES1)
|
||
|
|
tval = 1;
|
||
|
|
else
|
||
|
|
tval = 0; /* disable bit switched meaning */
|
||
|
|
|
||
|
|
/* global settings */
|
||
|
|
__raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
|
||
|
|
__raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
|
||
|
|
__raw_writel(tval, GPMC_TIMEOUT_CONTROL);/* timeout disable */
|
||
|
|
#ifdef CFG_NAND_BOOT
|
||
|
|
__raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */
|
||
|
|
#else
|
||
|
|
__raw_writel(0x111, GPMC_CONFIG); /* set nWP, disable limited addr */
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* discover bus connection from sysboot */
|
||
|
|
if (is_gpmc_muxed() == GPMC_MUXED)
|
||
|
|
mux = BIT9;
|
||
|
|
mtype = get_gpmc0_type();
|
||
|
|
mwidth = get_gpmc0_width();
|
||
|
|
|
||
|
|
/* setup cs0 */
|
||
|
|
__raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */
|
||
|
|
sdelay(1000);
|
||
|
|
|
||
|
|
#ifdef CFG_NAND_BOOT
|
||
|
|
__raw_writel(H4_24XX_GPMC_CONFIG1_0|mtype|mwidth, GPMC_CONFIG1_0);
|
||
|
|
#else
|
||
|
|
__raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef PRCM_CONFIG_III
|
||
|
|
__raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
|
||
|
|
#endif
|
||
|
|
__raw_writel(H4_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
|
||
|
|
__raw_writel(H4_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
|
||
|
|
#ifdef PRCM_CONFIG_III
|
||
|
|
__raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
|
||
|
|
__raw_writel(H4_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
|
||
|
|
#endif
|
||
|
|
__raw_writel(H4_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);/* enable new mapping */
|
||
|
|
sdelay(2000);
|
||
|
|
|
||
|
|
/* setup cs1 */
|
||
|
|
__raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */
|
||
|
|
sdelay(1000);
|
||
|
|
__raw_writel(H4_24XX_GPMC_CONFIG1_1|mux, GPMC_CONFIG1_1);
|
||
|
|
__raw_writel(H4_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
|
||
|
|
__raw_writel(H4_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
|
||
|
|
__raw_writel(H4_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
|
||
|
|
__raw_writel(H4_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
|
||
|
|
__raw_writel(H4_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
|
||
|
|
__raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */
|
||
|
|
sdelay(2000);
|
||
|
|
}
|