396 lines
8.8 KiB
ArmAsm
396 lines
8.8 KiB
ArmAsm
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/*
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* Board specific setup info
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*
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* (C) Copyright 2003-2004
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*
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* Texas Instruments, <www.ti.com>
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* Kshitij Gupta <Kshitij@ti.com>
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*
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* Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
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*
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* Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited
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* (http://www.mpc-data.co.uk)
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*
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* TODO : Tidy up and change to use system register defines
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* from omap730.h where possible.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#if defined(CONFIG_OMAP730)
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#include <./configs/omap730.h>
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#endif
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_TEXT_BASE:
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.word TEXT_BASE /* sdram load addr from config.mk */
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.globl lowlevel_init
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lowlevel_init:
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/* Save callers address in r11 - r11 must never be modified */
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mov r11, lr
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/*------------------------------------------------------*
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*mask all IRQs by setting all bits in the INTMR default*
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*------------------------------------------------------*/
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mov r1, #0xffffffff
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ldr r0, =REG_IHL1_MIR
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str r1, [r0]
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ldr r0, =REG_IHL2_MIR
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str r1, [r0]
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/*------------------------------------------------------*
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* Set up ARM CLM registers (IDLECT1) *
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*------------------------------------------------------*/
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ldr r0, REG_ARM_IDLECT1
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ldr r1, VAL_ARM_IDLECT1
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str r1, [r0]
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/*------------------------------------------------------*
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* Set up ARM CLM registers (IDLECT2) *
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*------------------------------------------------------*/
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ldr r0, REG_ARM_IDLECT2
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ldr r1, VAL_ARM_IDLECT2
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str r1, [r0]
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/*------------------------------------------------------*
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* Set up ARM CLM registers (IDLECT3) *
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*------------------------------------------------------*/
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ldr r0, REG_ARM_IDLECT3
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ldr r1, VAL_ARM_IDLECT3
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str r1, [r0]
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mov r1, #0x01 /* PER_EN bit */
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ldr r0, REG_ARM_RSTCT2
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strh r1, [r0] /* CLKM; Peripheral reset. */
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/* Set CLKM to Sync-Scalable */
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/* I supposedly need to enable the dsp clock before switching */
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mov r1, #0x1000
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ldr r0, REG_ARM_SYSST
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strh r1, [r0]
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mov r0, #0x400
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1:
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subs r0, r0, #0x1 /* wait for any bubbles to finish */
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bne 1b
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ldr r1, VAL_ARM_CKCTL
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ldr r0, REG_ARM_CKCTL
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strh r1, [r0]
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/* a few nops to let settle */
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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/* setup DPLL 1 */
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/* Ramp up the clock to 96Mhz */
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ldr r1, VAL_DPLL1_CTL
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ldr r0, REG_DPLL1_CTL
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strh r1, [r0]
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ands r1, r1, #0x10 /* Check if PLL is enabled. */
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beq lock_end /* Do not look for lock if BYPASS selected */
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2:
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ldrh r1, [r0]
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ands r1, r1, #0x01 /* Check the LOCK bit.*/
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beq 2b /* loop until bit goes hi. */
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lock_end:
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/*------------------------------------------------------*
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* Turn off the watchdog during init... *
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*------------------------------------------------------*/
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ldr r0, REG_WATCHDOG
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ldr r1, WATCHDOG_VAL1
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str r1, [r0]
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ldr r1, WATCHDOG_VAL2
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str r1, [r0]
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ldr r0, REG_WSPRDOG
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ldr r1, WSPRDOG_VAL1
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str r1, [r0]
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ldr r0, REG_WWPSDOG
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watch1Wait:
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ldr r1, [r0]
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tst r1, #0x10
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bne watch1Wait
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ldr r0, REG_WSPRDOG
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ldr r1, WSPRDOG_VAL2
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str r1, [r0]
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ldr r0, REG_WWPSDOG
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watch2Wait:
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ldr r1, [r0]
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tst r1, #0x10
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bne watch2Wait
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/* Set memory timings corresponding to the new clock speed */
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/* Check execution location to determine current execution location
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* and branch to appropriate initialization code.
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*/
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/* Compare physical SDRAM base & current execution location. */
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and r0, pc, #0xF0000000
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/* Compare. */
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cmp r0, #0
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/* Skip over EMIF-fast initialization if running from SDRAM. */
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bne skip_sdram
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/*
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* Delay for SDRAM initialization.
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*/
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mov r3, #0x1800 /* value should be checked */
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3:
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subs r3, r3, #0x1 /* Decrement count */
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bne 3b
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ldr r0, REG_SDRAM_CONFIG
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ldr r1, SDRAM_CONFIG_VAL
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str r1, [r0]
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ldr r0, REG_SDRAM_MRS_LEGACY
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ldr r1, SDRAM_MRS_VAL
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str r1, [r0]
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skip_sdram:
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common_tc:
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/* slow interface */
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ldr r1, VAL_TC_EMIFS_CS0_CONFIG
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ldr r0, REG_TC_EMIFS_CS0_CONFIG
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str r1, [r0] /* Chip Select 0 */
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ldr r1, VAL_TC_EMIFS_CS1_CONFIG
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ldr r0, REG_TC_EMIFS_CS1_CONFIG
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str r1, [r0] /* Chip Select 1 */
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ldr r1, VAL_TC_EMIFS_CS2_CONFIG
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ldr r0, REG_TC_EMIFS_CS2_CONFIG
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str r1, [r0] /* Chip Select 2 */
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ldr r1, VAL_TC_EMIFS_CS3_CONFIG
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ldr r0, REG_TC_EMIFS_CS3_CONFIG
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str r1, [r0] /* Chip Select 3 */
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/* 48MHz clock request for UART1 */
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ldr r1, PERSEUS2_CONFIG_BASE
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ldrh r0, [r1, #CONFIG_PCC_CONF]
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orr r0, r0, #CONF_MOD_UART1_CLK_MODE_R
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strh r0, [r1, #CONFIG_PCC_CONF]
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/* Initialize public and private rheas
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* - set access factor 2 on both rhea / strobe
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* - disable write buffer on strb0, enable write buffer on strb1
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*/
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ldr R0, REG_RHEA_PUB_CTL
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ldr R1, REG_RHEA_PRIV_CTL
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ldr R2, VAL_RHEA_CTL
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strh R2, [R0]
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strh R2, [R1]
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mov R3, #2 /* disable write buffer on strb0, enable write buffer on strb1 */
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strh R3, [R0, #0x08] /* arm rhea control reg */
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strh R3, [R1, #0x08]
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/* enable IRQ and FIQ */
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mrs r4, CPSR
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bic r4, r4, #IRQ_MASK
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bic r4, r4, #FIQ_MASK
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msr CPSR, r4
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/* set TAP CONF to TRI EMULATION */
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ldr r1, [r0, #CONFIG_MODE2]
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bic r1, r1, #0x18
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orr r1, r1, #0x10
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str r1, [r0, #CONFIG_MODE2]
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/* set tdbgen to 1 */
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ldr r0, PERSEUS2_CONFIG_BASE
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ldr r1, [r0, #CONFIG_MODE1]
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mov r2, #0x10000
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orr r1, r1, r2
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str r1, [r0, #CONFIG_MODE1]
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#ifdef CONFIG_P2_OMAP1610
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/* inserting additional 2 clock cycle hold time for LAN */
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ldr r0, REG_TC_EMIFS_CS1_ADVANCED
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ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
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str r1, [r0]
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#endif
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/* Start MPU Timer 1 */
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ldr r0, REG_MPU_LOAD_TIMER
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ldr r1, VAL_MPU_LOAD_TIMER
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str r1, [r0]
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ldr r0, REG_MPU_CNTL_TIMER
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ldr r1, VAL_MPU_CNTL_TIMER
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str r1, [r0]
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/* back to arch calling code */
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mov pc, r11
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/* the literal pools origin */
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.ltorg
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REG_TC_EMIFS_CONFIG: /* 32 bits */
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.word 0xfffecc0c
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REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
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.word 0xfffecc10
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REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
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.word 0xfffecc14
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REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
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.word 0xfffecc18
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REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
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.word 0xfffecc1c
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#ifdef CONFIG_P2_OMAP730
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REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
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.word 0xfffecc54
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#endif
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/* MPU clock/reset/power mode control registers */
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REG_ARM_CKCTL: /* 16 bits */
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.word 0xfffece00
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REG_ARM_IDLECT3: /* 16 bits */
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.word 0xfffece24
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REG_ARM_IDLECT2: /* 16 bits */
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.word 0xfffece08
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REG_ARM_IDLECT1: /* 16 bits */
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.word 0xfffece04
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REG_ARM_RSTCT2: /* 16 bits */
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.word 0xfffece14
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REG_ARM_SYSST: /* 16 bits */
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.word 0xfffece18
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/* DPLL control registers */
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REG_DPLL1_CTL: /* 16 bits */
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.word 0xfffecf00
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/* Watch Dog register */
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/* secure watchdog stop */
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REG_WSPRDOG:
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.word 0xfffeb048
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/* watchdog write pending */
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REG_WWPSDOG:
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.word 0xfffeb034
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WSPRDOG_VAL1:
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.word 0x0000aaaa
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WSPRDOG_VAL2:
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.word 0x00005555
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/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
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counter @8192 rows, 10 ns, 8 burst */
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REG_SDRAM_CONFIG:
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.word 0xfffecc20
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REG_SDRAM_MRS_LEGACY:
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.word 0xfffecc24
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REG_WATCHDOG:
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.word 0xfffec808
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REG_MPU_LOAD_TIMER:
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.word 0xfffec600
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REG_MPU_CNTL_TIMER:
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.word 0xfffec500
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/* Public and private rhea bridge registers definition */
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REG_RHEA_PUB_CTL:
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.word 0xFFFECA00
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REG_RHEA_PRIV_CTL:
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.word 0xFFFED300
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/* EMIFF SDRAM Configuration register
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- self refresh disable
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- auto refresh enabled
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- SDRAM type 64 Mb, 16 bits bus 4 banks
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- power down enabled
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- SDRAM clock disabled
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*/
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SDRAM_CONFIG_VAL:
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.word 0x0C017DF4
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/* Burst full page length ; cas latency = 3 */
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SDRAM_MRS_VAL:
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.word 0x00000037
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VAL_ARM_CKCTL:
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.word 0x6505
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VAL_DPLL1_CTL:
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.word 0x3412
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#ifdef CONFIG_P2_OMAP730
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VAL_TC_EMIFS_CS0_CONFIG:
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.word 0x0000FFF3
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VAL_TC_EMIFS_CS1_CONFIG:
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.word 0x00004278
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VAL_TC_EMIFS_CS2_CONFIG:
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.word 0x00004278
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VAL_TC_EMIFS_CS3_CONFIG:
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.word 0x00004278
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VAL_TC_EMIFS_CS1_ADVANCED:
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.word 0x00000022
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#endif
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VAL_ARM_IDLECT1:
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.word 0x00000400
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VAL_ARM_IDLECT2:
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.word 0x00000886
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VAL_ARM_IDLECT3:
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.word 0x00000015
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WATCHDOG_VAL1:
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.word 0x000000f5
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WATCHDOG_VAL2:
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.word 0x000000a0
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VAL_MPU_LOAD_TIMER:
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.word 0xffffffff
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VAL_MPU_CNTL_TIMER:
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.word 0xffffffa1
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||
|
|
|
||
|
|
VAL_RHEA_CTL:
|
||
|
|
.word 0xFF22
|
||
|
|
|
||
|
|
/* Config Register vals */
|
||
|
|
PERSEUS2_CONFIG_BASE:
|
||
|
|
.word 0xFFFE1000
|
||
|
|
|
||
|
|
.equ CONFIG_PCC_CONF, 0xB4
|
||
|
|
.equ CONFIG_MODE1, 0x10
|
||
|
|
.equ CONFIG_MODE2, 0x14
|
||
|
|
.equ CONF_MOD_UART1_CLK_MODE_R, 0x0A
|
||
|
|
|
||
|
|
/* misc values */
|
||
|
|
.equ IRQ_MASK, 0x80 /* IRQ mask value */
|
||
|
|
.equ FIQ_MASK, 0x40 /* FIQ mask value */
|