133 lines
2.7 KiB
C
133 lines
2.7 KiB
C
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/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include "fpga_serial.h"
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#include "hardware.h"
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#include "pcippc2.h"
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/* 8 data, 1 stop, no parity
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*/
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#define LCRVAL 0x03
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/* RTS/DTR
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*/
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#define MCRVAL 0x03
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/* Clear & enable FIFOs
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*/
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#define FCRVAL 0x07
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static void fpga_serial_wait (void);
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static void fpga_serial_print (char c);
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void fpga_serial_init (int baudrate)
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{
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int clock_divisor = 115200 / baudrate;
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out8 (FPGA (INT, SERIAL_CONFIG), 0x24);
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iobarrier_rw ();
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fpga_serial_wait ();
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out8 (UART (IER), 0);
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out8 (UART (LCR), LCRVAL | 0x80);
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iobarrier_rw ();
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out8 (UART (DLL), clock_divisor & 0xff);
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out8 (UART (DLM), clock_divisor >> 8);
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iobarrier_rw ();
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out8 (UART (LCR), LCRVAL);
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iobarrier_rw ();
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out8 (UART (MCR), MCRVAL);
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out8 (UART (FCR), FCRVAL);
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iobarrier_rw ();
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}
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void fpga_serial_putc (char c)
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{
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if (c) {
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fpga_serial_print (c);
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}
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}
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void fpga_serial_puts (const char *s)
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{
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while (*s) {
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fpga_serial_print (*s++);
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}
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}
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int fpga_serial_getc (void)
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{
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while ((in8 (UART (LSR)) & 0x01) == 0);
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return in8 (UART (RBR));
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}
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int fpga_serial_tstc (void)
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{
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return (in8 (UART (LSR)) & 0x01) != 0;
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}
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void fpga_serial_setbrg (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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int clock_divisor = 115200 / gd->baudrate;
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fpga_serial_wait ();
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out8 (UART (LCR), LCRVAL | 0x80);
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iobarrier_rw ();
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out8 (UART (DLL), clock_divisor & 0xff);
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out8 (UART (DLM), clock_divisor >> 8);
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iobarrier_rw ();
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out8 (UART (LCR), LCRVAL);
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iobarrier_rw ();
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}
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static void fpga_serial_wait (void)
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{
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while ((in8 (UART (LSR)) & 0x40) == 0);
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}
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static void fpga_serial_print (char c)
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{
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if (c == '\n') {
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while ((in8 (UART (LSR)) & 0x20) == 0);
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out8 (UART (THR), '\r');
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iobarrier_rw ();
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}
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while ((in8 (UART (LSR)) & 0x20) == 0);
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out8 (UART (THR), c);
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iobarrier_rw ();
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if (c == '\n') {
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fpga_serial_wait ();
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}
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}
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