218 lines
11 KiB
C
218 lines
11 KiB
C
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/*
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* I/O Port configuration table
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*
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* If conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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#ifdef SKIP
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#undef SKIP
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#endif
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#ifdef CONF
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#undef CONF
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#endif
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#ifdef DIN
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#undef DIN
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#endif
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#ifdef DOUT
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#undef DOUT
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#endif
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#ifdef GPIO
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#undef GPIO
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#endif
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#ifdef SPEC
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#undef SPEC
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#endif
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#ifdef ACTV
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#undef ACTV
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#endif
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#ifdef OPEN
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#undef OPEN
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#endif
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#define SKIP 0 /* SKIP over this port */
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#define CONF 1 /* CONFiguration the port */
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#define DIN 0 /* PDIRx 0: Direction IN */
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#define DOUT 1 /* PDIRx 1: Direction OUT */
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#define GPIO 0 /* PPARx 0: General Purpose I/O */
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#define SPEC 1 /* PPARx 1: dedicated to a peripheral function, */
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/* i.e. the port has a SPECial use. */
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#define ACTV 0 /* PODRx 0: ACTiVely driven as an output */
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#define OPEN 1 /* PODRx 1: OPEN-drain driver */
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS8* */
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/* PA30 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS7* */
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/* PA29 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS6* */
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/* PA28 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS5* */
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/* PA27 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS4* */
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/* PA26 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS3* */
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/* PA25 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS2* */
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/* PA24 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS1* */
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/* PA23 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* ODIS_EN* */
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/* PA22 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* STLED2_EN* */
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/* PA21 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* STLED1_EN* */
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/* PA20 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PLED3_EN* */
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/* PA19 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PLED2_EN* */
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/* PA18 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* PLED1_EN* */
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/* PA17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PA16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* DAC_RST* */
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/* PA15 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH34SDATA_PU */
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/* PA14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH12SDATA_PU */
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/* PA13 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SLRCLK_EN* */
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/* PA12 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4ACDC* */
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/* PA11 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4TEDS* */
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/* PA10 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4XTDS* */
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/* PA9 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3ACDC* */
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/* PA8 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3TEDS* */
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/* PA7 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3XTDS* */
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/* PA6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2ACDC* */
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/* PA5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2TEDS* */
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/* PA4 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2XTDS* */
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/* PA3 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PA2 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_1ACDC* */
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/* PA1 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_1TEDS* */
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/* PA0 */ { CONF, GPIO, 0, DOUT, ACTV, 1 } /* MTRX_1XTDS* */
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},
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TX_ER */
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/* PB30 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RX_DV */
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/* PB29 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* FCC2 MII_TX_EN */
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/* PB28 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RX_ER */
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/* PB27 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_COL */
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/* PB26 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_CRS */
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/* PB25 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD3 */
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/* PB24 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD2 */
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/* PB23 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD1 */
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/* PB22 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD0 */
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/* PB21 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD0 */
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/* PB20 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD1 */
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/* PB19 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD2 */
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/* PB18 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD3 */
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/* PB17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PB16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PB15 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PB14 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RXDC1, BSDATA_ADC12 */
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/* PB13 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PB12 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RSYNCC1, LRCLK */
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/* PB11 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1TXDD1, RSDATA_DAC12 */
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/* PB10 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RXDD1, BSDATA_ADC34 */
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/* PB9 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PB8 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RSYNCD1, LRCLK */
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/* PB7 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PB6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* XCITE_SHDN */
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/* PB5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* TRIGGER */
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/* PB4 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* ARM */
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/* PB3 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
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/* PB2 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
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/* PB1 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
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/* PB0 */ { SKIP, GPIO, 0, DIN, ACTV, 0 } /* pin doesn't exist */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PC30 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PC29 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK3, MCLK */
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/* PC28 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* TOUT2* */
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#ifdef QQQ
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/* PC28 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TOUT2* */
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#endif
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/* PC27 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK5, SCLK */
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/* PC26 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PC25 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK7, SCLK */
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/* PC24 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PC23 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK9, MCLK */
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/* PC22 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PC21 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* BRGO6 (LRCLK) */
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/* PC20 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PC19 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK13, MII_RXCLK */
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/* PC18 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK14, MII_TXCLK */
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/* PC17 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* BRGO8 (SCLK) */
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/* PC16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PC15 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* SMC2_TX */
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/* PC14 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PC13 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PC12 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB3 */
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/* PC11 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PC10 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* TDM_STRB4 */
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/* PC9 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN3 */
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/* PC8 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN2 */
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/* PC7 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN1 */
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/* PC6 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PC5 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN2* */
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/* PC4 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN1* */
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/* PC3 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* MUSH_STAT */
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/* PC2 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* OUTDRV_STAT */
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/* PC1 */ { CONF, GPIO, 0, DOUT, OPEN, 1 }, /* PHY_MDIO */
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/* PC0 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PHY_MDC */
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* SCC1_RX */
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/* PD30 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SCC1_TX */
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/* PD29 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PD28 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PD27 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PD26 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PD25 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PD24 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PD23 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PD22 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PD21 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PD20 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SPI_ADC_CS* */
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/* PD19 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SPI_DAC_CS* */
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#if defined(CONFIG_SOFT_SPI)
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/* PD18 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* SPI_CLK */
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/* PD17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* SPI_MOSI */
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/* PD16 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* SPI_MISO */
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#else
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/* PD18 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SPI_CLK */
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/* PD17 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SPI_MOSI */
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/* PD16 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* SPI_MISO */
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#endif
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#if defined(CONFIG_SOFT_I2C)
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/* PD15 */ { CONF, GPIO, 0, DOUT, OPEN, 1 }, /* I2C_SDA */
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/* PD14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* I2C_SCL */
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#else
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#if defined(CONFIG_HARD_I2C)
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/* PD15 */ { CONF, SPEC, 1, DIN, OPEN, 0 }, /* I2C_SDA */
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/* PD14 */ { CONF, SPEC, 1, DIN, OPEN, 0 }, /* I2C_SCL */
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#else /* normal I/O port pins */
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/* PD15 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* I2C_SDA */
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/* PD14 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* I2C_SCL */
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#endif
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#endif
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/* PD13 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB1 */
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/* PD12 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB2 */
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/* PD11 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
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/* PD10 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* BRGO4 (MCLK) */
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/* PD9 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* SMC1_TX */
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/* PD8 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* SMC1_RX */
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/* PD7 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */
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/* PD6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */
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/* PD5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */
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/* PD4 */ { CONF, SPEC, 1, DOUT, ACTV, 1 }, /* SMC2_RX */
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/* PD3 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
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/* PD2 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
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/* PD1 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */
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/* PD0 */ { SKIP, GPIO, 0, DIN, ACTV, 0 } /* pin doesn't exist */
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}
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};
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