146 lines
4.1 KiB
ArmAsm
146 lines
4.1 KiB
ArmAsm
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/*
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* Copyright (C) 2001, 2002 ETC s.r.o.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
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* 02111-1307, USA.
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*
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* Written by Marcel Telka <marcel@telka.sk>, 2001, 2002.
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* Changes for U-Boot Peter Figuli <peposh@etc.sk>, 2003.
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*
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* This file is taken from OpenWinCE project hosted by SourceForge.net
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*
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* Documentation:
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* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
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* Developer's Manual", February 2002, Order Number: 278522-001
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* [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P",
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* Revision 1.0, February 2002
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* [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)",
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* Revision 1.0, February 2002
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*
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/pxa-regs.h>
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.globl lowlevel_init
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lowlevel_init:
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mov r10, lr
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/* setup memory - see 6.12 in [1]
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* Step 1 - wait 200 us
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*/
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mov r0,#0x2700 /* wait 200 us @ 99.5 MHz */
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1: subs r0, r0, #1
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bne 1b
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/* TODO: complete step 1 for Synchronous Static memory*/
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ldr r0, =0x48000000 /* MC_BASE */
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/* step 1.a - setup MSCx
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*/
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ldr r1, =0x000012B3 /* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */
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str r1, [r0, #0x8] /* MSC0_OFFSET */
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/* step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI
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* see AUTO REFRESH chapter in section D. in [2] and in [3]
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* DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633
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* DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633
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* TODO: complete for Synchronous Static memory
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*/
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ldr r1, [r0, #4] /* MDREFR_OFFSET */
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ldr r2, =0x01000FFF /* MDREFR_K1FREE | MDREFR_DRI_MASK */
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bic r1, r1, r2
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#if defined( WEP_SDRAM_K4S281633 )
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orr r1, r1, #48 /* MDREFR_DRI(48) */
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#elif defined( WEP_SDRAM_K4S561633 )
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orr r1, r1, #24 /* MDREFR_DRI(24) */
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#else
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#error SDRAM chip is not defined
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#endif
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str r1, [r0, #4] /* MDREFR_OFFSET */
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/* Step 2 - only for Synchronous Static memory (TODO)
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*
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* Step 3 - same as step 4
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*
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* Step 4
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*
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* Step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2
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*/
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orr r1, r1, #0x00010000 /* MDREFR_K1RUN */
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bic r1, r1, #0x00020000 /* MDREFR_K1DB2 */
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str r1, [r0, #4] /* MDREFR_OFFSET */
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/* Step 4.b - clear MDREFR:SLFRSH */
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bic r1, r1, #0x00400000 /* MDREFR_SLFRSH */
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str r1, [r0, #4] /* MDREFR_OFFSET */
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/* Step 4.c - set MDREFR:E1PIN */
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orr r1, r1, #0x00008000 /* MDREFR_E1PIN */
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str r1, [r0, #4] /* MDREFR_OFFSET */
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/* Step 4.d - automatically done
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*
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* Steps 4.e and 4.f - configure SDRAM
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*/
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#if defined( WEP_SDRAM_K4S281633 )
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ldr r1, =0x00000AA8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0 */
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#elif defined( WEP_SDRAM_K4S561633 )
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ldr r1, =0x00000AC8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0 */
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#else
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#error SDRAM chip is not defined
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#endif
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str r1, [r0, #0] /* MDCNFG_OFFSET */
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/* Step 5 - wait at least 200 us for SDRAM
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* see section B. in [2]
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*/
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mov r2,#0x2700 /* wait 200 us @ 99.5 MHz */
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1: subs r2, r2, #1
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bne 1b
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/* Step 6 - after reset dcache is disabled, so automatically done
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*
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* Step 7 - eight refresh cycles
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*/
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mov r2, #0xA0000000
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ldr r3, [r2]
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ldr r3, [r2]
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ldr r3, [r2]
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ldr r3, [r2]
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ldr r3, [r2]
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ldr r3, [r2]
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ldr r3, [r2]
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ldr r3, [r2]
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/* Step 8 - we don't need dcache now
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*
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* Step 9 - enable SDRAM partition 0
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*/
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orr r1, r1, #1 /* MDCNFG_DE0 */
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str r1, [r0, #0] /* MDCNFG_OFFSET */
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/* Step 10 - write MDMRS */
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mov r1, #0
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str r1, [r0, #0x40] /* MDMRS_OFFSET */
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/* Step 11 - optional (TODO) */
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mov pc,r10
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